MMA8451Q - Double Pulse Detection

[brandonkuhn]

I am using the MMA8451Q on the FRDM-KL25Z board. Using the example code from 6.1 from AN4072, I can correctly receive interrupts for single pulse detection. But I am having problems with double pulse detection which originated when trying to do both single and double pulse detection as per example 6.3.

If consider just double pulse detection for a moment and use the example code from 6.2, I can also receive interrupts, but reading the PULSE_SRC register doesn't return the values I expect. From 6.2 example code, when I read back PULSE_SRC, I was expecting to see bits EA and DPE set, but the register reads back as 0x00. I then amended the PULSE_CFG register and also set the ELE bit - to latch values into the PULSE_SRC register (in case I wasn't reading this before the latency expired), but then found that no interrupts would occur expect for once immediately after I finished the configuration routine. I also then read the PULSE_SRC register before I left the config routine in case the interrupt had already trigger, but this didn't make any difference. That was expect because when moving from Standby Mode to Active Mode (the last action of the configuration routine) the PULSE_SRC register should be cleared automatically anyway according to note (2) on Page20 of the datasheet.

Where am I going wrong?

Thanks

Brandon

[reyes]

Hi Brandon Kuhn,

I would recommend you to check bit3 (SRC_PULSE bit) of register 0x0C (INT_SOURCE) instead of PULSE_SCR register (0x22) for single/double pulse detection. Logic ‘1’ on SRC_PULSE bit indicates that an interrupt was generated due to single and/or double pulse event. Logic ‘0’ indicates that no pulse event was detected. This bit is asserted whenever “EA” bit in the PULSE_SRC is asserted and the interrupt has been enabled. This bit is cleared by reading the PULSE_SRC register.

One thing that I think is not mentioned in section6.3 of the AN4072 and that I would recommend you to set is the Pulse_LPF_EN bit (Bit 4) on the High-Pass Filter Register (0x0F).

Can you please send me your configuration for the complete PULSE registers (0x0F, 0x21, 0x23, 0x24, 0x25, 0x26, 0x27 and 0x28), please?

This are the configuration values I would recommend for the Pulse registers:

0x0F: 0x10

0x21: 0x3F

0x23: 0x20

0x24: 0x20

0x25: 0x2A

0x26: 0x14

0x27: 0x14

0x28: 0x28

I hope this helps.

Have a great day,
Jose Reyes

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[brandonkuhn]

Hi Jose,

Thanks for your reply. These are the settings based on example 6.2 from AN4072 for double tap only:

0x0F:     no setting entered, so default = 0x00

0x21:      0x2A          (I tried 0x6A to latch interrupts but it caused other problems)

0x23:      0x20

0x24:      0x20

0x25:      0x20          (changed from to get more sensitivity on z axis)

0x26:      0x30

0x27:      0x30

0x28:      0x28

I used the following settings initially to try detect single & double tap. I could receive the interrupt for single tap correctly, but I could never detect double tap. That is when I tried to detect double only (above). These are from example 6.3 in AN4072:

0x0F:     no setting entered, so default = 0x00

0x21:      0x3F

0x23:      0x20

0x24:      0x20

0x25:      0x40

0x26:      0x18

0x27:      0x28

0x28:      0x3C

I will try  your suggestion on the Low pass filter bit and advise. Your suggestion of checking the SRC_PULSE bit of INT_SOURCE won't show me the difference between a single and double pulse - only that a pulse interrupt has occurred. My ultimate goal was to tell the difference between single and double taps.

Some questions I have:

1. Why do you recommend this instead of the EA bit? I have to read the PULSE_SRC register anyway to clear interrupts so reading the EA bit is easier.

2. Using the first settings, I receive an interrupt for double tap (single tap does not trigger an interrupt), but the DPE bit in PULSE_SRC is never set (or the EA bit) - do you know why? This is the bit I need to check to tell the difference bewteen single & double tap for example 6.3.

3. I tried setting the ELE bit in PULSE_CFG (0x21), but after making this simple change I found the part never triggered any interrupts - do you know why?

Separate question out of interest:

If the the ELE bit in PULSE_CFG is set to 0 (flags not latched), do I still need to read the PULSE_SRC register to clear the flags or will the part just clear the interrupt after the latency perdiod?

Thanks for your help.

Regards

Brandon

[reyes]

Hi Brandom,

Answering to your questions:

1. You are correct, sorry, you should read PULSE_SRC Register in order to read if a single or double pulse was detected. But it’s important to mention that when the EA bit gets set while ELE = 1, all status bits (AxZ, AxY, AxZ, DPE, and PolX, PolY, PolZ) are frozen. Reading the PULSE_SRC register clears all bits. Reading the source register will clear the interrupt.

2. I do not understand what could be causing this problem, I just test the values from example 6.2 of AN4070 on my MMA8451Q and I didn’t have any problem: I received an interrupt for double tap (single tap does not trigger an interrupt) and both DPE bit and EA bit in PULSE_SRC were set.

And I also tested my MMA8451Q with the setting mentioned for single & double tap from your last update, and I didn’t found any problem, even without the LPF disabled (0x0F = 0x00).

3. I don’t know what would be the reason of this, the function of the ELE bit is to hold the contents of the status register until the status register is read.

4.If the ELE bit of the PULSE_CFG register is not set (0), the interrupt is kept high for the duration of the Latency window PULSE_LTCY.

Is just in case that the ELE bit is set (1), the source register values will remain static until the PULSE_SRC register is read.

This latency window applies either for single pulse or double pulse detection.

Have a great day,
Jose Reyes

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[brandonkuhn]

Hi Jose,

I found the problem. My external interrupt was configured to trigger in either rising/falling edge mode and this was obviously causing an issue between when receiving the interrupt and when reading the registers. Once the interrupt was configured for falling edge only, reading of the registers proved 100% correct and as expected.

Thanks for your help

Brandon