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The purpose of this document is to provide supportive information for selection of suitable LPDDR4, DDR4 and DDR3L devices that are supported by i.MX 8M family of processors to aid project feasibility assessment capabilities of customers that are evaluating the SoCs for usage in their products. It is strongly recommended to consult with NXP and the memory vendor the final choice of the memory part number to ensure that the device meets all the compatibility, availability, longevity and pricing requirements. Please note that some of the LPDDR4 devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low speed operation is planned in the use case, please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs available on NXP.com For any questions related to specific DRAM part numbers please contact the respective DRAM vendor. For any questions regarding the i.MX SoC please contact your support representative or enter a support ticket. LPDDR4 - maximum supported densities Please note that the SoCs only support memory devices that support either the LPDDR4 mode or support both LPDDR4 and LPDDR4X modes. Memory devices that support only the LPDDR4X mode are not supported. SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8M Quad 32-bit 32Gb/4GB dual rank, dual-channel device with 16-row addresses (R0-R15) 1, 2, 4 i.MX 8M Mini 32-bit 64Gb/8GB dual rank, dual-channel device with 17-row addresses (R0-R16) 1, 2 i.MX 8M Nano 16-bit 32Gb/4GB dual rank, single-channel device with 17-row addresses (R0-R16) 1, 2, 3, 12 i.MX 8M Plus 32-bit 64Gb/8GB dual rank, dual-channel device with 17-row addresses (R0-R16) 1, 2 LPDDR4 - list of validated memories Please note that the validation process is an ongoing effort - regular updates of the table are expected. Please contact NXP if a specific vendor or configuration is required. SoC Density Validated part number (vendor) Notes i.MX 8M Quad 24Gb/3GB MT53B768M32D4NQ-062 WT:B (Micron) 15 32Gb/4GB MT53D1024M32D4DT-046 AAT:D (Micron) 14 4Gb/512MB IS43LQ16256B-062BLI (ISSI) 5, 14 8Gb/1GB IS43LQ32256B-062BLI (ISSI) 5, 14 i.MX 8M Mini 16Gb/2GB MT53D512M32D2DS-053 WT:D (Micron) 15 16Gb/2GB M56Z16G32512A (ESMT) 5, 14 32Gb/4GB MT53E1G32D2FW-046 WT:A (Micron) 5, 14 64Gb/8GB MT53E2G32D4DT-046 AIT:A (Micron) 5, 14 32Gb/4GB B3221PM3BDGUI (Kingston) 5 i.MX 8M Nano 16Gb/2GB C1612PC2WDGTKR-U (Kingston) 15 32Gb/4GB MT53E2G32D4DT-046 AIT:A (Micron) 5, 13, 15 8Gb/1GB MT53D512M32D2DS-053 WT:D (Micron) 13, 15 i.MX 8M Plus 48Gb/6GB MT53E1536M32D4DT-046 WT:A (Micron) 15 64Gb/8GB MT53E2G32D4DE-046 AUT:C (Micron) 5, 14 LPDDR4 - list of incompatible devices Given the limitations mentioned in this document, the following memory devices were identified as incompatible with the particular SoCs as detailed in the following table: Memory vendor Part Number Density Incompatible SoCs Incompatibility reason Samsung K4FHE3S4HA-KU(H/F)CL 24Gb/3Gb i.MX 8M Quad The memory device requires 17th row address bit to function. Samsung K4UHE3S4AA-KU(H/F)CL K4UJE3D4AA-KU(H/F)CL 24Gb/3Gb 48Gb/6GB i.MX 8M Quad i.MX 8M Mini i.MX 8M Nano i.MX 8M Plus The memory device only supports the LPDDR4X mode. Samsung K4FCE3Q4HB-KU(H/F)CL K4UCE3Q4AB-KU(H/F)CL 64Gb/8GB i.MX 8M Quad i.MX 8M Mini i.MX 8M Nano i.MX 8M Plus A byte mode memory device. The memory device only supports the LPDDR4X mode. DDR4 - maximum supported densities SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8M Quad 32-bit 32Gb/4GB x16, 16Gb device with 1 bank group address, 17-row addresses and 10 column addresses 1, 6 i.MX 8M Mini 32-bit 64Gb/8GB x16, 16Gb device with 1 bank group address, 17-row addresses and 10 column addresses 1, 7 i.MX 8M Nano 16-bit 64Gb/8GB x8, 16Gb device with 2 bank group addresses, 17-row addresses and 10 column addresses 1, 8 i.MX 8M Plus 32-bit 64Gb/8GB x16, 16Gb device with 1 bank group address, 17-row addresses and 10 column addresses 1, 7 DDR4 - list of validated memories Please note that the validation process is an ongoing effort - regular updates of the table are expected. Please contact NXP if a specific vendor or configuration is required. SoC Density Validated part number (vendor) Notes i.MX 8M Quad 32Gb/4GB 4x MT40A512M16JY-083EAAT (Micron) 15 i.MX 8M Mini 16Gb/2GB 2x MT40A512M16LY-075:E (Micron) 15 i.MX 8M Nano 16Gb/2GB 1x MT40A1G16RC-062E:B (Micron) 15 i.MX 8M Plus 64Gb/8GB 4x MT40A1G16RC-062E:B (Micron) 15 16Gb/2GB NT5AD512M16C4-JRI (Nanya) 14 DDR3L - maximum supported densities SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8M Quad 32-bit 32Gb/4GB x16, 8Gb device with 16-row addresses and 10 column addresses 1, 9 i.MX 8M Mini 32-bit 64Gb/8GB x8, 8Gb device with 16-row addresses and 11 column addresses 1, 10 i.MX 8M Nano 16-bit 32Gb/4GB x8, 8Gb device with 16-row addresses and 11 column addresses 1, 11 i.MX 8M Plus i.MX 8M Plus does not support DDR3L DDR3L - list of validated memories Please note that the validation process is an ongoing effort - regular updates of the table are expected. Please contact NXP if a specific vendor or configuration is required. SoC Density Validated part number (vendor) Notes i.MX 8M Quad 16Gb/2GB 4x MT41K256M16TW-107 AAT (Micron) 14 i.MX 8M Mini 16Gb/2GB 4x MT41K256M16TW-107 AAT (Micron) 14 Note 1: The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, and on the JEDEC standards JESD209-4/JESD209-4A (LPDDR4), JESD279-4/JESD279-4A (DDR4), and JESD79-3E/JESD79-3F/JESD79-3-1A (DDR3/DDR3L). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 2: Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification). Note 3: The memory vendors often do not offer so many variants of single-channel memory devices. As an alternative, a dual-channel device with only one channel connected may be used. For example: A dual-rank, single-channel device with 16-row address bits has a density of 16Gb. If such a device is not available at the chosen supplier, a dual-rank, dual-channel device with 16-row address bits can be used instead. This device has a density of 32 Gb however since only one channel can be connected to the SoC, only half of the density is available (16 Gb). Usage of more than one discrete memory chips to overcome market constraints is not supported since only point-to-point connections are assumed for LPDDR4. Note 4: Devices with 17-row addresses (R0-R16) are not supported by the DDR Controller Note 5: The memory part number did not undergo full JEDEC verification however, it passed all functional testing items. Note 6: The density can be achieved by connecting 2 single-rank discrete devices with one 16Gb die each. Since the SoC supports x8 devices and also has connectivity for a second rank, usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 32Gb/4GB of address space dedicated for the DDR. Two x16 16Gb devices giving 32Gb/4GB in total is, therefore, the optimal choice that balances the maximum density aspects, the signal integrity aspects (only two discrete devices used), and bandwidth aspects (full data bus width used). Note 7: The density can be achieved by connecting 4 single rank discrete devices with one 16Gb die each, 2 devices connected to each chip select. Since the SoC supports x8 devices, the usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 64Gb/8GB of address space dedicated for the DDR. Four x16 16Gb devices giving 64Gb/8GB in total is the optimal choice that balances the maximum density aspects, the signal integrity aspects (only four discrete devices used), and the bandwidth aspects (full data bus width used). Note 8: The density can be achieved by connecting 4 single rank discrete devices with one 16Gb die each, 2 devices connected to each chip select. Note 9: The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select, or by connecting 2 dual rank discrete devices with two 8Gb dies each. Since the SoC supports x8 devices, the usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 32Gb/4GB of address space dedicated for the DDR. Four x16 8Gb devices giving 32Gb/4GB in total is, therefore, the optimal choice that balances the maximum density aspects, the signal integrity aspects (four discrete devices used), and bandwidth aspects (full data bus width used). Note 10: The density can be achieved by connecting 8 single rank discrete devices with one 8Gb die each, 4 devices connected to each chip select or by connecting 4 dual rank discrete devices with two 8Gb dies each. Note that the first option significantly exceeds the number of devices used on the validation board (4 discrete devices) therefore, it is not guaranteed that the i.MX would be able to drive the signals with margin to the required voltage levels due to increased loading on the traces. A significant effort would be required in terms of PCB layout and signal integrity analysis. Practically, it is not recommended to use more than 4 discrete DDR3L devices. This corresponds to the maximum density of 32Gb/4GB in the case of the single rank devices containing one 8Gb die or 64Gb/8GB in case of the dual-rank devices, each containing two 8Gb dies. Note 11: The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select or by connecting 2 dual rank discrete devices with two 8Gb dies each. Note 12: For single-channel (x16) memory devices, the current maximum available density in the market is 16Gb/2GB (Q1 2022). Note 13: Only one channel of the device (and hence, half of its density) was utilized due to the reduced data bus width (x16) of the SoC. Note 14: Part is active. Reviewed May 16th 2024 Note 15: Part is obsolete. Additional Links https://community.nxp.com/t5/iMX-and-Vybrid-Support/i-MX-8-8X-8XL-maximum-supported-LPDDR4-and-DDR3L-densities/ta-p/1152715

Hello! In this post, we’ll cross-compile a kernel module for Linux 6.12. This can be done either using a standalone kernel or a Yocto-built kernel. Requirements: A compiled Linux kernel 6.12. A board running the same kernel version (Linux 6.12 in this case). A cross-compiler toolchain. This process applies to any i.MX processor, including i.MX8, i.MX8M, i.MX8MM, i.MX8MN, i.MX8MP, i.MX93, i.MX91, i.MX95, as well as the i.MX6 and i.MX7 families. Step 1: Compile the Linux Kernel and get the Toolchain First, you need to compile the Linux kernel (6.12 in this case). You can do this in a standalone environment or using Yocto. If you are using a Standalone environment, please refer to the Chapter 4.5.12 How to build U-Boot and Kernel in standalone environment of i.MX Linux User's Guide. Also, in that document section, you will see how to obtain the cross-compiler toolchain. NOTE: To get the toolchain you need use Yocto at least once (for more information please refer to i.MX Yocto Project User's Guide😞 $ DISTRO=fsl-imx-xwayland MACHINE=Target-Machine bitbake core-image-minimal -c populate_sdk At the end of the building, you can install your toolchain populated under: yocto-bsp/build/tmp/deploy/sdk There you will find a file called: fsl-imx-wayland-glibc-x86_64-imx-image-core-armv8a-your-machine-name-toolchain-6.12-walnascar.sh Execute with: $ sudo ./fsl-imx-wayland-glibc-x86_64-imx-image-core-armv8a-your-machine-name-toolchain-6.12-walnascar.sh If you use the default installation, you will have your toolchain under /opt in your host machine. (If you will use the compiled kernel from Yocto, you can avoid below step) Download Standalone Kernel source by cloning with: $ git clone https://github.com/nxp-imx/linux-imx -b lf-6.12.y $ cd linux-imx To build the kernel in the standalone environment for i.MX 6 and i.MX 7, execute the following commands: $ make imx_v7_defconfig $ Make To build the kernel in the standalone environment for i.MX 8 and i.MX 9, execute the following commands: $ make imx_v8_defconfig $ make The full kernel compilation is required to generate headers and symbol files required for external module compilation, even if you don't plan to boot this kernel directly. Step 2: Write a simple Kernel Module to test Now that your kernel is compiled, you can write a basic kernel module for testing. Create a new directory. It will have our hello.c and Makefile. We will create the file hello.c: #include <linux/init.h> #include <linux/module.h> #include <linux/kernel.h> MODULE_LICENSE("GPL"); MODULE_AUTHOR("Salas"); MODULE_DESCRIPTION("A simple kernel module example for cross-compilation."); MODULE_VERSION("0.1"); static int __init hello_init(void) { printk(KERN_INFO "Hello from the kernel module!\n"); return 0; } static void __exit hello_exit(void) { printk(KERN_INFO "Goodbye from the kernel module!\n"); } module_init(hello_init); module_exit(hello_exit); Then, create a basic Makefile to compile the modules: # Module name obj-m += hello.o # Build flags ldflags-y += --strip-debug # Kernel source directory (provided by Yocto) KERNEL_SRC ?= /path/to/your/compiled/kernel # Build target all: $(MAKE) -C $(KERNEL_SRC) M=$(PWD) modules # Clean target clean: $(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean # Install target modules_install: $(MAKE) -C $(KERNEL_SRC) M=$(PWD) modules_install KERNEL_SRC should be your compiled kernel from your Yocto build: yocto-bsp/build/tmp/work/your-machine-poky-linux/linux-imx/6.12.20+git/build Or the Standalone : path/to/linux-imx/ Step 3: Set the toolchain and compile the kernel module Finally, we can compile the kernel module. First, set the toolchain (in my case): $ source /opt/fsl-imx-wayland/6.12-walnascar/environment-setup-armv8a-poky-linux Then, compile using the makefile: $ make f everything goes well, at final you will have the generated files: hello.ko hello.mod hello.mod.c hello.mod.o hello.o Makefile modules.order Module.symvers The one we need is the hello.ko (Kernel Object). We can check if the file was created correctly using: $ readelf -h hello.ko ELF Header: Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 Class: ELF64 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: REL (Relocatable file) Machine: AArch64 Version: 0x1 Entry point address: 0x0 Start of program headers: 0 (bytes into file) Start of section headers: 33992 (bytes into file) Flags: 0x0 Size of this header: 64 (bytes) Size of program headers: 0 (bytes) Number of program headers: 0 Size of section headers: 64 (bytes) Number of section headers: 41 Section header string table index: 40 We can see the Machine is AArch64 and the Type is a Relocatable file. Step 4: Running the Kernel Object/Module in the board Transfer the generated hello.ko file from your host machine to your board. Then, In your board you can run with: root@imx93evk:~# ls hello.ko root@imx93evk:~# insmod hello.ko root@imx93evk:~# dmesg | tail [ 5140.547447] Hello world from kernel! root@imx93evk:~# rmmod hello.ko root@imx93evk:~# dmesg | tail [ 5140.547447] Hello world from kernel! [ 5153.415215] Goodbye world from kernel! I hope this can helps to you. Best regards, Salas.

Background : Some customer want to test the LPDDR4/X ECC feature based on the i.MX93 chip, But, for now, Our DDR Config Tool do not release this test chosen. And our ECC guide only tell the ECC feature function, does not tell the customer how to test it. So in this article, Will show you more details about ECC feature and how to run the ECC test use uboot command. But I won't put the source code of the test here, You can download the binary run the test on the i.MX93 EVK board. HW : i.MX93 EVK board with 2GB LPDDR4 SW : 6.1.1-1.0.0 ECC Introduce what is ECC? ECC is the abbreviation of Error Correction Code. Its function is to automatically detect and repair some minor errors in the memory to prevent data errors. How does ECC work? We can think of it as an "automatic proofreader", and its workflow is roughly as follows: When writing data: The memory controller generates a "check code" (similar to the fingerprint of the data) for each piece of data. This check code will be stored together with the data. When reading data: The memory controller will recalculate the "fingerprint". Then compare the previously stored check code to see if there is any difference. If a difference is found: If it is just a 1-bit error, ECC can automatically correct it. But, If there are multiple errors, ECC can at least detect them and issue a warning. ECC test step: 1. Flash the attachment file to the imx93 board. 2. Enter the uboot, run the "ecc --help" command, you will see the below help output message 3. For example : ecc 0x80000000 0x90000000, it will test the ecc feature with on bit error detect and correct , 2 bits errors detect with 256MB DRM size. if you need this ECC_ test binary file, please contact me, i will share it to you

Our default BSP code can support below resolution: https://github.com/nxp-imx/linux-imx/blob/cbfe1a744dc4a794e79396c7079339a54f89c8f2/drivers/phy/freescale/phy-fsl-samsung-hdmi.c If customer want to add new pixel clock about their panel, they can ask our support to generate the new parameters about it, and then add the result to below struct: const struct phy_config samsung_phy_pll_cfg[] = {}. After add the result to the struct, you need to re-compile the kernel and boot your board, then run the "modetest -c" command Check whether the changes are effective when you run the modetest -c command, the following code show as below, You can see all the resolutions currently supported by your monitor. How to change the panel display resolution: 1) Run the below command at the uboot period: setenv mmcargs 'setenv bootargs console=${console} root=${mmcroot} video=HDMI-A-1:1920x1080-32@30' video=HDMI-A-1:3840x2160-32@30: Set video output parameters: HDMI-A-1: Specifies the use of the HDMI interface. 3840x2160: The resolution is 3840x2160 (4K). -32: The color depth is 32 bits. @30: The refresh rate is 30Hz. saveenv boot 2) Change the westom.ini file at the /etc/xdg/weston location, Change the resolution you want in [output] part. [output] #name=HDMI-A-1 #mode=640x480@60 #transform=rotate-90 3)Reboot the board, and run the "modetest -p" command see if your change is effective

This article is an example for users to change the DDR clock on i.MX6ULL board Environment: Hardware : i.MX6ULL EVK board Concept of MMDC controller clock source on i.MX6ull Consult Chapter 18 Clock Controller Module(CCM) in the I.MX 6ull reference manual. The MMDC clock source is shown in Figure 23.3.3.1: Figure 23.3.3.1 MMDC Clock Source Figure 23.3.3.1 shows the clock source path diagram of MMDC, which is mainly divided into three parts. 1. CBCMR[PRE_PERIPH2_CLK_SEL] : The pre_periph2 clock selector, which is the pre-selector of periph2_clkd, is controlled by the PRE_PERIPH2_CLK_SEL bit (bit22:21) of the CBCMR register. 2. CBCDR[PERIPH2_CLK_SEL] : periph2_clk clock selector, controlled by the PERIPH2_CLK_SEL bit (bit26) of the CBCDR register,When it is 0, pll2_main_clk is selected as the clock source of periph2_clk. When it is 1, periph2_clk2_clk is selected as the clock source of periph2_clk. 3. CBCDR[FABRIC_MMDC_PODF] : It is a frequency divider. The frequency division value is set by the FABRIC_MMDC_PODF bit (bit5:3) of the CBCDR register. It can be set to 0~7, corresponding to 1~8 frequency divisions respectively. To configure the clock source of the MMDC to 396MHz, it must be set to 1 here, so FABRIC_MMDC_PODF=0. The above is the clock source setting of MMDC. Implementation Step 1 : git clone the uboot code from NXP github web $ git clone https://github.com/nxp-imx/uboot-imx.git Step 2 : Modify the different frequencies of DDR by modifying the following files : uboot-imx/board/freescale/mx6ullevk/imximage.cfg As default BSP code, our DDR run frequency is 400MHz (Actually, it's 396MHz), If you want DDR to boot at 132MHz, we need to configurate the CCM_CBCDR[FABRIC_MMDC_PODF] bit, from this bit content, we need to set it to 010. The frequency division value is 3 based on 396MHz Change code as following: DATA 4 0x020c4014 0x00018910, Add this code in imximage.cfg file. Step 3 : Re-compile the uboot and flash the uboot to the board. Result Now, We can see that DDR is running at successfully at 132MHz. Before modification: After modification:

Hello everyone, in this post we will control one (or more) WS2812 LEDs from a Linux UserSpace application, communicating with Cortex M33 through RPMSG. Required materials: FRDM-IMX93 WS2812 LED/Strip Attached wsled.c (userspace application) Attached ws2812_m33_project (Source code of firmware for M33) Environment: Linux Kernel 6.6 arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi SDK 24.12.00 This is the block diagram of the application: CORTEX M33 SIDE. From WS2812 LED datasheet, we can see the timing must be precise, that is the reason we will use the Cortex M33 (Real time applications): As we can see, the timing just accept tolerance of 150ns, that is the reason is preferred to use the Cortex M33 instead of control with Linux that is in charge of other tasks. The function that we will implement to send Zero and One is: void WS2812B_send_bit(uint8_t bit) { if (bit) { // Send "1" RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 1); for (int i = 0; i < HIGH_ONE_CYCLES; i++) __asm__("NOP"); RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 0); for (int i = 0; i < LOW_ONE_CYCLES; i++) __asm__("NOP"); } else { // Send "0" RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 1); for (int i = 0; i < HIGH_ZERO_CYCLES; i++) __asm__("NOP"); RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 0); for (int i = 0; i < LOW_ZERO_CYCLES; i++) __asm__("NOP"); } } Testing and measuring the toggle timing with the RGPIO driver of Cortex M33, we could find the best number of NOP instructions to adjust with the required timing according to datasheet, and the results with core running at 200MHz are: Parameter Number of NOP times HIGH_ONE_CYCLES 22 (T1H: 700 ns) LOW_ONE_CYCLES 12 (T1L: 600 ns) LOW_ZERO_CYCLES 20 (T0L: 800 ns) HIGH_ZERO_CYCLES 6 (T0H: 350 ns) Zero: One: Taking in mind this information, we can start to develop our application. From Cortex M33, we created a little protocol, that will wait for instructions to do. For example, the expected string to fill the RPMSG buffer is: Index Purpose Example app_buf[0] Command ('c' or 't') 'c' = store color in buffer 't' = show colors on LEDs app_buf[1] Red component (0–255) 0xFF app_buf[2] Green component (0–255) 0x00 app_buf[3] Blue component (0–255) 0x80 app_buf[4] LED index (target LED position) e.g. 0, 1, 2 Commands: 'c' "Color store" This command stores the RGB color value into a local buffer, targeting a specific LED (app_buf[4]). It doesn't update the LED strip immediately, it just prepares the data. Example of RPMSG received buffer from Cortex A (Linux): app_buf = { 'c', 0xFF, 0x00, 0x00, 2 }; // Store red color for LED 2 't' "Transfer" This command sends the full color buffer to the WS2812 strip, updating the LED colors. The RGB values in the buffer are ignored, it simply triggers an update based on previously stored data. Example of RPMSG received buffer from Cortex A (Linux): app_buf = { 't', 0, 0, 0, 0 }; // Transfer the buffered colors to the LED strip You can modify the code to add your custom commands like change number of LEDs on the strip, or change the GPIO, etc. Currently, the number of WS2812 LEDs supported is defined in software by NUM_RGB_LEDS. As default is 8 LEDs. I will attach the full code for Cortex M33 firmware, it was tested with arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi and SDK 2_15, SDK 2_16 and SDK 24. In this example, the EXP_GPIO_IO24 of FRDM-IMX93 was used to control the LED Strip. CORTEX A55 SIDE. For Cortex A55 (Linux side), we developed an userspace application, that will create the structure for the buffer to send to the Cortex M33 and send through RPMSG using the imx_rpmsg_tty included on the NXP BSP. You can find the userspace application attached. As we know, the imx_rpmsg_tty creates the tty channel called ttyRPMSG31 under /dev. So, this userspace application communicates directly with the device /dev/ttyRPMSG31 to send the buffer with the required structure for Cortex M33. EXAMPLE OF USAGE. STEP 1. Compile firmware for Cortex M33 and store in FRDM-IMX93 under /lib/firmware to use with remoteproc: STEP 2. Compile or cross-compile the userspace application (attached.) To compile on the platform: root@imx93evk:~# gcc wsled.c -o wsled root@imx93evk:~# ls wsled wsled.c Also, we can copy the wsled under /bin to practicity. root@imx93evk:~# wsled Error: -c <red> <green> <blue> is required. WS2812 Usage: wsled -c <red> <green> <blue> [-n <led_position>] Load the color of exact LED to the buffer wsled -t Shows the colors to the LEDs STEP 3. To run the entire example: boot the board and load the firmware for cortex M33 with remoteproc: root@imx93evk:~# cd /sys/class/remoteproc/remoteproc0 root@imx93evk:/sys/class/remoteproc/remoteproc0# echo ws2812_m33.elf > firmware root@imx93evk:/sys/class/remoteproc/remoteproc0# echo start > state Then, we will receive this from Cortex M33 terminal: RPMSG String Communication Channel FreeRTOS RTOS M33 clock is at: 200000000 Hz Nameservice sent, ready for incoming messages from Cortex-A55! WSLED Load the imx_rpmsg_tty module in Linux to initialize RPMSG: root@imx93evk:~# modprobe imx_rpmsg_tty Then, we will have the hello world message from Cortex A (Linux side), but with our buffer format in Cortex M33 console: CMD: h [1]:0x65 [2]:0x6c [3]:0x6c [4]: 111 LEN = 12 Finally, we are ready change colors of the LEDs: Load the buffer (LED 1 = RED, LED 2 = Green, LED 3 = Blue). root@imx93evk:~# wsled -c 0x55 0x00 0x00 -n 1 root@imx93evk:~# wsled -c 0x00 0x55 0x00 -n 2 root@imx93evk:~# wsled -c 0x00 0x00 0x55 -n 3 Show colors on LEDs. root@imx93evk:~# wsled -t

NETC is a TSN capable Ethernet IP, which enables a comprehensive portfolio of Ethernet solutions. One of the major capabilities offered by NETC is the support of Time Sensitive Networking (TSN). TSN is a set of standards developed by IEEE that enables Ethernet to handle time sensitive traffic in addition to best effort traffic. TSN allows time sensitive traffic and best effort traffic to co-exist on the same network, makes Ethernet deterministic with bounded low latency, and with improved reliability and resiliency. This document introduces I.MX95 NETC functional view and capabilities; Analyze IMX95 supported TSN protocols such as 802.1Qbv, 802.1Qav, 802.1Qci, IEEE1588 and stream identifying; Provide Procedures to implement the Qbv use case scenario on I.MX95.

Platform: i.MX8MP EVK, SDK 2.16 The rpmsg debug will stuck at rpmsg_queue_recv/rpmsg_lite_send when we use Step Over debug with JLink. The error log on Linux side: [ 42.422658] remoteproc remoteproc0: kicking vq index: 1 [ 42.524256] imx-rproc imx8mp-cm7: imx_rproc_kick: failed (1, err:-62) [ 42.524286] remoteproc remoteproc0: kicking vq index: 0 [ 42.628566] imx-rproc imx8mp-cm7: imx_rproc_kick: failed (0, err:-62) The demo source code of rpmsg in SDK uses RL_BLOCK, this flag will cause communication stuck during debug. while (msg.DATA <= 100U) { (void)PRINTF("Waiting for ping...\r\n"); (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char *)&msg, sizeof(THE_MESSAGE), ((void *)0), RL_BLOCK); msg.DATA++; (void)PRINTF("Sending pong...\r\n"); (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_BLOCK); } The solution for rpmsg step over debug is that we need to use RL_DONT_BLOCK in sdk.

Introduction There are some cases where it is needed to flash the image from a removable boot source (e.g. an SD card) to another boot source (e.g. eMMC), according to our documentation this can be done via dd but this does not work in the case you would like to do all the process in the board caused by the eMMC partition structure. Required equipment. i.MX93 FRDM board (this is the selected board for this post, it works for others). Debug USB-C cable. Data USB-C cable. Micro SD (64GB memory used in this test). Personal computer. The default partition configuration for an eMMC device is as follows: Where: - Boot areas are used for bootloader and environment configurations. - Replay-protected memory-block area (RPMB) is used to store secure data. - User area used for application data such as file system, usually divided in two or more partitions. In the case of an image, the eMMC is organized according to the next diagram: - Boot area 1 is used to store SPL and U-boot with no file system in a fixed offset according to each processor as mentioned in i.MX Linux User's Guide section 4.3 Preparing an SD/MMC card to boot. - User area partition 1 uses a FAT format where Kernel and Device Tree files are stored. - User area partition 2 is used for root file system with Ext3/Ext4 format. Exception Our documentation has a method to flash .wic image which contains all the mentioned above or each part manually using an SD card connected to a host Linux machine via dd command: sudo dd if=<image name>.wic of=/dev/sdx bs=1M && sync Or set up the partitions manually such as bootloader: sudo dd if=<U-Boot image> of=/dev/sdx bs=1k seek=<offset> conv=fsync Also, copying the kernel image and DTB file and the root file system as mentioned in i.MX Linux User's Guide. This method works for SD card since the data is stored in user area and the offset changes to burn the bootloader. This fails when we try to flash the image from SD card to eMMC. How to reproduce the issue? First, we need to erase the eMMC, here a post to achieve this task. Format boot partition of eMMC from U-boot - NXP Community How to flash image from SD card to eMMC? With the eMMC erased, we need a boot source to store and flash the image, in this case the SD card. Once the image is flashed into the Micro SD, we need to copy the necessary files such as bootloader and image. By default, our BSP has a User Area space of <>GB and we need to increase it to save the bootloader and the image, here the steps: Verify the device and partition numeration: lsblk The command to increase the size of the partition is the next: parted /dev/<storage unit> unit MiB resizepart <partition> <size in bytes> And the command to apply the changes is: resize2fs /dev/<storage and partition unit> In this case, the device and partition we need to change is mmcblk0p2 so, the command is as follows: parted /dev/mmcblk0 unit MiB resizepart 2 10000 I increased the partition size by 10000 MB; this will be enough to store the required files. And now, we need to apply the changes: resize2fs /dev/mmcblk0p2 In the board will look like this: Now, let's copy the bootloader and root file system in SD. In this post we will use SCP: Now, we need to boot from SD card and run the next commands: As is mentioned in Linux User's guide, we need to flash the .wic image. This contains all the necessary data to flash the entire image but when flashing from SD card to eMMC we need to follow additional steps to unlock the partition used to store the bootloader: sudo dd if=<image name>.wic of=/dev/sdx bs=1M && sync Disable write protection: echo 0 > /sys/block/<storage and partition unit>/force_ro And flash the bootloader: dd if=<bootloader> of=/dev/<storage and partition unit> bs=1K seek=0 In the board will look like this: With this process now it is needed to reboot the board, change boot mode switches to boot from eMMC, and the board will boot normally, the user can perform an image flashing to simplify development workflow and also an alternative to update OS without external host dependencies.

Hello, this post describes how you can add Japanese Language to the Yocto BSP. There are just a few steps to achieve. It was tested on the i.MX93-FRDM board, i.MX93-EVK and i.MX8M (Family). And Linux kernel 6.6.36. The first step before to start your board building according to the Yocto Project User's Guide, is adding the below lines to the local.conf file: GLIBC_GENERATE_LOCALES = "en_US.UTF-8 ja_JP.UTF-8" IMAGE_LINGUAS = "en-us ja-jp" IMAGE_INSTALL:append = " \ glibc-gconv-euc-jp \ glibc-gconv-sjis \ glibc-gconv-utf-16 \ glibc-utils \ fontconfig \ ttf-bitstream-vera \ ttf-dejavu-sans \ " Where: glibc-gconv-*: Adds Japanese encoding conversions. After building, flash the Image to the board and boot it. You can check if the Japanese font was installed successfully with: root@imx93frdm:~# locale -a C POSIX en_US en_US.utf8 ja_JP ja_JP.utf8 We can see it was installed successfully: ja_JP ja_JP.utf8 Then, we can change the Language at Runtime with: root@imx93frdm:~# export LANG=ja_JP.UTF-8 root@imx93frdm:~# export LC_ALL=ja_JP.UTF-8 Finally, probe with a command that supports Japanese outputs like "date": root@imx93frdm:~# date 2024年 2月 27日火曜日 17:29:11 UTC I hope this information can helps to you. Best regards, Salas.

We are pleased to announce that Config Tools for i.MX v25.06 are now available. Downloads & links To download the installer for all platforms, please login to our download site via: https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX Please refer to Documentation for installation and quick start guides. For further information about DDR config and validation, please go to this blog post. Release Notes Full details on the release (features, known issues...) • DDR – Support for i.MX 91 is added. – Synchronized with BSP Q2 release – Support for the i.MX 91 FRDM board is added. – Support for the i.MX 93 FRDM board is added. – Spectrum support for i.MX 95 and i.MX 943 is spread. – The Address mirroring option in the UI for all mscale devices with DDR3L and DDR4 is exposed. – DDR3L support for i.MX 8M and i.MX 8MM is added. – Linux support for code generation (beta) is added. • SerDes tool – i.MX 943 support (Beta) is added. • Clocks – Support for read-only element settings is added. – Filtering all settings of Initialization modules in the Details view is supported. • Peripherals – A wizard to export the Registers view data in the CSV format is supported. – Performance of the tool is improved. • An ability to export/import Expansion Boards and Expansion Headers is added.

This guide provides a clear overview of how different versions of GUI Guider integrate with LVGL and the supported rendering backends: DRM and Wayland. It also explains how to configure and run your application based on the selected backend. Switching between backends is straightforward—simply modify a few lines in the lv_conf.h file, located in the lvgl folder of the code generated by GUI Guider. Default Rendering Backends by GUI Guider Version GUI Guider Version LVGL v8 LVGL v9 1.9.1 DRM WAYLAND 1.9.0 WAYLAND WAYLAND Note: Only one configuration (DRM or Wayland) can be used at a time. Configuration Settings in lv_conf.h To use DRM, set the following: #define LV_USE_WAYLAND 0 #define LV_USE_LINUX_DRM 1 To use Wayland, set: #define LV_USE_WAYLAND 1 #define LV_USE_LINUX_DRM 0 Running LVGL with DRM Before launching the gui_guider binary in DRM mode, you must stop the Weston service: systemctl stop weston ./gui_guider Note: These steps must be executed via the debug console or over SSH, as stopping Weston will disable the desktop environment and make the local display unavailable Running LVGL with Wayland No special steps are required. Simply run the binary: ./gui_guider You can refer to the following guides to learn how to compile GUI Guider binaries according to the version you are using: Build GUI Guider projects for iMX93 (GUI GUIDER 1.9.X) Build GUI Guider projects for iMX93 (GUI GUIDER 1.6.x, 1.7.x, 1.8x)

The purpose of this document is to provide extended guidance for the selection of compatible LPDDR4/4X memory devices that are supported by the i.MX 93 series of processors. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs. The i.MX 93 series of processors supports different packages, and each have their own maximum supported LPDDR4/4x data rates. Please refer to the respective datasheets. NOTE: Some of the LPDDR4/4X devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low-speed operation is planned in the use case, please consult with the memory vendor about the configuration aspects and possible customization of the memory device so correct functionality is ensured. LPDDR4/4X - Maximum Supported Densities SoC Max Data bus width Maximum density Assumed memory organization Notes i.MX 93 (i.MX 93xx) 16-bit 16 Gb / (2 GB) single rank, single channel device with 17-row addresses (R0 - R16) 1, 2, 3 LPDDR4/4X - List of Validated Memories The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Memory Vendor Validated Memory Part# Notes i.MX 93 16 Gb/ (2 GB) Micron LPDDR4/4x: MT53E1G16D1FW-046 AAT:A (Z32N) MT53E1G16D1ZW-046 AAT:C (Z42N) 7 4, 8 8 Gb/ (1 GB) Micron LPDDR4/4x: MT53D512M16D1DS-046 AAT (Z11M) 4, 10 16 Gb/ (2 GB) Micron LPDDR4/4x: MT53E1G32D2FW-046 AUT:B (Z42M) 4, 5, 10 8 Gb/ (1 GB) Nanya LPDDR4: NT6AN512M16AV-J1I LPDDR4x: NT6AP512M16BV-J1I 4, 8 4 Gb/ (512 MB) Nanya LPDDR4x: NT6AP256M16AV 4, 8 16 Gb/ (2 GB) Kingston LPDDR4: C1612PC2WDGTKR-U 7, 9 8 Gb/ (1 GB) ISSI LPDDR4: IS43LQ16512A-053BLI 4, 8 8 Gb/ (1 GB) CXMT LPDDR4/4x: CXDB4CBAM-EA-M 4, 9 16 Gb/ (2 GB) JSC LPDDR4x: JSL4BAG167ZAMF 4, 8 8 Gb/ (1 GB) JSC LPDDR4x: JSL4B8G168ZAMF-05x 4, 8 4 Gb/ (512 MB) JSC LPDDR4x: JSL4A4G168ZAMF-05 4, 8 2Gb / (256 MB) Winbond LPDDR4x: W66BQ6NBHAGJ 4, 6, 8 8Gb / (1 GB) IM (Intelligent Memory) LPDDR4x: IM8G16L4JCB-046I 4, 11 4Gb / (512 MB) Samsung LPDDR4: K4F4E164HD-THCL 4, 8 8 Gb / (1 GB) AM (Alliance Memory) LPDDR4X: AS4C512M16MD4V-053BIN 4, 8 2Gb / (256 MB) ISSI LPDDR4: IS46LQ16128A-062BSLI 4, 6, 8 Note 1: The numbers are based purely on the IP documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, SoC reference manual and on the JEDEC standards JESD209-4B/JESD209-4-1 (LPDDR4/4X). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 2: Byte-mode LPDDR4/4X devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification). Note 3: The SoC also supports dual rank single channel devices therefore, 16Gb/2GB density can be also achieved by using a dual rank single channel device with 16-row addresses (R0 - R15). Note 4: The memory part number did not undergo full JEDEC verification however, it passed all functional testing items. Note 5: This is a dual channel x32 device. Since i.MX93 only supports 16-bit LPDDR4/X data bus, it can only interface with one of the channels and therefore, utilize only half of the device's density. As indicated in the table - the device has 32Gb/4GB density however, only 16Gb/2GB can be used. There is no functional problem with using only one channel of a dual channel device as the channels are independent in LPDDR4/4X. Note 6: This is a new JEDEC 100 ball package, half the size of the standard 200 ball package. This 100 ball package has the same performance and functionality as the 200 ball package, and has the added advantage of being smaller and cheaper than the standard package. Note 7: This device has been EoLed by the manufacturer and has been updated by a new memory part number Note 8: Part is active. Reviewed Jun 2025 Note 9: Part is obsolete. Note 10: This device will be EoLed in Q2 24 by the manufacturer and will not be updated by a new memory part number Note 11: DQ eye marginalities were identified during TSA analysis. vTSA and stability testing did not identify any issues.

the enclosed code is based on How to fuse key through nvmem on i.MX93 - NXP Community and modified for the imx8mp, this article about how to fuse mac address via fuse command in the uboot or nvmem in the kernel ================================================================ Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

This guide walks you through the required steps to prepare your development environment and hardware for debugging the M core on the FRDM-IMX93 board using the MCU-LINK Pro. You’ll install the necessary firmware, perform minor hardware modifications, compile and flash a binary, and finally, initiate a debug session using MCUXpresso for VS Code. Requirements: FRDM-IMX93 Board MCU-LINK Pro Debug Probe Soldering Station (for minor rework) PC Host with MCUXpresso for VS Code installed Adapter Cables Install Segger Firmware on MCU-LINK Pro By default, the MCU-LINK Pro does not support i.MX processors. Installing the Segger firmware is essential for proper debugging. Follow the firmware update guide to update your MCU-LINK Pro. Rework the FRDM-IMX93 Board The FRDM-IMX93 uses UART5 (shared with the BT module) for debug pins, which causes conflicts. To enable reliable debugging, remove the following resistors: R3017 R3018 Note: After this modification, the Bluetooth module will no longer function under Linux. Schematic: FRDM BOARD: Note: After this rework we can't use the Bluetooth module in Linux Compile the Binary for the M Core Ensure MCUXpresso for VS Code is properly installed. Import the iMX93-EVK SDK Import "hello world" example Ensure that we are compiling a debug binary Build Project Flash the Binary using UUU Tool Connect the FRDM Board to your Host PC via USB Enter Fastboot Mode in U-Boot Terminal => fastboot 0 On your Host PC, navigate to the binary location and flash it using the next commands: $ cd <project_location>/armgcc/debug/ $ uuu -b fat_write sdk20-app.bin mmc X:1 hello_world.bin Note: replace the X with 0 if you are booting from eMMC or 1 if you are booting from SD Card Connect MCU-LINK Pro to the Target To set up debugging, connect the FRDM-IMX93 board to your host computer using the MCU-LINK Pro and the J-LINK Adapter for Cortex-M. FRDM-IMX93 Debug connector: Required Connections Use the following pin mapping between the J-LINK Adapter and the FRDM-IMX93 debug connector: J-LINK ADAPTER --> FRMD-IMX93 V REF --> 3.3v(RPI Connector pin 1 ) SWDIO --> SWDIO (P14 pin 2) SWCLK --> SWCLK (P14 pin 1) GND --> GND (P14 pin 3) Make sure all connections are secure before powering on the board. Launch the M Core from U-Boot Terminal Use the following commands in the U-Boot terminal: => fatload mmc X:1 80000000 hello_world.bin; cp.b 0x80000000 0x201e0000 0x10000; => bootaux 0x1ffe0000 0 Note: replace the X with 0 if you are booting from eMMC or 1 if you are booting from SD Card Start the Debug Session Once the M core is launched, you can start your debug session in VS Code using MCUXpresso: With the MCU-LINK Pro configured, the FRDM-IMX93 reworked, and the binary successfully flashed and executed, you are now ready to debug applications on the M core using MCUXpresso and VS Code. This setup enables a reliable development workflow for i.MX93-based projects.

Introduction. In some cases, such as development stages, testing, validate flash process from zero, etc. It is needed to erase the eMMC storage device, here is described the process and the required equipment: Required equipment. i.MX93 FRDM board (this is the selected board for this post, it works for others). Debug USB-C cable. Data USB-C cable. Micro SD (16GB recommended). Personal computer. How to erase the eMMC? This method will use another boot source (Micro SD) to erase the eMMC so, it is needed to flash the Micro SD with at least the bootloader (U-boot), you can use a prebuilt image for the EVK board, it can be downloaded from the following link. But, in the case of i.MX93 FRDM board, there is no pre-built image available and needs to be build: The FRDM-IMX93 BSP release is based on i.MX SW 2024 Q3 release with Yocto Project 5.0 (Scarthgap). To build FRDM-IMX93 image from source code, please first check i.MX Yocto Project User's Guide to get familiar with Yocto project and Yocto build. Then please follow below steps to build image for FRDM-IMX93. 1. Download i.MX SW 2024 Q3 BSP Release: $ repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-scarthgap -m imx-6.6.36-2.1.0.xml $ repo sync 2. Integrate FRDM-MX93 layer into Yocto code base: $ cd ${MY_YOCTO}/sources $ git clone https://github.com/nxp-imx-support/meta-imx-frdm.git 3. Yocto Project Setup: $ MACHINE=imx93frdm DISTRO=fsl-imx-xwayland source sources/meta-imx-frdm/tools/imx-frdm-setup.sh -b frdm-imx93 4. Build images: $ bitbake imx-image-full The flashing process can be consulted here. Once the board is flashed, we need to change the boot switches to boot from Micro SD and turn-on the board. To debug this process, we will use Tera Term terminal with the board connected from the Micro USB debug cable to the PC and select the next configuration: Please verify that you are selecting the corresponding COM for Cortex-A debug. After boot we need to press a key, and the board will enter to U-boot. So, then we need to select the partition of the eMMC with the next command: u-boot=> mmc dev <storage device> <partition> In the case of the eMMC, the storage device corresponds to the device "0" and if the device has an image flashed into the eMMC e.g. Linux, the device will have three partitions from 0 to 2. The next command will select the eMMC and the boot partition area: u-boot=> mmc dev 0 0 switch to partitions #0, OK mmc0(part 0) is current device Depending on the device, image, etc. This partition size can vary so, we need to know how many blocks it has. We can use the next command that will let us know the max address value that is assigned to this partition by getting an error on the address that is out of the range. u-boot=> mmc read ${loadaddr} 0x7fffffff 1 MMC read: dev # 0, block # 2147483647, count 1 ... MMC: block number 0x80000000 exceeds max(0x1d5a000) 0 blocks read: ERROR Now, with this information, we are able to erase the entire partition with the next command: u-boot=> mmc erase 0 0x1d5a000 MMC erase: dev # 0, block # 0, count 30777344 ... 30777344 blocks erased: OK As mentioned before, the device has multiple partitions so, this process needs to be done in each partition Boot area Partition. User Area 1 Partition. User Area 2 Partition. But the process is the same, let's change the partition to User Area 1: u-boot=> mmc dev 0 1 switch to partitions #1, OK mmc0(part 1) is current device Confirm the size of the partition: u-boot=> mmc read ${loadaddr} 0x7fffffff 1 MMC read: dev # 0, block # 2147483647, count 1 ... MMC: block number 0x80000000 exceeds max(0x2000) 0 blocks read: ERROR And erase it: u-boot=> mmc erase 0 0x2000 MMC erase: dev # 0, block # 0, count 8192 ... 8192 blocks erased: OK And let's finish with User Area 2 Partition: u-boot=> mmc dev 0 2 switch to partitions #2, OK mmc0(part 2) is current device u-boot=> mmc read ${loadaddr} 0x7fffffff 1 MMC read: dev # 0, block # 2147483647, count 1 ... MMC: block number 0x80000000 exceeds max(0x2000) 0 blocks read: ERROR u-boot=> mmc erase 0 0x2000 MMC erase: dev # 0, block # 0, count 8192 ... 8192 blocks erased: OK With this done, the eMMC is completely erased and you can confirm it by turning off the board, change the boot switched to eMMC, remove the SD card and turn-on the board. Since there is not a bootable image into the boot source, the board will jump to serial download mode and you can verify connecting the USB data cable to the board and run the next command in UUU: Conclusion. Erasing the eMMC of the board is optional step in your development stage but also helpful for testing or system recovery (e.g. test manufacture mode). By using a Micro SD you can access to the eMMC and do all the modifications in the partitions that you want without issues. With this you can go to a clean storage state into the boot device and test a new image from scratch or test recovery methods in your design.

i.MX Processors Knowledge Base

i.MX Processors Knowledge Base

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