I read the S32K3XX PDF and was wondering if EDC, XBIC, and FCCU are peripherals of the S32K3. If they are, why can’t I find them listed under the McuPeripherals tab in EB Tresos? Seems moudles connected to AHBS (system bus), are not Peripherals, right? The PFLASH controller is not listed under the McuPeripherals tab. Can I access the PFLASH registers by including the RTD header file?
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Hi， In the Safety manual for SC900719,We Can find some Safe mechanismes about Power(VPWR、VCC5.VCC3P3..)；But Can't find the Safe mechanism Aout Wheel Speed Sensor And LSDx、HSDx ; We want to inquire whether the Wheel Speed Sensor And LSDx and HSDx meet the Asil D design requirements; or what needs to be done to meet Asil D . Thanks!
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Customer is Ford.
AOU 216468 and 25593:
to fulfill static configuration registers check via : REG_PROT, XRDC and MMU.
we have way of fulfilling static configuration registers check of MSCM static registers by periodic interrupt monitoring .
Is it sufficient to fulfill the given AoUs or do we need to implement REG_PROT for individual registers as well.
if yes, could you please help us with the registers which needs to be protected/verified by REG_PROT.
Note: As discussed, only MSCM configuration registers are leading to single point failures.
-Randy Krakora
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Hi, Our customer has the following question regarding SRAM ECC faults: SM_119 is described as this: "The Flash memory ECC failure reporting path should be checked to validate if detected ECC faults are correctly reported." There is no such SM for the SRAM ECC to validate if SRAM ECC faults are correctly reported. Is that a missing one, or is there no need validate such a thing for SRAM ECC? Kind regards, Norm
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