Hi, I am wondering if you can explain what would happen if one of the pins in either of the +1V1,+1V5,+2V5, +VDD etc power nets were to be unconnected? The reason I ask is we are doing an fmeda on each pin where "open" is one fault condition. I also know that all of the power nets need to be connected externally. So, would the power rail, for instance +1V5, be unaffected, slightly affected or worse by one of the pins being left unconnected. Best regards, Jon Klaesson ... View more

For the following assumption requirement, master safety core is used , which is Core 2. However Core 2 is aligned with Lockstep(Core1) and it is more secured. So instead of using Core 2, can Core 0 is used for the following requirement?   Software assumption The application software running on the master safety core manages the FCCU failure status and interrupts. Rationale Ensures consistency with the safety concept. Recommendation NXP solution: Use the S32 Safety Software Framework (eMCEM module). ... View more

Hi Safety team, One of my client is not using the SAF, they want to implement the SM. Q-1. In the Addendum_S32K3xx.xls sheet,Module Clasification section, Safety machanism for S32K322 Microcontroller is missing. Below Micro variants are mentioned. S32K344 S32K312 S32K342 S32K358 S32K311 S32K388 Q-2. As per below section, talks about the redundancy. Is it applicable for ASIL B? 6.13.4.1.1 Digital inputs Functional safety digital inputs may need to be acquired redundantly. To reduce the risk of common cause failures, the redundant channels must use GPIO/PWM functionality on two different ports. The double read digital inputs can be acquired as follows: Table 45. Digital outputs software tests Double Write Digital Output Redundant PORT hardware element is used to perform a double-write digital output. Double Write PWM OutputRedundant PORT hardware element is used to perform a double-write digital output Q-3. ADC self test ,it’s mentioned that C self-test and the voltage self-test. Please provide more details, what exactly we have to do in these two test. Client want to implement this. As per the Addendum_S32K3xx.xls sheet :-- "ADC self test (periodical test of correct ADC operation). There are two different modes in self-test, the C self-test and the voltage self-test. The self-test C algorithm tests the :-- whole conversion frontend, CDAC, comparator and data drive out. What it does not test is most of the channel mux and the reference input, though when compared with the voltage self-test, :--- then there is only part of the channel mux left untested Please suggest. Regards, Dinesh ... View more

Hello, I have questions regarding some of the safety mechanisms that require NXP's clarification.  1. The Safety Manual Rev 2. SM17 (table 11) states both "Medium" and "60% diagnostic coverage, which cannot both be true. Based on the fact that LFM requires ASIL B (with a DC of 60% or greater), it is assumed this is a typographical error. Please confirm the diagnostic coverage for SM17. 2. While DC of 60% is acceptable per ISO 26262, Part4-6.4.2.5, is there a reason that both ABIST and LBIST cannot meet 90%? Please advise. 3. VDDIOMON, VCOREMON, VMONx, and HVLDO monitors all have safety mechanisms for OV, UV, and OV&UV detection. Where the latter is SMxC. For example, I don't understand why there is a separate mechanism for VMON1 OV (SM3A) and UV (SM3B), and a different mechanism for the combination (SM3C). Further, there is a further set of mechanism to encompass all monitors OV, UV, and OV&UV (SM18, SM19, SM20). I've reviewed the FMEDA and it still isn't clear to me what the difference truly is and how to use each. Please advise as they all reference the same respective safety manual sections. I look forward to reviewing your feedback. Thanks, Jeff     ... View more