Using external PSRAM on the MCX FlexSPI port can enable a large degree of application flexibility. In this paper we show how to add 8MB of Octal DDR PSRAM to the MCXN947 and execute baseline performance tests.

These two lab guides provide step-by-step instructions on how to take a quantized TensorFlow Lite model and use the Neutron Conversion Tool found in eIQ Toolkit to convert the model to run on the eIQ Neutron NPU found on MCX N devices.  The eIQ Neutron NPU for MCUs Lab Guide - Part 1 - Mobilenet.pdf document focuses on using the eIQ Toolkit GUI method to convert a model and then import that converted model into an eIQ MCUXpresso SDK example. It is recommended to go through this lab first.    The eIQ Neutron NPU for MCUs Lab Guide - Part 2 - Face Detect.pdf document focuses on using the eIQ Toolkit command line utilities to convert a model for the eIQ Neutron NPU and integrate that newly converted model into the Face Detect demo found on the Application Code Hub. Both labs were designed to run on the FRDM-MCXN947 but the same concepts can be applied to other MCX N boards.  Also be sure to also check out the Getting Started community post for more details on the eIQ Neutron NPU. --- Updated May 2024 for eIQ Toolkit 1.11.4

The table below contains notable updates to the current release of the Reference Manual. The information provided here is preliminary and subject to change without notice. Affected Modules Issue Summary Description  Date MCXNx4x Pinout xlsx Attachment Defeature PF* pins Erroneous pinouts to PF* signals on ALT11 are removed.  Before:    After:    01 March 2024 System Boot ROM API Missing Boot Modes sections in ROM API chapter of System Boot New sections added: 15.3 Boot modes 15.3.1 Master boot mode Master boot mode supports the following boot devices: Internal flash memory boot FlexSPI NOR flash memory boot SPI 1-bit NOR recovery boot Secondary bootloader boot Table 229. Image offsets for different boot media   Boot media Image offset Internal flash memory boot 0h FlexSPI NOR flash memory boot 1000h SPI 1-bit NOR recovery boot 0h Secondary bootloader boot 0h   15.3.2 Secondary bootloader mode   The Secondary bootloader mode can be enabled by setting the CMPA[BOOT_SRC] as 2, the image loaded in the Bank1_IFR0 region (0x0100_8000 to 0x0100_FFFF) will be set as primary boot mode, and the secondary boot image will boot first after the device reset. The secondary boot image type can be plain, crc or signed image, but cannot set as the SB file.   Based on the CMPA[OEM_BANK1_IFR0_PROT](0x01004004[5:7]) setting, after the secondary boot image boot, the Bank1_IFR0 region will be configured with different MBC setting:   Lifecycle CMPA[OEM_BANK1_IFR0_PROT] Secondary bootloader mode MBC IFR0 recovery boot MBC Develop (0x3) NA GLABC0 GLBAC0 Develop2 (0x7), In-field (0xF), In-field Locked (0xCF), Field Return OEM (1F) 0 GLBAC4 GLBAC4   1 GLBAC4 2 GLBAC2 3 GLBAC6 4 GLBAC4 5 6 7     01 March 2024 Input Multiplexing (INPUTMUX) Clarification to CMP trigger input registers Update to the CMPx_TRIG Register function description for the following registers: CMP0_TRIG (260h), CMP1_TRIG (4EOh), and CMP2_TRIG (500h)  Before:  Function This register selects the CMPx trigger inputs   After: Function This register selects the CMPx SAMPLE/WINDOW input 01 March 2024  

When deploying a custom built model to replace the default models in MCUXpresso SDK examples, there are several modifications that need to be made as described in the eIQ Neutron NPU hands-on labs. Here are some common issues and error messages that you might encounter when using a new custom model with the SDK examples and how to solve them. If there is an issue not covered here, then please make a new thread to discuss that issue.    “Didn't find op for builtin opcode ‘<operator_name>’” Need to add that operator to MODEL_GetOpsResolver function found in source\model\model_name_ops_npu.cpp A full list of operators used by a model that can be copy-and-pasted into that file is automatically generated by Neutron Converter Tool with the dump-header-file option. Make sure to also increase the size of the static array s_microOpResolver to match the number of operators   “resolver size is too small” Need to increase the size of the static array s_microOpResolver in MODEL_GetOpsResolver function found in source\model\model_name_ops_npu.cpp to match the number of operators     “Failed to resize buffer” The scratch memory buffer is too small for the model and needs to be increased. The size of the memory buffer is set with the kTensorArenaSize variable found in the model data header file   “Incompatible Neutron NPU microcode and driver versions!” Ensure the version of the eIQ Neutron Converter Tool used to convert the model is the correct one that is compatible with the NPU libraries used by the SDK project.  eIQ Toolkit v1.10.0 should be used with MCXUpresso SDK for MCX N 2.14.0. The Neutron Converter Tool version is 1.2.0+0X84d37e1f     Camera colors are incorrect on FRDM-MCXN947 board Modify solder jumpers SJ16, SJ26, and SJ27 on the back of board to move them to the left (dashed line side) to connect camera signals properly.             This modification will disable Ethernet functionality on the board due to a signal conflict with EZH D0 and ENET_TXCLK. If your project needs both camera and Ethernet functionality, then only move SJ16 and SJ26 to the left (dashed line side) and then connect a wire from P1_4 (J9 pin 😎 to the left side of R58. Then in the pin_mux.c file in the project, instead of using PORT1_PCR4 for EZH_Camera_D0, use PORT3_PCR0.                           

An open-source PCB template for creating a custom shield for the FRDM-MCXN947  

An open-source PCB template for creating a custom shield for the FRDM-MCXA153  

The open source hardware community is please to offer ECAD schematic symbols for the new MCX A153 and MCX N947 microcontrollers.     The MCX A153 schematic library has the QFP32, QFN48 and LQFP64 variants. The MCX N947 schematic library has the BGA184 and LQFP100 variants. The symbols were generated using data from the MCUXpresso Pin Config tool to ensure accuracy. The pin names include all pin mux options to make it easy to see all available peripheral functions and further simplify the symbol for your own design purpose The symbol data is provided in the open source KiCad V7 format and is attached to this post. The symbols can be imported into commercial tools such as Altium Designer. Enjoy!  

  The MCX  N series are MCUs with an integrated flash memory like many traditional MCU series. Having an embedded flash memory is particularly useful, as facilitates board design, development, simplifies BOM, software development.  However, the size of the embedded flash might not meet applications required memory footprint. Some customers simply need more flash memory. For example, Graphical applications require store large image buffers in a non-volatile memory. Data logger devices that need to store large amounts of data. Or heavy inference models for object recognition.  Applications that need to store backup versions of their firmware or are way too complex and big. To solve this requirement the MCX N94x provides the capability to interface a great variety of wider and external memories. There are several traditional options to expand flash storage, but the one we are addressing is the use of external NOR  flash memories. To access an external memory the MCX N94x integrates modules that support external memory interfacing, those are  FlexIO and the FlexSPI. The FlexSPI module is capable of communicating with several kinds of memories. One of them is the Serial NOR flash which can be used as booting device. The goal of this article is to present the solution of a customer case scenario: How to run code from an external flash memory. Demonstrating the flexibility of the MCX N94x platform as well as introducing several tools, peripherals, and concepts that a developer will need to be familiar with while developing an application that runs from an external flash memory. The below figure illustrates the goal of this article, Run code from an external flash memory. The same hello world application can be run from the internal and external memory, for example, a NOR serial QuadSPI memory, without any functionality changes. The core simply will fetch and execute the instructions, using dedicated peripherals like FlexSPI.   Figure 1 Executing same code from internal memory vs external memory. The MCX N94x series integrates a FlexSPI module, which enables running code from an external NOR flash memory.   Figure 2 MCX N94x block diagram To follow this article, you will need the  FRDM-MCXN947 Development board. Which is the evaluation board for the MCX N94x and N54x MCUs. The FRDM-MCXN947 integrates a W25Q64JVSSIQ QuadSPI flash memory. Therefore, this platform is perfect for creating an application that runs from an external flash memory. Figure 3 External NOR flash memory on FRDM-MCXN947   Boot, PFR, and SPSDK   With the boot ROM  that the MCX  N integrates you can erase, program, and read the on-chip or external flash memory, which means you can use the boot ROM to download a boot image into the on-chip or external flash memory via the ISP interfaces. This article shows how to load a customized led_blinky demo, from the SDK  to the external flash memory using the boot ROM. However, other application projects may be used as well. Also, the boot ROM takes responsibility for the boot flow. It selects whether to boot from on-chip flash memory, external flash memory, or ISP mode.  The figure below shows an extremely simplified boot flow, which gives an overall understanding of the chip boot flow.  For more details on the boot flow mechanism refer to the section Top-level boot flow of the MCX Nx4x Reference manual.   Figure 4 Simplified boot Flow After the reset handling routine, the boot ROM will take control of the chip’s boot flow. It will begin with pertinent chip’s initialization. Then will check the status of the ISP pin. If the ISP pin is currently asserted, the ISP boot handling routine will be executed. ISP or  In-system programming is an execution mode where the boot ROM will wait for commands from an external host, over protocols like UART or USB, to do actions like read and write the chip memory, burn fuses, and many more. If the ISP pin is not asserted, the boot ROM will continue to determine the boot mode. Boot mode can be controlled with the CMPA[BOOT_SOURCE] bit of the CMPA of the PFR or eFUSES. If  CMPA[BOOT_SOURCE]= 01b the boot ROM will run FlexSPI NOR boot handling routine. If CMPA[BOOT_SOURCE] is 00b or 11b internal flash memory handling routine is executed. After the boot mode selection, the image will be validated. If it is not valid, for example, is not present in memory, is corrupted, or does not have proper format,  the ISP boot handling routine is executed. If the image is valid, finally the boot ROM will perform the jump to the user´s application. The default boot flow is by internal flash, most of the SDK examples will be configured to boot from internal flash, as CMPA[BOOT_SOURCE] equals zero by default, or when CMPA area is erased. According to the Simplified bot Flow diagram, we need to make boot ROM go to FlexSPI NOR boot handling routine, to boot from the external flash. Therefore, we need to make   CMPA[BOOT_SOURCE] = 01b. The PFR holds critical boot and security settings that are monitored by the boot ROM after every reset. As just described earlier, the CMPA area can be used to control boot mode. Therefore, PFR areas need to be carefully configured, as they control boot flow and also security features of the chip. The below figure shows a very minimalistic representation of the PFR containing the CMPA, next to the internal flash.   Figure 5 PFR's CMPA area   For specific details of the PFR  please refer to the MCXNx4x_IFR.xlsx, attached to the MCX Nx4x Reference Manual. To facilitate writing into the CMPA and other areas of the  PFR, signing applications, burning fuses.  programming applications, NXP already developed several host command tools, APIs, and applications and integrated into a python tool called SPSDK. The below figure shows all the tools contained by the SPSDK. To get  details on the SPSDK and description of APIs, Applications, and tools  refer to SPSDK documentation at  https://spsdk.readthedocs.io/en/latest/spsdk.html#   Figure 6 SPSDK API modules, applications, and tools The above figure highlights 3 applications, provided by the SPSDK,  that is going to be used to configure the chip to boot from the external flash memory those are: nxpdebugmbox, PRF, and BLHOST. Detailed step-by-step usage of these applications will be described later on.  The nxpdebugmbox application sends interfaces with the chip’s debug mailbox over SWD. The purpose of this tool is set MCU into ISP mode, without having to set low ISP pin,  also to make a mass erase to the chip's memory and PFR. Once the MCU enters ISP mode the host PC will be able to communicate with the boot ROM over UART or USB protocols. This enables the use of PFR and BLHOST applications. The PFR application will be used to write the CMPA[BOOT_SOURCE] = 01b and enable FlexSPI, port to probe and let the chip communicate with the external flash, in the CMPA area of the PFR. The BLHOST application will be used to erase the chip and program application image, in this particular case,  a led_blinky demo.    External Serial NOR flash interfacing   The following terms are critical to understand how we can execute code in an external NOR flash memory with the MCX N94x. First of all, Execute-in-Place refers to the capability that the MCU core has to fetch and execute instructions directly from the external memory. It refers to the capability that an MCU has to execute code from the flash memory instead of an internal and traditional flash. To do XIP the MCX  N94x requires a capable peripheral with the ability to fetch instructions from the external memory. The FlexSPI module is capable of doing this. The FlexSPI does support several types of external memories. One of them is Serial NOR Flash. To interface the external memory with the FlexSPI supports SPI. SPI is an excellent serial protocol for short-distance and high-speed communications. The term QuadSPI could be simply understood as an implementation of the SPI protocol, where instead of having a single Data line, there are 4 data lines. SPI also supports two, and eight data lines. Flexible Serial Peripheral Interface (FlexSPI) memory controller supports connection to external serial NOR, NAND, and RAMs. It supports two SPI channels and up to four external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines). Flexible sequence engine (LUT table) to support various vendor devices (serial NOR, serial NAND, HyperBus, FPGA, etc). Memory-mapped read/write access by AHB Bus AHB RX Buffer implemented to reduce read latency. Total AHB RX Buffer size: 1024 Kbytes 8 flexible and configurable buffers in AHB RX Buffer Software triggered Flash read/write access by IP Bus IP RX FIFO implemented to buffer all read data from External device. FIFO size: 1024 Bytes IP TX FIFO implemented to buffer all Write data to External device. FIFO size: 1024 Bytes DMA support to fill IP TX FIFO DMA support to read IP RX FIFO   Figure 7 FlexSPI block diagram   FlexSPI system memory map regions are remapped to different addresses at the FlexSPI sub-module:   Figure 8 FlexSPI memory map FlexSPI can support serial devices compliant with JESD216. Pre-requisites You will need the following Hardware: FRDM-MCXN947 evaluation board. USB C cable. Windows or Linux PC. You will need to install the following Software. MCUXpresso IDE v11.9.0 or above.  FRDM-MCXN947 SDK v2.15.0 or above.  SPSDK and python.     SPSDK installation and virtual environment   We recommend to run the SPSDK on a python virtual environment, as this simplifies the installation of the SPSDK. Before proceeding with installation steps for the SPSDK we recommend to create a folder in your computer. This is where the virtual environment will be running, the SPSDK tools will be called,  and all the files generated by the SPSDK will be stored. Open a terminal, command, or Power Shell prompt  and navigate to your folder and follow the SPSDK installation  commands listed in this guide: Installation Guide — SPSDK documentation            To double check installation of the SPSDK run the following command in your virtual environment. spsdk --version         This figure shows the example of this command and the spsdk version used for this document.   Figure 9 SPSDK version.  Setup  This chapter describes all steps to generate and boot an image from the external memory.  To run the commands listed in this document you will need use your python’s virtual environment. Use the virtual environment you created during SPSDK installation.  PFR settings This section describes the settings that need to be done in the MCX N94x PFR and bootable image.        Create CMPA and CFPA yaml  templates   In the following steps, we are going to focus on editing CMPA area since it contains boot-related fields for external execution.  CFPA area is not required to be edited.            Note:The commands used to generate the templates are based on ‘pfr’ tool  For details on the capabilities of these commands, visit: User Guide - pfr — SPSDK documentation First we are going to use pfr to create our yml CMPA/CFPA templates. These templates contain only the default configurations specified for the CMPA and CFPA areas of  device. If the command run successful the templates will be generated. As shown in figure this figures   Figure 10 Yaml template created.   Edit the CMPA and CFPA yaml templates   Open CMPA   template in any text editor and follow the below steps. Set DEFAULT_BOOT_SOURCE to FLEXSPI_FLASH_XIP_0b01 Set FLEXSPI_AUTO_PROBE   to ENABLE Save the changes in the CMPA template.      Create and write the  CMPA and CFPA binaries         After editing the cmpa yaml, you will generate the CMPA/CFPA binaries from the yml templates.     Import and edit image   This section shows how to create an XIP bootable image from the  MCUXpresso SDK  led_blinky example.    Import the led_blinky demo from the SDK.  Click on “Import SDK example(s)…” (1), then search and select the FRDM-MCXN947 (2), and click “Next” (3). Inside the “SDK import wizard” search and select the “led_blinky  demo (4) and click on “Finish” (5)     Figure 11 Import the blinky example.      Once the demo project is imported open the project properties. Do a right-click in the project’s name (1), then click on “Properties” option (2) and open the project properties(3)   Figure 12 Project ´properties Navigate to the Properties> C/C++ Build > MCU settings section       Figure 13 MCU settings window Make sure that there are two  Flash areas for the external memory: QSPI_FLASH and             QSPI_FCB as shown in Figure 14. If the areas are missing add them as shown in the next step.     Figure 14 External flash areas in the linker.     Add the two flash areas for the  QSPI_FLASH and QSPI_FCB in the “Memory details” table, the move them to the Top.  Click in “Add Flash”  (1) twice, then click on “Move selected memory up in table” (2), the two newly created flash areas should be placed at the top.   Note: Moving a memory area to the top of the “Memory details” table indicates the linker that text and data should be placed preferably in that area. Update the newly created flash areas name and parameters with the ones from the below table.   Type Name Alias Location Size Driver Flash QSPI_FLASH Flash 0x80001000 0xFFFF000 MCXN9xx_SFDP_FlexSPI.cfx Flash QSPI_FCB Flash 2 0x80000400 0x400 MCXN9xx_SFDP_FlexSPI.cfx     Make sure that the flash areas match the ones shown in the Figure 15.     Figure 15 Configured flash areas    Click “Build” (1), once compilation is finished, should return 0 errors (2).   Figure 16 Successfully compiled image.                                      Note: You should see that the QSPI_FLASH section is being used and that the PROGRAM_FLASH section is not. Generate the binary. Navigate to the project’s debug folder and locate generated .axf (1). Then do a right-click in the .axf, and click on Binary utilities > Create Binary.   Figure 17 Create binary.   7 The binary should appear in the debug folder. Get  easily get the binary location by doing a right click on the binary and navigating to  “Show in>System Explorer”   Figure 18 Get created binary with ease. 8. Paste the binary into the workspace where you created the cmpa_bin.bin. This step is only to simplify the commands shown later on.   Erase and ISP mode entry        ISP (In system programming ) is a mode where a host is able to instruct the ROM bootloader to program a new image or the PFR. The which holds the CMPA field with our configuration to do XIP from the external flash memory. Basically, the Host computer sends commands to the ROM bootloader to program the PFR using NXP’s BLHOST. To enter into ISP mode there are two options: ISP pin entry and Debugger mailbox. ISP pin entry requires keeping ISP pin asserted during reset sequence and de-asserting this pin after reset has been completed. Debugger mailbox only requires to use of a SWD debugger to make the ROM entry ISP mode. To enter into ISP mode over ISP pins follow is necessary keep ISP pin asserted during reset sequence and de-assert this pin after reset has been completed. To use the debugger mailbox is only needed having a debugger. For simplicity, the communication protocol will be USB. However, UART can be used as well. Erase the flash memory and enter ISP mode using the nxpdebugmbox. Proceed to run each command nxpdebugmbox erase  nxpdebugmbox ispmode -m 0   This figure shows the expected output when running the two commands from above.   This operation will erase the contents on the internal and external flash memory. Also the PFR contents. Repeating this operation can be useful to get the chip to boot from internal flash memory. Note:  nxpdebugmbox commands need to be run using a SWD-JTAG debugger. For this example on-board debugger of the FRDM-MCXN947 is used. Ping rom Bootloader  Run the following command to ping the rom Bootloader, this way we can ensure that the device was set correctly in ISP mode. blhost  -t 2000 -p COMxxx,115200 -j -- get-property 1     Figure 19 Ping rom Bootloader From now on, an external debugger is not strictly required. The communication with the rom bootloader can be done over UART or USB. For simplicity, the UART protocol-based commands are used from now on in the rest of this document. Write  image and PFR and run demo   We are going to follow the steps to write image.  1 Write CMPA binary. pfr write -p COMxxx,115200 -t cmpa -f mcxn9xx -b cmpa_bin.bin   2 Write CFPA binary. pfr write -p COM140,115200 -t cfpa -f mcxn9xx -b cfpa_bin.bin   3 Provide FlexSPI flash memory configuration blhost  -t 2000 -p COMxxx,115200 -- fill-memory 0x20000000 0x04 0xc0000405   4 Configure and fill memory. blhost  -t 2000 -p COMxxx,115200 -- configure-memory 0x09 0x20000000 blhost  -t 2000 -p COMxxx,115200 -- fill-memory 0x20003000 0x04 0xf000000f   5 Erase flash blhost  -t 2000 -p COMxxx,115200 -- flash-erase-region 0x80000000 0x100000   6 Configure memory. blhost  -t 2000 -p COMxxx,115200 -- configure-memory 0x09 0x20003000    7 Write image. blhost  -t 2000 -p COMxxx,115200 write-memory 0x80001000 frdmmcxn947_led_blinky.bin   8 Reset. blhost  -t 2000 -p COMxxx,115200 reset You might use this command or directly press the reset button from the FRDM board. The below image shows the successful execution of each command. Your FRDM-MCXN947  should be blinking by now. Figure 20 Successful image write and reset. Once the board is reset you will notice that the loaded example will begin to execute.    Double-check execution from external flash    To double-check that the image is executing from the external flash you can use the disassembly view from MCUXpresso. 1  Attach the debugger to the running target and place a breakpoint at any part of the code.   Figure 21 Attach debugger to a running target. Once your debug probe is discovered, click “OK.”   Halt the processor execution. Use the debug button.   Figure 22 halt execution. Reset processor. Use the “Restart button”. The program should be stop at the first line of the main function.   Figure 23 Breakpoint at main. Find and open the disassembly view. Click on “Instruction Stepping Mode” button or search for disassembly. Any option will open the MCUXpresso “Disassembly” view.   Figure 24 Open "Disassembly" view Processor must be running at 0x8000_0000 address space. On the disassembly view you can check that the instructions are executed from address on the range of 0x8000_xxxx which is assigned for external flash.   Figure 25 Running code from external flash. If you want to return the device to run from internal memory, then you need to go back to default values. If there are no modifications, to the ones shown in this document,  to the CMPA and CMPA areas, the nxpdebugmbox command can be executed.      

Introduction The MCX N has a Programmable Logic Unit (PLU) capable of creating combinational and sequential logic circuits that operate independently of the cores. The PLU does this by preprogramming look up tables or LUTs that dictate the behavior of designated outputs for all inputs of the PLU. The features of the MCX N PLU module includes: An array of 26 inter-connectable, 5-input look-up table (LUT) elements. 4 flip-flops. Six primary inputs pins. Eight primary output pins. An external clock to drive the four flip-flops if a sequential network is implemented. Capability to generate interrupts and wakeup requests from Sleep and Deep Sleep modes.   Module architecture The PLU is composed of 3 main elements: Look Up Tables (LUTs), Multiplexers and Flip Flops. Look Up Tables are used to create the actual logic of the PLU’s network, while multiplexers route these logic signals to and from other LUTs, as well as the PLU’s input and output pins. Flip Flops provide a method of gating logic signals from LUT elements to a shared clock input, adding a mechanism of synchronization and delay to the logic network.   Look Up Table (LUT) The PLU module has 26 inter-connectable Look Up Tables (LUTs), which can implement any combinational function with up to five inputs at once. The LUTs work by storing a pre-programmed output for every combination of inputs. This allows the look up tables to reproduce a specific output of logical 0 or 1 as soon as the input is changed without any processing required. By interconnecting LUT elements with one another, more complex programmable networks can be achieved, providing functionality of many logic gates at once.   Multiplexers The PLU module includes a variety of multiplexers that select the inputs and outputs for each Look Up Table (LUT) element. Each LUT element has 5 input multiplexers that route a signal to each of its 5 inputs. The available input signals for each LUT include: PLU Input pads. Other LUT element outputs. State Flip Flop outputs.   The PLU also has one output multiplexer for each PLU output pad (eight in total) that selects what Look-Up Table or Flip Flop state will drive each output pad.   Flip Flops The final PLU element is a type D flip flop that allows for retention of data, providing the means for sequential logic circuits and simple state machines.   The PLU module has 4 flip flops that are connected to the outputs of LUTs[3:0] as well as the external PLU_CLKIN signal that is used for timing and synchronization between flip flops. In order to use the flip flop elements, a clock signal must be supplied via the PLU_CLKIN pad. Note that since the flip flops are directly connected to the outputs of the first 4 LUT elements, the corresponding LUT elements must be set up in order to use each Flip Flop element.     PLU Setup The following steps must be done in order to achieve a logic network on the PLU module: Enable clocks for the PLU using the SYSCON_SYSAHBCLKCTRLx register and then toggle the PLU Reset bit from the SYSCON_PRESETCTRLx register. Assign pins using the PORTx_PCRn registers. Create logic network using the following steps: Write the logic behavior in the truth table register for each of the LUT elements that will be used. Program the input multiplexer registers to select the source of up to five inputs presented to each LUT. Program the output multiplexer register to select up to eight primary outputs from the PLU module. (Optional) Set the wakeup behavior by using the WAKEINT_CTRL register to select the outputs to be used as wakeup sources, as well as setting a deglitching method.   Creating logic networks Basic logic gates With a simple configuration of two inputs and one output on a single LUT element, all of the basic logic gates can be achieved. This would be achieved, for example, using a configuration of PLU_IN0 and PLU_IN1 pads as inputs and PLU_OUT0 pad as output for LUT0.   The first step of creating any logic network is to understand the truth table of the desired logic circuit. For a single AND gate using the previous configuration, the truth table would equate to the following: #   PLU_IN1 PLU_IN0 PLU_OUT0 0   0 0 0 1   0 1 0 2   1 0 0 3   1 1 1   The LUT would have to be set up in a way were the output is HIGH only when PLU_IN1 and PLU_IN0 are both HIGH, which is coincidentally the third combination of the LUT inputs for the previous truth table. Therefore, we need to program the LUT to output HIGH for combination #3. We can program this logic gate by writing a '1' on bit number 3 of the LUT’s truth table register. This way, when both LUT0 inputs are HIGH, the LUT element will “look up and find” a ‘1’, so it will output HIGH. On the other hand, for every other combination it will find a ‘0’ and output LOW. Combination # (Input) Truth table register (Output) 0 (0b00) 0 1 (0b01) 0 2 (0b10) 0 3 (0b11) 1   Taking this into account, it is easy to see that all the LUT element does is "look up" each combination of inputs on a predefined table to know what logic to output. This table is programmed via the 32 bit LUTa_TRUTH register for each LUT element. The 32 bit value required for the previous logic gate expressed in hexadecimal would then be as follows: AND gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 1 0 0 0 → 0x00000008 And, for the rest of the basic logic gates: OR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 1 1 1 0 → 0x0000000E   XOR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 0 1 1 0 → 0x00000006   NAND gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 0 1 1 1 → 0x00000007   NOR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 0 0 0 1 → 0x00000001   XNOR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 1 0 0 1 → 0x00000009   NOT gate LUT inputs[0] 1 0     LUT0_TRUTH 0 1 → 0x00000001   Buffer gate LUT inputs[0] 1 0     LUT0_TRUTH 1 0 → 0x00000002   Note that the truth table value for a NOR gate and a NOT gate is the same in this case, as both require an output of ‘1’ for the first combination of inputs and ‘0’ for the rest. This demonstrates how the PLU does not actually create an array of logic gates but rather, simply outputs predefined values from a table of all possible combinations of inputs. The previous tables show the register values to achieve all of the basic logic gates with the previous setup of LUT0. However, in order to achieve this configuration with input pins PLU_IN0 and PLU_IN1 as well as output pin PLU_OUT0, the multiplexers would have to be set up in the following manner:   In order to achieve this, pin PLU_IN0 must be routed as input[0] of LUT0 and PLU_IN1 as input[1] of LUT0. Additionally, the output of LUT0 will be routed to the PLU_OUT0 pad. This configuration to set up both input sources, route the output source and write the truth table register to result in an AND gate can be achieved with the following code:   /* Select input pin PLU_IN0 as LUT Input 0 (Input MUX0) for LUT0 on module PLU0 */ PLU_SetLutInputSource(PLU0, kPLU_LUT_0, kPLU_LUT_IN_0, kPLU_LUT_IN_SRC_PLU_IN_0); /* Select input pin PLU_IN1 as LUT Input 1 (Input MUX1) for LUT0 on module PLU0 */ PLU_SetLutInputSource(PLU0, kPLU_LUT_0, kPLU_LUT_IN_1, kPLU_LUT_IN_SRC_PLU_IN_1); /* Set Truth Table 0x08 for LUT element 0 on module PLU0 */ PLU_SetLutTruthTable(PLU0, kPLU_LUT_0, 0x08); // This will result in an AND gate /* Select LUT0 output as driver for PLU_OUT0 pin on module PLU0 */ PLU_SetOutputSource(PLU0, kPLU_OUTPUT_0, kPLU_OUT_SRC_LUT_0);   Conclusion The PLU module of the MCX N is modest when it comes to the complexity of the inner components as it is only made up from a series of look-up tables, multiplexers and flip flops. In spite of that, more elaborate and powerful logic networks can be achieved from those basic elements, providing on-chip solutions to many essential digital circuits and avoiding the need of external components for these digital applications. Not only that, but its interruption and wake up capabilities also enable the PLU to be a simple but effective addition to many low power applications. The PLU’s flexibility and built-in features enable this module to be a very effective addition to the MCX N series of MCUs that should not be overlooked. More information as well as example codes for combinational, sequential, and low-power applications can be found on the full article on Application Code Hub.

Ⅰ、Introduction MCXA153 supports Read Out Protection (ROP) to protect code from reading from the device internal flash. This read out protection is a mechanism that allows user to enable different levels of protection in the system. This article explains in detail the configuration of the four ROP levels as well as the relationships between the different levels and the corresponding life cycles. Ⅱ、Four levels of Read Out Protection (ROP) The ROP is controlled by ROP_STATE bits, It is a 32-bit field stored in IFR0. It can be programmed by customer. Below is an introduction to the four ROP levels： 1.ROP_LEVEL0 ROP_STATE = 0xFFFF_FFFF (erased FLASH value), No ROP. Default for blank state. 2.ROP_LEVEL1 ROP_STATE = 0x0000_0003 Debug is disabled and unlocked, however it can be modified by customer, only limited debug mailbox commands are available. 3 .ROP_LEVEL2 ROP_STATE = 0x0000_0001 Debug is disabled and locked, it cannot be modified by customer, only limited debug mailbox commands are available. 4.ROP_LEVEL3 ROP_STATE = 0x0000_0000 Debug is disabled and locked, it cannot be modified by customer, no debug mailbox commands are available NOTE：Anything else = ROP3-like behavior (Debug disabled/Locked, ISP disabled). When the ROP level is 0, we can change the ROP level to 1, 2, and 3 by modifying the value of ROP_STATE in IFR0.When the ROP level is 1 or 2, we can change the ROP level to 0 through the ISP or DM-AP command. ROP level 3 is a one-way trip, so be careful. Below is a diagram of the relationship between the four levels：   Ⅲ、Life cycle and ROP When the chip is delivered to the customer from NXP, the life cycle is “NXP Provisioned”, we can also call it “OEM Open”, ”OEM Field return”, “NXP Field Return”. Because at this point, the chip is completely blank, and ISP and debugging functions are allowed. Of course, the ROP level at this point is 0. In this lifecycle, customers can develop and debug. During customer production, customers can impose certain restrictions on ISP and debugging based on their needs through ROP. Customers can choose between ROP level 1 or ROP level 2. The lifecycle at this point is “OEM Closed”. In this lifecycle, when there are some quality issues, customers can use the ISP or DM-AP command to erase the entire chip, or use the DM-AP command “set FA” to transfer the chip life cycle to the initial state, and return it to NXP’s factory for analysis without storing any IP assets. In some scenarios, customers may need to completely disable ISP and debugging functions. In that case, customers can set the ROP level to 3, and the chip’s lifecycle is “OEM No Return”. Please note that at this point, even NXP cannot restore the chip. So once there are some CQC issues, our factory cannot conduct further analysis. Also, we can transfer the chip to a ‘Bricked’ state in any lifecycle. During “Bricked” lifecycle, the chip will not be booted and will become a brick. The following table shows the relationship between life cycle and ROP: Ⅳ. Impact of different ROP levels on SWD and ISP The supported SWD and ISP commands are different at different ROP levels. From ROP0 to ROP3, fewer commands are supported. The following figure shows the commands supported by SWD and ISP at different ROP Levels. ISP commands supported in ROP0-ROP3:   SWD DM-AP commands supported in ROP0-ROP3:   Ⅴ、Configure ROP with SEC tool We can configure ROP through the MCUXpresso Secure Provisioning( SEC) tool. The MCUXpresso Secure Provisioning Tool is a GUI-based application provided to simplify generation and provisioning of bootable executables on NXP MCU devices. Hardware requirements: FRDM-MCXA153 board、Type-C USB cable Software requirements: MCUXpresso Secure Provisioning (MCUXpresso Secure Provisioning v8_b240110 or later.) Configuration steps: Step1. Create a new workspace After opening the software, click File->New Workspace, select "MCX A14x/A15x" -> MCXA153 -> Click "create". Refer to the following figure: Step2. Connection with Target Processor Enter ISP mode：Press and hold SW3(ISP key) => Press and release SW1 (RESET key) => Release SW3 Go to your workspace and click “Target”->Connection, the Connection with Target Processor window is displayed. Here, we make Connection through UART and select port and baud rate. Refer to the following figure: We can click "Test connection" to check whether the connection is successful. If the connection is successful, the result will display "OK". We can also see the life cycle of the current board: OEM Open. Refer to the following figure: Step3.Select Life Cycle Settings ROP Click on the toolbar "OEM Open" According to the requirements, select the appropriate ROP, in this case ROP 2. NOTE: Use ROP 3 with caution. Refer to the following figure: Step4. Build image After completing the above operations, we need to load the .s19 or .hex file generated by MCUXpresso IDE into the Source executable image. After the file is loaded, the start address is automatically identified. If the start address is not 0x00000000, you cannot "built image". Then click on "built image". Refer to the following figure: After completing the built image, "SUCCECC: built image" will be displayed. Click "close". Refer to the following figure: Step5. Write image We can see that the required .bin file has been generated automatically in "write image", or we can import the corresponding .bin file we wrote by "import". The Image path file will be automatically loaded. Clicking "write image" will pop up to confirm, and then click "ok" to run the script automatically. After the file is successfully written, the message "SUCCESS: write image" is displayed. Refer to the following figure: Step6. Check When we complete the configuration of ROP 2, we can check the status of registers through "PFR configuration". The used registers cannot be read out and unknown is displayed, as shown in the following figure: Finally, by pressing the RESET key on the board to exit ISP mode. At this point, the board has entered ROP 2, debug is disabled. The method of entering other ROP levels is the same. So how do we get back to the other ROP levels? ROP 2 state debugging is disabled, even the IDE cannot operate, we can only use ISP command and SWD command to operate. The SEC tool integrates SWD bulk erase command to return to ROP 0. However, we can also use the Blhost software to use ISP command, enter the ISP mode, enter “blhost -p comxx -- flash-erase-all” and return to ROP 0. Next, we'll look at using the SWD bulk erase command. Click on the toolbar "Dbg": The Select Debug Probe window is displayed. Refer to the following figure: Select “Probe: ”and click “erase”. After the erase succeeds, the following message is displayed: Flash mass erase succeeded! So we've successfully returned to ROP 0. Ⅶ、Summary ROP function protects the security of the chip, users can set different levels of ROP according to the requirements of their own applications. Using MCUXpresso Secure Provisionin simplifies the ROP configuration process. Configuring different ROPs requires modifying the status bits of ROP_STAT and ROP_STAT_DP in CMPA. The SEC tool helps us automate this work through a GUI interface.                               

Developing code for MCXN family from Scratch The MCX family is a newly released MCU family, of course, the SDK package includes almost all the examples of the MCXN modules based on the SDK driver, for example led_blinky which shows the method of toggling GPIO, CTimer interrupt, etc. While the program in this article doesn’t use SDK driver. It focuses on understanding the related module from register level which is friendly to beginners to understand MCX working mechanism. The doc introduces how to toggle a GPIO, how to have CTimer generate interrupt, and in the CTimer ISR, toggle a LED, while it also describes how to initialize the NVIC so that CTimer can generate ISR by writing the module registers without calling the SDK driver. Environment: FRDM-MCXN947 board MCUXPresso IDE v11.9.0 IDE on Win10 OS   1. Toggle a LED On the FRDM-MCXN947 board, the PIO0_10(P0_10) of MCXN947 is connected to a LED. With MCUXPresso IDE with v11.9.0, you can add the code to test the LED toggling and CTimer interrupt function.   1.1 Configure the PIO0_10 pin as GPIO0_10 pin SYSCON->AHBCLKCTRLSET[0]=1<<13; PORT0->PCR[10]=0x1000; Before you initialize the PORT0 register to assign the PIO0_10 function, you have to enable the PORT0 gated clock in the SYSCON->AHBCLKCTRL0 reg. Write the PORT0->PCR[10]=0x1000; to configure the PIO0_10 as GPIO0_10 function. 1.2 Configure the GPIO0_10 pin as GPIO output mode and toggle the GPIO pin. SYSCON->AHBCLKCTRLSET[0]=1<<19; GPIO0->PDDR|=1<<10; GPIO0->PTOR=1<<10; Before you initialize the GPIO0 registers, you have to enable the GPIO0 gated clock in the SYSCON->AHBCLKCTRL0 reg. Set the bit 10 of GPIO0->PDDR so that the GPIO0_10 is in GPIO output mode. Toggle GPIO0_10 pin by writing the bit 10 in GPIO0->PTOR reg   Set a break point in the debugger on the GPIO0->PTOR=1<<10; line,and run step by step, you can see that led toggles.   2. Initialize CTimer 2.1 enable Ctimer gated clock and clock source and divider. Before you initialize the CTimer register, you have to enable the CTimer gated clock. For example, enable CTimer4 gated clock with the line： SYSCON->AHBCLKCTRLSET[2]=1<<22; You have to also select the CTimer clock source and Ctimer clock divider. For example, set the CTimer4 clock source and divider. SYSCON->CTIMERCLKSEL[4]=0x04; SYSCON->CTIMERCLKDIV[4]=0x02; //P0_10 is LED red void GPIOInit(void) { SYSCON->AHBCLKCTRLSET[0]=1<<13; PORT0->PCR[10]=0x1000; //enable gated clock of GPIO SYSCON->AHBCLKCTRLSET[0]=1<<19; GPIO0->PDDR|=1<<10; GPIO0->PTOR=1<<10; //set break point here GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; } 2.2 Initialize the CTimer register. CTIMER4->CTCR=0x00; CTIMER4->PR=0x00; //set the CTimet4 mode and enable interrupt for match0 CTIMER4->MCR=0x03; CTIMER4->PWMC=0x00; //set the CTimer4 cycle time CTIMER4->MR[0]=2000000; CTIMER4->MSR[0]=2000000; //Start up CTimer4 CTIMER4->TCR=0x01; 2.3 Initialize the NVIC The IRQ number of CTimer4 is 56, so you have to set the bit 24 of both NVIC->ISER[1]|=1<<24; NVIC->ICPR[1]|=1<<24; and set the priority of NVIC->IPR[56] with 0x00; NVIC->IPR[56]=0x00;   //CTimer4 IRQ 56, 56-32=24 void cTimer0Init(void) { //CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1u); //CLOCK_AttachClk(kFRO_HF_to_CTIMER4); //enable Ctimer4 gated clock SYSCON->AHBCLKCTRLSET[2]=1<<22; SYSCON->PRESETCTRLSET[2]=1<<22; SYSCON->PRESETCTRLCLR[2]=1<<22; SYSCON->CTIMERGLOBALSTARTEN|=1<<4; //select CTimer4 clock source SYSCON->CTIMERCLKSEL[4]=0x04; SYSCON->CTIMERCLKDIV[4]=0x02; //init the CTimer0 CTIMER4->CTCR=0x00; CTIMER4->PR=0x00; CTIMER4->MCR=0x03; CTIMER4->PWMC=0x00; CTIMER4->MR[0]=2000000; CTIMER4->MSR[0]=2000000; //CTIMER0->IR=0x01; CTIMER4->TCR=0x01; NVIC->ISER[1]|=1<<24; NVIC->ICPR[1]|=1<<24; NVIC->IPR[56]=0x00; } 2.3 Each interrupt source has unique interrupt service routine in the file startup_mcxn947_cm33_core0.c For the CTimer4 ISR, it is called: CTIMER4_IRQHandler So it is okay to fill the function: void CTIMER4_IRQHandler(void) { //clear flag CTIMER4->IR|=0x01; //toggle LED GPIO0->PTOR=1<<10; } In conclusion, the doc gives a snippet which can toggle a LED by writing the register directly. It also give the code to configure CTimer4 so that it can generate interrupt, in the ISR, toggle a LED. Appendix This is the entire source code:   /* * Copyright 2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "pin_mux.h" #include "peripherals.h" #include "board.h" /******************************************************************************* * Definitions ******************************************************************************/ void clockOUTInit(void); void GPIOInit(void); void cTimer0Init(void); void MRTInit(void); /******************************************************************************* * Prototypes ******************************************************************************/ /******************************************************************************* * Variables ******************************************************************************/ /******************************************************************************* * Code ******************************************************************************/ /*! * @brief Main function */ int main(void) { /* Board pin init */ CLOCK_EnableClock(kCLOCK_Gpio0); BOARD_InitPins(); BOARD_BootClockFRO12M(); //FlexPWMPinInit(); GPIOInit(); cTimer0Init(); //MRTInit(); __asm("nop"); while (1) { } } //P0_10 is LED red void GPIOInit(void) { SYSCON->AHBCLKCTRLSET[0]=1<<13; PORT0->PCR[10]=0x1000; //enable gated clock of GPIO SYSCON->AHBCLKCTRLSET[0]=1<<19; GPIO0->PDDR|=1<<10; //set a break point here and run step by step GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; GPIO0->PTOR=1<<10; } //CTimer4 IRQ 56, 56-32=24 void cTimer0Init(void) { // CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1u); // CLOCK_AttachClk(kFRO_HF_to_CTIMER4); //enable Ctimer4 gated clock SYSCON->AHBCLKCTRLSET[2]=1<<22; SYSCON->PRESETCTRLSET[2]=1<<22; SYSCON->PRESETCTRLCLR[2]=1<<22; SYSCON->CTIMERGLOBALSTARTEN|=1<<4; //select CTimer4 clock source SYSCON->CTIMERCLKSEL[4]=0x04; SYSCON->CTIMERCLKDIV[4]=0x02; //init the CTimer0 CTIMER4->CTCR=0x00; CTIMER4->PR=0x00; CTIMER4->MCR=0x03; CTIMER4->PWMC=0x00; CTIMER4->MR[0]=2000000; CTIMER4->MSR[0]=2000000; //CTIMER0->IR=0x01; CTIMER4->TCR=0x01; NVIC->ISER[1]|=1<<24; NVIC->ICPR[1]|=1<<24; NVIC->IPR[56]=0x00; } void CTIMER4_IRQHandler(void) { //clear flag CTIMER4->IR|=0x01; //toggle LED GPIO0->PTOR=1<<10; } //MRT0 interrupt IRQ is 30 void MRTInit(void) { SYSCON->AHBCLKCTRLSET[1]=1<<0; SYSCON->PRESETCTRLSET[1]=1<<0; SYSCON->PRESETCTRLCLR[1]=1<<0; MRT0->CHANNEL[0].INTVAL=6000000; MRT0->CHANNEL[0].INTVAL|=1<<31; MRT0->CHANNEL[0].CTRL=0x01; NVIC->ISER[0]|=1<<30; NVIC->ICPR[0]|=1<<30; NVIC->IPR[30]=0x00; } void MRT0_IRQHandler(void) { if(MRT0->CHANNEL[0].STAT&0x01) { MRT0->CHANNEL[0].STAT|=0x01; } //toggle LED GPIO0->PTOR=1<<10; }

Ⅰ、Introduction The MCUXpresso Secure Provisioning Tool (SEC) tool is a GUI-based application provided to simplify generation and provisioning of bootable executables on NXP MCU platforms. The latest version of SEC v8 adds FCB configuration function to help users program image to external flash. The MCX N94x family is a typical product series of MCX. A controller with a flexible serial peripheral interface (FlexSPI) that supports external memory. The external flash has a large storage capacity, high flexibility. It is relatively independent of the replacement or upgrade of the main chip, and has high reliability and lifecycle. This article focuses on how to use SEC tools to configure and program MCXN947 external flash quickly and easily. Ⅱ、Configuration steps This article uses the FRDM-MCXN947 board as an example to configure FCB and download an external flash image. Hardware requirements: FRDM-MCXN947 board、Type-C USB cable Software requirements: MCUXpresso Secure Provisioning Tool | NXP Semiconductors Step1. Create new workspace  After opening the software, click File->New Workspace, select "MCX N94x/N54x" -> MCXN947 -> Click "create". Refer to the following figure: Step2. Connection with Target Processor Enter ISP mode：Press and hold SW3(ISP key) => Press and release SW1 (RESET key) => Release SW3 Go to your workspace and click “Target”->Connection, the Connection with Target Processor window is displayed. Here, we make Connection through UART and select port and baud rate. Refer to the following figure: We can click "Test connection" to check whether the connection is successful. If the connection is successful, the result will display "OK". Refer to the following figure: Step3. Boot memory configuration Next we need to configure FCB. Click on "Target"-> Boot Memory… ,The Boot memory configuration window is displayed. First we need to select the Boot memory type, this part allows selection of the boot memory type, and optionally instance. The selection contains all memory types but unsupported types are disabled. FlexSPI NOR flash can be configured in two ways: By using the flashloader/ROM based simple configuration in the Boot Memory Configuration dialog or By using the complete FCB (FCB binary), which can be prepared from the boot device configuration as well, or via MCUXpresso IDE by adding the FCB component into Peripheral Drivers in Peripherals tools, where the full configuration can be specified. Here we use a simple configuration, click "FlexSPI NOR-simplified", on this Predefined template, select W25Q64JW and click apply. Then, corresponding parameters on W25Q64JW will be automatically created on Boot memory configuration parameters. Normally, keep the default value. Refer to the following figure: We use "Test the configuration" to check whether the configuration is correct. After clicking "Test", the script will pop up to run automatically, and "SUCCESS" will be displayed after running. Refer to the following figure: Then click "convert to FCB" and the "convert to FCB" dialog box will pop up. Keep the default position of "FCB file path". Select "Apply the converted FCB as boot device configuration" and click "convert". The script automatically runs and generates "converted_fcb.bin". The FlexSPI NOR-complete FCB window is displayed. Refer to the following figure: The generated converted_fcb.bin file is automatically loaded to FCB file for runtime and FCB File for write. Click "Test" and "SUCCESS" will be displayed. Click "OK" to close the window. Refer to the following figure: Step4. Build image After completing the above operations, we need to load the .s19 or .hex file generated by MCUXpresso IDE into the Source executable image. Note: The start address of the external flash of the project needs to be changed to 0x80001000. This section does not explain how to change the start address. For details, see “How to config booting from external flash”. After the file is loaded, the start address is automatically identified. If the start address is not 0x80001000, you cannot "built image". Then click on "built image". Refer to the following figure: After completing the built image, "SUCCECC: built image" will be displayed. Click "close". Refer to the following figure: Step5. Write image We can see that the required .bin file has been generated automatically in "write image", or we can import the corresponding .bin file we wrote by "import". The Image path file will be automatically loaded. Click "write image" to run the script automatically. After the file is successfully written, "SUCCESS: write image" is displayed. Refer to the following figure: Finally, by pressing the RESET key on the board to exit ISP mode, we completed the configuration and downloaded the external flash image. Ⅲ、Summarize We use SEC Tool to configure FCB and download external flash images via GUI. This is just a simple method, and users can choose different ways according to their requirements.

  This guide helps you to: Get familiar with NPU inside the MCX Know eIQ ML examples included in SDK. Summarize related application notes and demo projects on GitHub Prerequisites: Windows 10 development PC. FRDM-MCXN947 board NXP’s  MCUXpresso IDE is installed on the development PC Generate and download FRDM-MCXN947 SDK package from the web-based MCUXpresso SDK builder. Introduction to NPU The MCXN94x and MCXN54x are based on dual high-performance Arm® Cortex®-M33 cores running at up to 150 MHz, it has 2MB of on-chip Flash with optional full ECC RAM and an integrated proprietary NPU. The integrated NPU delivers up to 40x faster machine learning (ML) throughput compared to a CPU core, enabling it to spend less time awake and reducing overall power consumption. The architecture provides power and performance-optimized NPUs integrated with NXP's very wide portfolio of microcontrollers and applications processors. The eIQ Neutron NPUs offer support for a wide variety of neural network types such as CNN, RNN, TCN, and Transformer networks and more. ML application development with the eIQ Neutron NPU is fully supported by the eIQ machine learning software development environment. The NPU used in MCXN94 is Neutron N1-16, its block diagram is shown in the below figure. The eIQ Neutron N1-16 NPU found inside the MCXN94 has 4 compute pipes and each compute pipe contains 4 INT8 MAC (Multiply Accumulate) blocks for a total of 16 MAC blocks. This means that MCXN94 could execute 4.8G(150MHz * 4 * 4 * 2) INT8 operations per second. The MCUXpresso Software Development Kit (MCUXpresso SDK) provides a comprehensive software package with a pre-integrated TensorFlow Lite for Microcontrollers (TFLM). The Neutron library is integrated into TFLM as well. The following table shows the operators which are supported by the NPU. Operator Operator input type MCXN947/MCXN548 NPU ADD Float No Uint8(PTQ) No Int8(PCQ) Yes AVERAGE_POOL_2D Float No Uint8(PTQ) No Int8(PCQ) Yes CONV_2D Float No Uint8(PTQ) No Int8(PCQ) Yes DEPTHWISE_CONV_2D Float No Uint8(PTQ) No Int8(PCQ) Yes FULLY_CONNECTED Float No Uint8(PTQ) No Int8(PCQ) Yes UNIDIRECTIONAL_SEQUENCE_ LSTM Float No Uint8(PTQ) No Int8(PCQ) No LOGISTIC (Sigmoid) Float No Uint8(PTQ) No Int8(PCQ) Yes MAX_POOL_2D Float No Uint8(PTQ) No Int8(PCQ) Yes MUL Float No Uint8(PTQ) No Int8(PCQ) No SOFTMAX Float No Uint8(PTQ) No Int8(PCQ) No SVDF Float No Uint8(PTQ) No Int8(PCQ) No Note: PTQ — Per-tensor quantized (asymmetric 8-bit quantization). PCQ — Per-channel quantized (symmetric 8-bit quantization). For more information please refer to eIQ TensorFlow Lite User's Guide.pdf in middleware/eiq/doc of SDK. eIQ ML examples included in SDK. Download SDK and select FRDM-MCXN947 in MCUxpresso SDK Builder, Remember to select eIQ middleware. Then open MCUXpresso, it’s convenient to install the SDK by dragging and dropping the file into the SDK installation window of the MCUXpresso IDE. Import SDK examples into the workspace: There are 7 ML examples included in SDK: Here are the descriptions of the eIQ examples: eIQ example Description Hardware requirements tflm_cifar10 CIFAR10 example based on TensorFlow Lite Micro, recognizes a static image FRDM-MCXN947 USB type-c cable tflm_kws Keyword spotting example based on TensorFlow Lite Micro recognizes a static WAV audio FRDM-MCXN947 USB type-c cable tflm_label_image Label 1000 classes of images based on TensorFlow Lite Micro FRDM-MCXN947 USB type-c cable mpp_camera_mobilenet_view_tflm Label camera images based on TensorFlow Lite Micro FRDM-MCXN947 LCD: MikroElektronika TFT Proto 5" OV7670 module USB type-c cable mpp_camera_ultraface_view_tflm Face detection using the camera as the source, based on TensorFlow Lite Micro FRDM-MCXN947 LCD: MikroElektronika TFT Proto 5" OV7670 module USB type-c cable mpp_camera_view A simple camera preview pipeline. FRDM-MCXN947 LCD: MikroElektronika TFT Proto 5" OV7670 module USB type-c cable tflm_modelrunner TFLite Model Benchmark example for Microcontrollers. FRDM-MCXN947 RJ45 Network cable For additional information and guidance, kindly refer to the README file located in the doc folder that accompanies each example. Summary of related application notes There are two application notes available that provide information on advanced usage of NPU. How to Integrate Customer ML Model to NPU on MCXN94x Face Detection demo with NPU accelerated on MCXN947. Please find the notes on the NXP website Summary of demo projects on GitHub There are five demos on nxp-appcodehub from GitHub: Multiple Face detection on FRDM-MCXN947 Multiple person detection on FRDM-MCXN947 Label CIFAR10 images on FRDM-MCXN947 Fashion-MNIST recognition on FRDM-MCXN947 NPU vs TensorFLM benchmark on MCX  

Abstract   This Knowledge Base text is intended to be an introduction for the MCX A14x/15x Architecture. Therefore, the content that is presented is described in a simplified way.   Contents 1. Introduction  2. Bus and Memory Architecture  3. MCX N vs MCX A series  4. MCXA SoC Power Domain Configuration 5. Clock Tree  6. Life Cycle and ROP State  7. Closing remarks    1.    Introduction   The MCX is the new MCU for NXP generic-purposes microcontrollers. Its portfolio offers a comprehensive selection of Arm® Cortex®-M based MCUs offering expanded scalability with breakthrough product capabilities simplified system design, and a developer-focused experience thought the widely adopted MCUXpresso suite of software and tools. Particularly, the MCXA series MCUs expands the MCX Arm® Cortex®-M33 product offerings with multiple high-speed connectivity, operating up to 96 MHz, serial peripherals, timers, analog and low power consumption. This device has following target applications: Consumer and industrial IoT Industrial Communications Smart Metering Automation and Control Sensors The following figure shows a top-level organization of the modules within the chip organized by functional category. Figure 1. Features block diagram   2.    Bus and Memory Architecture   The memory system of the device includes SRAM, ROM, internal flash, and external memory. The following figure shows the Bus matrix block diagram of this chip. Where there are three bus initiators (CM33, DMA and USB FS) which to access to different slave ports thought a Multilayer AHB bus matrix. ROM, Flash and RAMX0/1 share the same slave port. RAMA0/1 share a second slave port. And the third slave port is used to access to the peripherals.   Figure 2. Bus matrix block diagram   The Bus matrix block diagram has de following features: CM33 Max speed is 96MHz Does not include MPU, FPU, DSP and Trustzone Cache 4KB LPCAC on CM33 code bus 8-way, 2-set-associative design based on 256-byte superpages. The access to flash can be cached. Write through Flash Up to 128KB flash. Line buffer and prefetch buffer IFR0 sector0 is CMPA region Memory Block Checker (MBC) is used to control the access permission Swap RAM SRAM is divided into Code TCM and System TCM: CTCM: Mapped to CM33 code bus space RAM X0: 8 KB 32-bit RAM RAM X1: 4 KB 32-bit RAM Can only be used as code RAM when LPCAC is disabled. STCM: Mapped to CM33 system bus space: RAM A0: 8 KB 32+7-bit ECC RAM RAM A1: 16 KB 32bit RAM Execute permission is configurable Remap When remap is enabled, the access to RAM X0, will be remapped to the end of system RAM   3.    MCX N vs MCX A series   The MCX N series have feature-rich on-chip accelerators and peripheral sets. Aimed at applications that need higher performance and fast features. The MCX A series have several device options for a wide range of applications. Provides coverage for all applications requiring microcontrollers in entry-level target products. The following table summarizes the main features of the MCX A and the MCX N series to compare their differences. Table 1. Feature Comparison between MCX N and MCX A series Description MCXN94x MCXA14x/15x Comments System 2x DMA3, CRC, 2x WWDT, SPC, SCG, EIM, ERM, INTM, EWM, SYSCON, WUU, CMC, VBAT 1x DMA3, CRC, WWDT, SPC, SCG, CMC, VBAT, EIM, ERM, SYSCON, WUU - MRCC in MCXA SYSCON is used to control peripherals’ clock select, clock divider and clock gating. - SPC and SCG programming model is forward compatible with MCXN. Security S50, PKC, PUF, TRNG, SM3, 2x GDET, Tamper, eFuse, ITRC, 2x CDOG, LVD/HVD, ROP (Read out protection), 1x CDOG, GLIKEY   Clocking 2x PLL, FRO144M, FRO12M, OSC48M, OSC32K, FRO16K FRO192, FRO12M, OSC48M, FRO16K - OSC48M min. frequency is reduced to 8MHz. Communications USB FS, 10x LP_FLEXCOMM,  2x FlexCAN, 2x SAI, 2x I3C, FlexIO, 2x EMVSIM USB FS, 2x LPSPI, 3x LPUART, LPI2C, I3C - LPSPI/LPUART/LPI2C are compatible with LP_FLEXCOMM. FIFO depth in MCXA is 4, and MCXN is 8. - I3C is new version in MCXA. It is compatible with MCXN - USB FS doesn’t support USB DCD in MCXA. High Speed Interface USB HS, FlexSPI, SDHC, ENET, eSPI, SPI Filter LPSPI (LP_FlexCOMM) LPSPI   Timers 2x FlexPWM, 2x QDC, 5x Ctimer, SCT, uTimer, OS Timer, RTC, 2x LPTMR, MRT 1x FlexPWM, 1x QDC, 3x Ctimer, SCT, uTimer, OS Timer, Wakeup Timer,  LPTMR - FlexPWM and Ctimer support up to 192MHz clock - 3 Sub Modules in FlexPWM of MCXA - QDC is a new design, but compatible with MCXN Analog 2x 16bit ADC, 3x DAC, 3x CMP, 3x OPAMP, VREF, TSI 1x 12bit ADC, 2x CMP - The ADC MCXA is single ended ADC, with single sample/hold circuit. Supports up to 4Msps in 12bit mode. Regulators DCDC, SYS_LDO, CORE_LDO, VBAT, SRAM_LDO OD/SD/MD RUN Mode CORE_LDO, SRAM_RET_LDO   Power Mode RUN Mode: OD/SD/MD LP Mode: Sleep/DS/PD/DPD/VBAT RUN Mode: SD/MD LP Mode: Sleep/DS/PD/DPD   IO 6 rails, 124 GPIO, 100M/50M/25M IO 2 rails, ~52 GPIO, 50M/25M IO High Drive IO, 5V Tolerant IO   NEW MODIFIED       New and modified features are highlighted. And as it can be seen, most of the features of the MCX A are compatible with the MCX N.   4.    MCXA SoC Power domain configuration   The following figure introduce in a simplified way the Power Architecture block diagram of the MCX A. Where it can be seen that consist in three power supplies (VDD, VDD_ANA and VDD_USB) to power system and peripherals.   Figure 3. Power Architecture   VDD is the main supply which powers SYSTEM Domain, PMC, LDO_CORE and IO. At the same time CORE_MAIN Domain is supplied by LDO_CORE. VDD_ANA supplies ADC. And VDD_USB supplies USB FS PHY. Power Architecture has the following features: Run Mode SD mode with 1.1V VDD_CORE, 96MHz max. MD mode with 1.0V VDD_CORE, 48MHz max. Low Power Mode Sleep Mode DS Mode PD Mode CORE_MAIN domain and RAM are retained in different voltage DPD Mode. CMC and SPC control the LP mode, which is compatible with MCX N RAM Retention 3 RAM retention groups, which can be retained independently RAM X0 and RAM X1 RAM A0 RAM A1 All RAM can be retained down to DPD mode RAM retention control logic is implemented in SPC Power Sequence VDD and VDD_ANA must be ramp up same time with same level Voltage Monitors POR on VDD LVD and HVD on VDD LVD on VDD_CORE VDD_USB detector The following figure shows the Power Mode Transition block diagram. After POR the chip enters in Reset, when it exits from Reset the chip enters Active Mode. By performing Active Mode, it is able to enter all Low Power Modes. In Sleep and Deep Sleep Modes, it is possible to return directly to Active Mode. Meanwhile, to exit from Deep Power Down Mode, a Reset must be performed. Figure 4. Power Modes Transition   5.    Clock Tree   The following Figure shows a high level of Clock Architecture block diagram. In the left of the block diagram there are the on-chip clock sources, meanwhile in the right there is the distribution of the clock signals that clocking the systems and peripherals of the chip. The SCG controls FRO192M, FRO12M and SOSC clock sources. VBAT implements the 16 kHz internal clock source. And the MRCC provides on-chip modules their own dedicated MRCC bits for clock gating, reset control and configuration options. Figure 5. Clock Architecture The Clock Architecture has the following features: Clock Source FRO192M. Outputs 192/96/48MHz FRO12M. Outputs 12MHz and 1MHz. SOSC. Supports 8~50MHz FRO16K. Output 16.384KHz Clock Management Overall clock architecture is same with MCXN SCG and VBAT control clock generators MRCC in SYSCON controls clock mux and clock divider of the system and peripherals.   6.    Life Cycle and ROP State The following Table summarizes the Life Cycle State model and the Read Out Protection (ROP), which are designed to protect customer code and data from reading from the device internal flash. There are different levels of protection in the system, so that access to the on-chip flash and use of ISP can be restricted. Also, the life cycle state of the device determines the debug access and ISP command availability. Table 2. Life Cycle and ROP Life Cycle State ROP State Debug Port Status Debug Mail Box Command ISP Command NXP_PROVISIONED OEM_OPEN OEM_FIELD_RETURN NXP_FIELD_RETURN ROP0  ROP_STATE = 0xFFFF_FFFF  ROP_STATE_DP = 0xFFFF_FFFF - Disabled by default - Enabled by Bootloader Full command OEM_CLOSED ROP1    ROP_STATE = 0x0000_0003    ROP_STATE_DP = 0x0000_0003 - Disabled by default - Not enabled by Bootloader - Debug configure register is not locked Reduced command ROP2    ROP_STATE = 0x0000_0001    ROP_STATE_DP = 0x0000_0001 - Disabled by default - Not enabled by Bootloader - Debug configure register is locked Reduced command OEM_NO_RETURN ROP3    ROP_STATE = 0x0000_0000    ROP_STATE_DP = 0x0000_0000 - Disabled by default - Not enabled by Bootloader - Debug configure register is locked No command BRICKED Other value - Disabled by default - Not enabled by Bootloader - Debug configure register is locked No command   NXP_BLANK and NXP_FAB are NXP states that are not available for customers. NXP_PROVISIONED, OEM_OPEN, OEM_FIELD_RETURN and NXP_FIELD_RETURN are initial customer development states after leaving NXP manufacturing. OEM_CLOSED is the customer in-field application state, with ROP protection. OEM_NO_RETURN is the customer in-field application state, with ROP protection which prevents use of field return. And finally, BRICKED is the end-of-life state to prevent device use.   7.    Closing remarks   The MCX A series is based on the Arm Cortex-M33 operating at up to 96 MHz. It is scalable and easily migrated between N and A series given that peripherals and memories are very similar. The main on-chip memories are a Non-Volatile Flash memory with ECC and a RAM with ECC and Self-Test. Enhanced peripherals are designed with specific use cases in mind. This gives the applications a lot of focus on what they need. Improved Read Out Protection is built into the hardware designed to protect customer code and data from unauthorized readings. This device provide great flexibility and multiple options for the user to achieve low-power consumption with memory retention. Comprehensive serial communications included in the MCX A allow to interact with various components in customer applications. The analog integration selection within the MCX A also provides real-time response to the outside world, including ADC, CMP and temperature sensor. Utilize MCUXpresso software and tools to optimize, ease and help accelerate your embedded system development with a development suite that includes device configuration tools, drivers and middleware, multiple IDEs and a secure provisioning tool.

Device manufacturers spend months or years developing application software for their end products, which is one of the most valuable assets.   During the software development phase, the engineering teams use development platforms with easy access to critical electronics development components, but this is no longer the case when the projects move to the manufacturing phase. Once the project is ready to go to manufacturing the exposure of the electronics components changes drastically from a development environment. In Most cases the programming connector is not accessible because PCB now resides inside an assembled enclosure or has been removed to reduce PCB cost or very important, for security reasons. On Any case you still need to download manufacture testing FW or final product firmware to the microcontrollers in the system and to help with that NXP MCX microcontrollers have embedded tools called the In-system programming to assist with the FW provisioning. In-System programming (ISP) is a method of erasing and programing the on-chip FLASH or RAM memory using a ROM bootloader firmware without using an external Debug tool. NXP MCX Microcontroller family have ISP support over several serial peripherals like: UART SPI I2C USB High-Speed USB Full-Speed CAN Depending on the MCX microcontroller you are using the ISP supported peripherals will change so it is important to review the “In-system Programming” reference manual chapter on the specific MCX microcontroller that will be used. One important thing to remark is that the ISP firmware resides inside a ROM section on the MCX microcontrollers, meaning that the entire flash of the device can be used for the main application without the need of reserving on-chip FLASH for a firmware provisioning bootloader. The flash bootloader code is executed automatically every time the part is powered on or reset. The bootloader can execute the ISP command handler or pass execution to the user application code depending on several conditions. When the internal flash in empty the MCX microcontroller automatically enters ISP mode. Translating this to the manufacturing, Microcontrollers are ready to get firmware using ISP after the PCB assembly process. In-circuit programming features can be tested using any FRDM or EVK boards available for MCX family. You can find instructions of how to use the ISP mode alongside many other MCX examples, demos and tools directly on NXP Application Code Hub   Here are some Application Code Hub for ISP on MCX FRDM boards: How to use In-System Programming (ISP) on FRDM-MCXN947 How to use In-System Programming (ISP) on FRDM-MCXA153   Security is at the core of NXP. Not only do we want each element of our devices or software to be safe and secure, but it is just as critical that we enable the manufacturing of each customer's product to be secure. Manufacturing processes should be worry-free and hassle-free with the backing of highly secure technology, even if the manufacturing site itself cannot provide strong assurances of security. NXP is offers a variety of features that enable OEMs to protect their IP and revenue. Utilizing our MCUXpresso Secure Provisioning tool (SEC) and Secure Provisioning SDK (SPSDK)   MCXpresso Secure Provisioning tool (SEC) The MCUXpresso Secure Provisioning tool (SEC) is a GUI-based application that provides firmware provisioning operations such as setting up e-fuses/OTP, building secure boot image, flash programming, keys generation, trust provisioning, etc.   NXP SEC tool features: Easy-to-use configuration of secure provisioning project settings Enables direct communication with attached device for provisioning and programming. Supports generation of executable scripts for production use Manufacturing mode for simplified production line use     Secure Provisioning SDK (SPSDK) Secure Provisioning SDK (SPSDK) is an open-source development kit with its source code released on Github and PyPI. It contains a set of API modules for custom production tool development which requires more advanced secure provisioning flow. SPSDK enables connection and communication with NXP’s microcontrollers for the following purposes:   Generation of Secure Binary (SB) bootable images Security features configuration (CMPA, CFPA, Trustzone, secure bootloader, debug authentication, etc.) Generation and management of cryptographic keys and certificates Trust provisioning and secure programming through MCU Bootloader Debug authentication through J-Link, PEmicro and PyOCD debug probes   For more information about NXP development ecosystem for microcontrollers please visit: MCUXpresso Suite of Software and Tools https://nxp.com/mcuxpresso  

FRDM-MCXA153 FRDM-MCXN947    Hardware & Software To do this, surely you have to download the next software. MCU Link JTAG/SWD Debug Probe | NXP Semiconductors MCUXpresso IDE for NXP MCUs | Linux, Windows and MacOS | NXP Semiconductors | NXP Semiconductors About the hardware. FRDM-MCXN947 FRDM-MCXA153 MCU Link Firmware update. We will need the firmware to update the LPC55s69 on the board, the MCU Link firmware version 2.263 is compatible with the MCX. You may need the EVK connected to the computer under DFU mode, in the schematic of the EVK does not mention the DFU but has the named jumper of ISP [JP21] MCX - N or [JP8] MCX - A, sure you put the LPC55s69 in ISP, not the MCX, review the schematic below. MCX - N MCX - A When you have installed this version on your computer, go to the locations. ROOT: C:\nxp\MCU-LINK_installer_2.263\scripts Then open the CMD prompt console and run the script for CMSIS. The console asks if you have the appropriate jumper, if yes click enter again. If everything is right the message successfully will appear. Then in the MCUXpresso, you can see the debugger probe. Happy Debugging.