1. Overview The MCXN947 chip is a highly integrated microcontroller featuring robust processing capabilities, extensive peripheral support, and advanced security features. It is suitable for a wide range of complex applications. The NXP FRDM-MCXN947 board is a low-cost design and evaluation board based on the MCXN947 device. NXP provides a comprehensive set of tools and software support for the MCXN947, including hardware evaluation boards, an integrated development environment (IDE), example applications, and drivers. Micro-ROS is an embedded version of ROS 2 specifically designed to operate on embedded systems, enabling real-time control and communication for robotics and embedded devices. It extends the powerful features of ROS 2 to resource-constrained embedded platforms like microcontrollers and embedded systems. The introduction of Micro-ROS facilitates tighter integration between embedded systems and the ROS 2 ecosystem, enabling advanced robotic automation and control. This document explores the process of porting Micro-ROS to the MCXN947 board.‌   This document explores the process of porting Micro-ROS to the MCXN947 board. Hardware Environment：     FRDM-MCXN947 Software Environment:     Ubuntu 22.04     IDE：MCUXpresso IDE v11.9.0     SDK：SDK Builder | MCUXpresso SDK Builder (nxp.com) 2. ROS 2 Architecture Before delving into the Micro-ROS porting process, let us briefly introduce the new ROS 2 architecture. This is necessary because Micro-ROS heavily leverages ROS 2's abstraction layer source code in its design and implementation. Compared to its predecessor ROS 1, ROS 2 employs a distinct communication mechanism, most notably adopting the DDS (Data Distribution Service) protocol for communication and node discovery. ROS 1, by contrast, relies on the XML-RPC protocol and requires the master node to launch before other nodes can join. ROS 1's limited support for embedded devices stems from the XML-RPC mechanism, which introduces significant software dependencies in these environments. To address this issue, projects like rosserial developed lightweight communication protocols tailored for MCU-to-PC master node communication. ROS 2, on the other hand, integrates the industry-proven DDS protocol, which has demonstrated its stability in domains like military, aerospace, and financial systems. It is important to note that DDS is a standard protocol with various implementations, such as Cyclone DDS (Eclipse), Fast DDS, and Micro XRCE-DDS (eProsima). To ensure that upper-layer ROS 2 code remains unaffected by different DDS implementations, ROS 2 defines a series of abstract layer interfaces, such as RCL (ROS Client Library) and RMW (ROS Middleware). These DDS implementations provide a uniform RMW interface. On top of RMW is the RCL, implemented in C, which supports various programming languages, including C++, Python, and Java. Thus, successfully porting ROS 2 to a real-time operating system (RTOS) hinges on the RTOS supporting a specific DDS implementation and its corresponding RMW interface. Only then can upper-layer RCL and ROS application code run without modification. ROS 2 comprises RCL (ROS Client Library), RMW (ROS Middleware Interface), and DDS (Data Distribution Service). Porting ROS 2 to a new platform essentially involves creating a compatible RMW-DDS combination, leaving the RCL layer unaltered. Micro-ROS provides such an RMW-DDS combination. Specifically, Micro-ROS employs Micro XRCE-DDS (a DDS standard designed for extremely resource-constrained environments) with a corresponding RMW implementation. This enables Micro-ROS to be compatible with ROS 2's architecture while efficiently running on resource-limited embedded devices. Thus, porting Micro-ROS to different hardware platforms fundamentally involves interfacing communication protocols like UART (Universal Asynchronous Receiver-Transmitter) and UDP (User Datagram Protocol) with the Micro-ROS RMW-DDS combination. This process ensures effective communication between Micro-ROS and other nodes or external systems while maintaining the lightweight and efficient characteristics suitable for embedded devices. From the above introduction, we can see that MicroROS transplantation mainly has two parts: Connect UART/UDP communication and clock to implement the 5 functions in default_transport.cpp. Folder DDS+RMW+RCL generates libmicroros.a static library. 3. Micro-ROS Static Library Toolchain and Environment Configuration 3.1 Micro-ROS Static Library Toolchain and Environment Configuration First, install ROS 2 on Ubuntu 22.04 LTS and run the following commands: sudo apt update&&sudo apt install locales sudo locale-gen en_US en_US.UTF-8 sudo update-locale LC_ALL=en_US.UTF-8 LANG=en_US.UTF-8 export LANG=en_US.UTF-8 sudo apt update && sudo apt install curl gnupg lsb-release sudo curl -sSL https://raw.githubusercontent.com/ros/rosdistro/master/ros.key -o /usr/share/keyrings/ros-archive-keyring.gpg (1) sudo apt update: Updates the system’s package list to fetch the latest package information. (2) sudo apt install locales: Installs the locales package, which provides tools for managing and configuring localization. (3) sudo locale-gen en_US en_US.UTF-8: Generates the localization settings for US English, including UTF-8 encoding. (4) sudo update-locale LC_ALL=en_US.UTF-8 LANG=en_US.UTF-8: Updates the system’s localization settings to use UTF-8 encoding for US English. (5) export LANG=en_US.UTF-8: Sets the current terminal’s language encoding to US English UTF-8. (6) sudo apt install curl gnupg lsb-release: Installs additional tools (curl for network requests, gnupg for encryption, lsb-release for distribution information). (7) sudo curl: Downloads the ROS public key for verifying package integrity.   3.2 Installing ROS on Ubuntu Set up and build the Micro-ROS development environment with the following commands: sudo apt update && sudo apt upgrade && sudo apt install ros-humble-desktop source /opt/ros/humble/setup.bash && echo “source /opt/ros/humble/setup.bash” >>~/.bashrc source /opt/ros/$ROS_DISTRO/setup.bash mkdir uros_ws && cd uros_ws git clone -b iron https://github.com/micro-ROS/micro_ros_setup.git src/micro_ros_setup rosdep update && rosdep install --from-paths src --ignore-src -y colcon build source install/local_setup.bash ros2 run micro_ros_setup create_firmware_ws.sh generate_lib (1) Update the software and install ROS (Robot Operating System) (2) Set and save the configuration of the ROS environment. (3) These two commands create a new directory uros_ws (workspace), and then switch to this directory. (4) Clone the project named micro_ros_setup from the GitHub repository and place it in the src directory of the workspace. (5) These two commands are used to install the dependencies required by the project. (6) This command uses the colcon build system to compile and install the project. Colcon is a general-purpose build tool suitable for multiple programming languages and platforms. (7) create_firmware_ws.sh: This is the name of the executable file to be run. It might be a script that creates a firmware workspace. The purpose of this command is to run the create_firmware_ws.sh script in the micro_ros_setup package and pass the parameter generate_lib to generate a firmware workspace containing the Micro-ROS library. This step requires downloading a large amount of source code from github. After failure, the next generation will prompt that the firmware already exists and you need to rm this folder. If the following picture appears, it proves that the code download is successful. 4. Generating the Micro-ROS Static Library If the toolchain and environment setup are successful, you should have five folders in your workspace: build, firmware, install, log, and src. The firmware folder contains the Micro-ROS workspace. 4.1 Configure the toolchain.cmake file according to the target processor Enter the fireware directory. The colcon.meta and toolchain.cmake inside are the configuration files we need to specify to generate the static library. Colcon.meta describes the configuration of our micro-ros, and toolchain.cmake describes the microcontroller platform. We can open MCUXpresso to find MCXN947 related configuration. and create toolchain.cmake. set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_CROSSCOMPILING 1) set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) # SET HERE THE PATH TO YOUR C99 AND C++ COMPILERS set(PIX /opt/gcc-arm-none-eabi-10.3-2021.10/bin) set(CMAKE_C_COMPILER ${PIX}/arm-none-eabi-gcc) set(CMAKE_CXX_COMPILER ${PIX}/arm-none-eabi-g++) set(CMAKE_C_COMPILER_WORKS 1 CACHE INTERNAL "") set(CMAKE_CXX_COMPILER_WORKS 1 CACHE INTERNAL "") # SET HERE YOUR BUILDING FLAGS set(FLAGS "-O2 -ffunction-sections -fdata-sections -fno-exceptions -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -nostdlib -mthumb --param max-inline-insns-single=500 -D'RCUTILS_LOG_MIN_SEVERITY=RCUTILS_LOG_MIN_SEVERITY_NONE'" CACHE STRING "" FORCE) set(CMAKE_C_FLAGS_INIT "-std=c11 ${FLAGS} -DCLOCK_MONOTONIC=0 -D'__attribute__(x)='" CACHE STRING "" FORCE) set(CMAKE_CXX_FLAGS_INIT "-std=c++11 ${FLAGS} -fno-rtti -DCLOCK_MONOTONIC=0 -D'__attribute__(x)='" CACHE STRING "" FORCE) set(__BIG_ENDIAN__ 0) The above is how cmake is written. Among them, "-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard": These options specify the architecture and floating point unit characteristics of the target processor. We can view the architecture and floating point unit characteristics of the MCXN947's target processor. We can open MCUXpresso IDE, open a MCXN947 project, and check mcpu=cortex-m33 -mfpu=fpv5-sp-d16 mfloat-abi=hard in All options in settings->MCU Linker. Therefore, the MCXN947 series is an M33 core. We need to change -mcpu=cortex-m7 to -mcpu=cortex-m33, and basically no other changes are needed. From this we can also see that a series of static libraries produced should be universal! 4.2 Configure the colcon.meta file according to Micro-ROS requirements The other file created sets the Micro-ROS library configurations. To set the transport layer type, here we want a custom transport layer, the configuration “-DUCLIENT_PROFILE_CUSTOM_TRANSPORT=ON” is set to “ON” and the configuration “-DRMW_UXRCE_TRANSPORT=custom” is set to “custom”. The other interesting settings are under the “rmw_microxrcedds” section. Here we can set the maximum number of nodes (1), publisher (5), subscribers (5), services (1) and clients (1) that should be supported, as well as the maximum message history (4) used for a reliable QoC mode. A more detailed description of all settings under this section, can be found in the eProsima Micro XRCE-DDS GitHub. An example configuration, the one I used, is shown bellow: touch colcon.meta { "names": { "tracetools": { "cmake-args": [ "-DTRACETOOLS_DISABLED=ON", "-DTRACETOOLS_STATUS_CHECKING_TOOL=OFF" ] }, "rosidl_typesupport": { "cmake-args": [ "-DROSIDL_TYPESUPPORT_SINGLE_TYPESUPPORT=ON" ] }, "rcl": { "cmake-args": [ "-DBUILD_TESTING=OFF", "-DRCL_COMMAND_LINE_ENABLED=OFF", "-DRCL_LOGGING_ENABLED=OFF" ] }, "rcutils": { "cmake-args": [ "-DENABLE_TESTING=OFF", "-DRCUTILS_NO_FILESYSTEM=ON", "-DRCUTILS_NO_THREAD_SUPPORT=ON", "-DRCUTILS_NO_64_ATOMIC=ON", "-DRCUTILS_AVOID_DYNAMIC_ALLOCATION=ON" ] }, "microxrcedds_client": { "cmake-args": [ "-DUCLIENT_PIC=OFF", "-DUCLIENT_PROFILE_UDP=OFF", "-DUCLIENT_PROFILE_TCP=OFF", "-DUCLIENT_PROFILE_DISCOVERY=OFF", "-DUCLIENT_PROFILE_SERIAL=OFF", "-UCLIENT_PROFILE_STREAM_FRAMING=ON", "-DUCLIENT_PROFILE_CUSTOM_TRANSPORT=ON", "-DUCLIENT_PROFILE_SHARED_MEMORY=ON", "-DUCLIENT_SHARED_MEMORY_MAX_ENTITIES=20" ] }, "rmw_microxrcedds": { "cmake-args": [ "-DRMW_UXRCE_MAX_NODES=5", "-DRMW_UXRCE_MAX_PUBLISHERS=6", "-DRMW_UXRCE_MAX_SUBSCRIPTIONS=4", "-DRMW_UXRCE_MAX_SERVICES=6", "-DRMW_UXRCE_MAX_CLIENTS=1", "-DRMW_UXRCE_MAX_HISTORY=4", "-DRMW_UXRCE_TRANSPORT=custom" ] } } } 4.3 Building the Micro-ROS Static Library Run the following commands: source install/local_setup.bash ros2 run micro_ros_setup build_firmware.sh $(pwd)/firmware/toolchain.cmake $(pwd)/firmware/colcon.meta If the static library is successfully generated, you will see libmicroros.a in the firmware/build file. 5. Integrating and Testing the Static Library Locally 5.1 Adding the Generated Micro-ros Static Library to the Local Project   (1) Create a folder named bsp_include. (2) Add all files from the include directory into your project under bsp_include. (3) Add all paths in the include file to the include path. (4) Add the generated libmicroros.a static library to the project, for example, add it to bsp_include.   (5) Add the libmicrorots.a static library and name path to Libraries(-l) and Library search path(-L). 5.2  Implementing the Serial Communication Interface Functions To port Micro-ROS to an MCU, you must provide transport layer functionalities for reading and writing through the communication interface. The required transport functions are defined as follows: rmw_ret_t rmw_uros_set_custom_transport( bool framing, void * args, open_custom_func open_cb, close_custom_func close_cb, write_custom_func write_cb, read_custom_func read_cb); ​ Through this structure, we can see that the communication interface function group mainly includes open, close, write, and read. open: This function is responsible for initializing (opening) peripheral devices used by the transport layer. This function is empty if the peripheral is initialized elsewhere and before the Micro-ROS function is called. close: This function is responsible for deinitializing (turning off) peripherals used by the transport layer. Because there is no need to deinitialize the function. This function is also empty. write: This function is responsible for writing data (bytes) on the peripheral device. The number of bytes to be written and the bytes themselves are given as parameters "len" and "buf" respectively. read: This function is responsible for reading data (bytes) from the peripheral device. The number of bytes to read is specified in the function parameter "len" and bytes should be returned via the function parameter "buf". bool transport_close(struct uxrCustomTransport * transport) { return true; } bool transport_open(struct uxrCustomTransport * transport) { return true; } size_t transport_write(struct uxrCustomTransport* transport, const uint8_t * buf, size_t len, uint8_t * err) { LPUART_WriteBlocking(DEMO_LPUART, buf, len); return len; } size_t transport_read(struct uxrCustomTransport* transport, uint8_t* buf, size_t len, int timeout, uint8_t* err) { LPUART_ReadBlocking(DEMO_LPUART, buf, len); return len; } Additionally, you need to implement a function to provide the system’s clock time. This clock does not have to provide real-time or world time, but rather elapsed time since startup or similar. For example: int clock_gettime(clock_t unused, struct timespec *tp) { (void)unused; IRTC_GetDatetime(RTC, &datetimeGet); tp->tv_sec = datetimeGet.second; tp->tv_nsec = (long)(datetimeGet.second) * 1000000; return 0; } 5.3 Testing To run Micro-ROS in practice, the setup includes two components: 1. A client running on the MCU. 2. An agent running on the host PC. Basic Micro-ROS Client (MCU) Below are the minimal steps and code needed to create and run a Micro-ROS client. These instructions are based on the Micro-ROS documentation for node creation. //Required global variables rcl_allocator_t allocator; rclc_support_t support; rcl_node_t node; rclc_executor_t executor; rmw_ret_t error; //Set Communication functions rmw_uros_set_custom_transport( true, NULL, rtt_transport_open, rtt_transport_close, rtt_transport_write, rtt_transport_read ); //Set Allocation functions (Optional) rcl_allocator_t allocator = rcutils_get_zero_initialized_allocator(); allocator.allocate = rtt_allocate; allocator.deallocate = rtt_deallocate; allocator.reallocate = rtt_reallocate; allocator.zero_allocate = rtt_zero_allocate; (void)!rcutils_set_default_allocator(&allocator); //Get allocator allocator = rcl_get_default_allocator(); //Create init_options error = rclc_support_init(&support, 0, NULL, &allocator); //Create node error = rclc_node_init_default(&node, "uROS_Terminal", "", &support); //Create executor error = rclc_executor_init(&executor, &support.context, 1, &allocator); //Call the executor periodically e.g. in the while(1) loop or a thread: while(1) { error = rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)); } ​ Setting up the Micro-ROS Agent (PC) The agent establishes an interface between the Micro-ROS client on the MCU and ROS 2 on the host PC. To set up the agent: # Go to the Micro-ROS workspace folder cd microros_ws # Source ROS 2 source /opt/ros/humble/setup.bash # Source local packages source install/local_setup.bash # Create Agent ros2 run micro_ros_setup create_agent_ws.sh # Build Agent ros2 run micro_ros_setup build_agent.sh # Possible ROS Update sudo rosdep init rosdep update  After successfully building the Micro ROS agent, the following bash command starts/runs the agent: # Go to the Micro-ROS workspace folder cd microros_ws # Source ROS 2 source /opt/ros/humble/setup.bash # Source local packages source install/local_setup.bash # Run Agent (serial connection) ros2 run micro_ros_agent micro_ros_agent serial --dev /dev/ttyACM0 Of these bash commands, the last one is the one that actually starts the Micro-ROS agent. It takes several parameters, the first is the type of connection to use, in this case a serial connection. Then there are two parameters that only apply to serial connections: "--dev/ttyACM0", which sets the serial interface to be used (to list all serial interfaces in linux, you can use the following bash command: "dmesg | grep tty".) After starting the Micro-ROS agent, the MCU can connect to the host PC via the serial interface and reset to establish a new connection. If the following Micro-ROS agent terminal output: This proves the success of transplanting Micro-Ros On Frdm-mcxm947.

MCUXN947 Security Configuration (Secure Boot + Lifecycle)   1. Introduction This application note aims to guide developers on configuring Secure Boot and Lifecycle on the MCXN947 microcontroller. The goal is to ensure security during mass production, prevent code theft and tampering, and allow for secure firmware updates. By following this document, developers can better understand and implement best practices for secure boot and firmware updates. 2. Implementation Overview 2.1 Secure Boot (SB) Introduction The Secure Binary (SB) container brings secure and easy way to upload or update firmware in embedded device during either the manufacturing process or end-customer's device lifecycle. An SB file is a command-based firmware update image. The SB file can be considered a script (commands and data), with the ROM acting as the interpreter. The ROM supports version 3.1 of the SB image format. The SB container in version 3.1 (SB3.1) uses the latest cryptographic algorithms to ensure the authenticity and confidentiality of the carried firmware. The boot time and security level, which fit the best for the required use case, control the various available security configurations. The digital signature based on Elliptic Curve Cryptography (ECC) ensures the authenticity of the SB3.1 container. The use of the Advanced Encryption Standard (AES) in Cipher Block Chaining (CBC) mode ensures the confidentiality of the SB3.1 container. 2.2 Lifecycle Introduction The lifecycle state of a chip reflects its actual state and is used to guide how the chip protects its hosted assets at specific times. For example, when a project is completed, during mass production, or when the device is in use by the end customer, the chip's access permissions are much more restricted compared to the development stage. The MCXN947 microcontroller supports multiple secure lifecycle states. For detailed information, refer to the "Lifecycle States" chapter in the MCX Nx4x Security Reference Manual. Note that the lifecycle state is monotonic, meaning it can only increase, and access permissions become more restrictive. This document focuses on field configuration (In-field) to ensure security after deployment. 2.3 MCUXpresso Tool Introduction The MCUXpresso Security Configuration Tool is a GUI-based application that simplifies the generation and configuration of bootable executable files on NXP MCUs. This tool can be used to generate SB3.1 files and deploy MCU security configurations. 3. Implementation Steps 3.1 Preparation Software Two image files: frdmmcxn947_led_blinky_red.s19 and frdmmcxn947_led_blinky_green.s19 MCUXpresso Secure Provisioning Tool v9.0 (SPT Tool) Blhost Hardware FRDM-MCXN947 Development Board 2 USB Type-C Cables Computer 3.2 Steps 3.2.1 Restore MCU to Default Configuration Power on MCU with ISP Mode Hold the ISP key and power on the MCU (POR). This document uses the ISP-USB interface, so connect the USB cable to J11 (HS-USB) port. Configure CMPA and CFPA to Default State Open the SPT Tool, create a new workspace, and select the corresponding chip. Configure as follows:   Program CMPA and CFPA OK -> Build image, Write image, to burn the configured default CMPA and CFPA into the MCU. Erase Entire Flash Connect the board's debugging interface MCU-link via USB. Select the debug probe in the SPT Tool. After a successful connection, use Erase to erase the entire flash. The chip is restored to its default state with no enabled security configurations. 3.2.2 Configure Secure Boot and Lifecycle for Field Mode (In-field)  Generate Secure Boot Keys Select the PKI management interface -> Generate Keys... -> Generate   Configure Image File Open the "Build image" interface and configure as follows: Boot: Select Encrypted (PRINCE/IPED) and signed Source executable image: Select the application image file frdmmcxn947_led_blinky_green.s19 Start address: 0x00000000 Firmware version: 1 Authentication key: Choose any one of the 4 options CUST_MK_SK: Click Random to generate a random number OEM seed: Click Random to generate a random number   Configure CMPA and CFPA Open CMPA and CFPA, and configure to enable security: Generate Configuration Files and Image File After configuration, build the image to generate CMPA, CFPA configuration files, and the SB3-formatted image file.   3.2.3 Program Application Program Configuration Files and Image File Open the "Write image" window, click "Write image" to program the configuration files and the SB image file.   Verify Application Power on the board again, and you should see the green LED flashing, indicating that the application is running normally. Then, hold the ISP key and perform a software reset of the board (note that this must be a software reset for the CFPA lifecycle configuration to take effect; a power-on reset will not activate the CFPA configuration). If the development is complete and in the production stage, and OTP is used to manage the lifecycle, any reset will detect the OTP configuration. At this point, secure boot is enabled, and the lifecycle is configured for field mode. Therefore, the chip no longer supports SWD interface debugging or reading flash content via ISP. To update the flash program, only a valid SB3 file can be burned. 3.2.4 Update Application Create a New SB3 File Compile the SDK example frdmmcxn947_led_blinky to generate a .bin file or s19 file. For all supported formats by the SPT tool, refer to the SPT manual. Here, use the s19 file format frdmmcxn947_led_blinky_red.s19. Open the SPT tool and use the workspace created for the first application image file. This will import the necessary keys directly. Then, import frdmmcxn947_led_blinky_red.s19. The Image firmware version should be greater than 0. Since we have not configured Set minimal firmware version, the minimum version is 0. This involves the anti-rollback feature, which will be explained in detail later. After configuration, hold the ISP key and power on the board to restart. Then, build the image to generate frdmmcxn947_led_blinky_red.sb. Program the New SB3 File Use the blhost receive-sb-file command to burn the file: blhost.exe -u 0x1fc9 0x014f receive-sb-file frdmmcxn947_led_blinky_red.sb After burning, restart the MCU. The red LED flashing indicates that the firmware update was successful. 3.2.5 Verify Security Features After enabling secure boot and configuring the lifecycle for field mode, the MCU cannot read the flash via SWD or ISP, ensuring the security of the customer's code against theft and tampering. To test if the configuration is successful, you can use the SWD and ISP interfaces. You should find that the SWD interface cannot connect, and while the ISP interface can connect, it cannot read or write. Note that before testing, you need to hold the ISP key and perform a software reset (not a power-on reset).     4. Notes By following this document, developers can learn how to configure and manage the security lifecycle on the MCXN947 microcontroller, ensuring the security and reliability of the device at different stages. Following the steps in this document can effectively achieve secure boot and operation, as well as firmware updates.  

In most cases, C project is generated and used. But assembly project has it’s own advantage, with assembly project, you can program with assembly language directly, can test assembly instruction with assembly mnemonic. Generally, C language is inefficient, so in order to test the performance of the core, or get peripheral highest performance, the assembly project is required. The doc discusses the procedure to create an assembly language project, in the end, gives an example to toggle a LED, which demos how to initialize the NVIC, CTimer, GPIO with assembly language. It also gives the example of subroutine.   1. The procedure to create an assembly language project based on MCUXPresso tools 1.1 Load MCUXPresso tools and drag SDK to the Installed SDK menu Then click “Create a new C/C++ project”   1.2 Select the board or processor, then clock “Next” software button   1.3 Name the project and Select the driver. In the menu, it is okay to use default configuration, then clock “Finish”   1.4 A New project called MCXN947_project is created with C language   1.5 Delete the MCXN947_project.c and add the main.s Click the “source” group with right mouse button, the click “New”->”source File”   1.6 Add the main.s as the following Fig and click “Finish”   1.7 The final project is like:   2.0 writing the assembly code in the main.s This is the code in main.s /* This assembly file uses GNU syntax */ .equ SYSCON_ANGCLKCTRLSET0,0x40000220 .equ SYSCON_AHBCLKCTRLSET1,0x40000224 .equ SYSCON_AHBCLKCTRLSET2,0x40000228 .equ SYSCON_CTIMER4CLKSEL, 0x4000027C .equ SYSCON_CTIMER4CLKDIV, 0x400003E0   /*PIO3_4 LED blue*/ .equ PORT3_PCR_BASE,0x40119000 .equ PORT3_PCR4,PORT3_PCR_BASE+0x90   .equ GPIO3_BASE,0x4009C000 .equ GPIO3_PDDR,GPIO3_BASE+0x54 .equ GPIO3_PDOR,GPIO3_BASE+0x40     /*PIT configuration*/ .equ CTIMER4_BASE,0x40010000 .equ CTIMER4_IR,CTIMER4_BASE+0x00 .equ CTIMER4_TCR,CTIMER4_BASE+0x04 .equ CTIMER4_MCR,CTIMER4_BASE+0x14 .equ CTIMER4_MR0,CTIMER4_BASE+0x18 .equ CTIMER4_MSR0,CTIMER4_BASE+0x78 .equ CTIMER4_PWMC,CTIMER4_BASE+0x74     /*NVIC configuration*/ /*refer to 4.2 Nested Vectored Interrupt Controller in Cortex-M4 Generic User's Guide.pdf*/ .equ NVIC_ISER0,0xE000E100 .equ NVIC_ISER1,0xE000E104   .equ NVIC_ICPR0,0xE000E284 .equ NVIC_ICPR1,0xE000E288   .equ NVIC_IPR12,0xE000E430 .equ NVIC_IPR14,0xE000E438           .global __user_mem_buffer1,__user_mem_buffer2     .text     .section   .rodata     .align  2     .LC0:       .text     .thumb     .align  2     .global main     .global CTIMER0_IRQHandler     .type main function   main:     push {r3, lr}     add r3, sp, #4     nop     BL peripheralInit     nop     nop     nop     nop     NOP     /*cpsie i*/ loop:     b loop     mov r3, #0     mov r0, r3     pop {r3, pc}     /*subroutine 1*/ /* copy 10 words from one place to another*/     .type MyFunc function     .func MyFunc:     push {r0,r1,r2,lr}     MOV R2,#0x00     LDR R0,=USER_MEM_BUFFER1     MOV R1,#0x00 loop1:     NOP     STR R1,[R0]     ADD R1,#0x10     ADD R0,#4     ADD R2,#1     CMP R2,#0x10     BNE loop1     AND R5,R1,R5 ;     ASR R3,R2,#1     ORR R5,R1,R5     ADD R3,R2,R3     ADC R3,R2,R3     AND R2,R1,R2 ; /*#0x0F*/     LDR R0,=0x1234     /*LDR R0, [R1], #4*/     nop     pop {r0,r1,r2,pc}     .endfunc /***************************************/   /*subroutine 2*/     .type peripheralInit function     .func peripheralInit:    //enable CTimer4 gated clock     LDR R0,=0x400000     LDR R1,=SYSCON_AHBCLKCTRLSET2     nop     STR R0, [R1]       MOV R0,#0x03 //select     LDR R1,=SYSCON_CTIMER4CLKSEL     nop     STR R0, [R1]         MOV R0,#0x09 //select     LDR R1,=SYSCON_CTIMER4CLKDIV     nop     STR R0, [R1]     /*setting CTimer0*/       //set Ctimer0_IR     MOV R3,#0x01     LDR R1,=CTIMER4_IR     Nop     LDR R2,[R1]     ORR R2,R2,R3     STR R2,[R1]     //set CTIMER4_MCR     MOV R3,#0x03     LDR R1,=CTIMER4_MCR     LDR R2,[R1]     ORR R2,R2,R3     STR R2,[R1]         LDR R0,=6000000     LDR R1,=CTIMER4_MR0     STR R0,[R1]       LDR R0,=6000000     LDR R1,=CTIMER4_MSR0     STR R0,[R1]         MOV R0,#00     LDR R1,=CTIMER4_PWMC     STR R0,[R1]       nop     nop //lop1: //  b lop1         /*setting interrupt, Ctimer4 IRQ 56*/     LDR R1,=NVIC_ISER1     LDR R0,[R1]     LDR R3,=0x01000000     ORR R0,R0,R3     STR R0,[R1]       LDR R1,=NVIC_ICPR1     LDR R0,[R1]     LDR R3,=0x01000000     ORR R0,R0,R3     STR R0,[R1]       MOV R0,#0x00     LDR R1,=NVIC_IPR14     STR R0,[R1]       /*pin mux setting*/     /*enable PORT3 and GPIO3 gated clock*/     LDR R0,=0x410000     LDR R1,=SYSCON_ANGCLKCTRLSET0     nop     STR R0, [R1]     /*set the GPIO3_4 as GPIO output mode*/     LDR R0,=#0x1000     LDR R1,=PORT3_PCR4     STR R0,[R1]         LDR R1,=GPIO3_PDDR     LDR R0,[R1]     LDR R3,=0x10     ORR R0,R0,R3     STR R0,[R1]       /*CTimer4 start*/     MOV R3,#0x01     LDR R1,=CTIMER4_TCR     LDR R0,[R1]     ORR R0, R0,R3     STR R0,[R1]     nop     nop     nop     /*cpsid i*/     BX LR     .endfunc /*********************************************/   /*subroutine 3*/     .text     .type testcal function     .func testCal:     LDR R0,=0x12345678     MOV R1,#0x0F     AND R0,R1     /*test saturation function*/     LDR R0,=0x8234     LDR R1,=0x8234     /*ADDS R5,R0,R1*/     QADD16 R6,R0,R1  /*saturation heppen, the R6 will become negative minumum 0x8000*/     nop     /***8888888*/       LDR R0,=0x6234     LDR R1,=0x6234     /*ADDS R5,R0,R1*/     SADD16 R6,R0,R1     nop     QADD16 R6,R0,R1 /*saturation heppen, the R6 will become negative minumum 0x7FFF*/     nop     SMUAD R6,R0,R1     BX LR     .endfunc /*********************************************/   /*interrupt service routine*/     .global CTIMER4_IRQHandler     .text     .align 2     .type CTIMER4_IRQHandler function     .func CTIMER4_IRQHandler:         /*clear interrupt*/     push {R0,R1,LR}     nop     nop     nop     LDR R1,=CTIMER4_IR     LDR R0,[R1] /*dummy reading*/     MOV R4,#0x10;     ORR R0,R0,R4     STR R0, [R1]     /*toggle a LED*/     LDR R1,=GPIO3_PDOR     LDR R0,[R1]     LDR R3,=0x10     EOR R0,R0,R3     STR R0,[R1]     NOP     POP {R0,R1,PC}     .endfunc     /******************************************************/ /*interrupt service routine*/     .global SVC_Handler     .text     .align 2     .type SVC_Handler function     .func SVC_Handler:     push {R0,R1,LR}            NOP     POP {R0,R1,PC} /******************************************************/       .align  2 .L3:     .word       .align 4     .section .contantData HELLO_TXT:     .space 0x100 Hello_END:     .ALIGN 4   /*.lcomm */   .lcomm USER_MEM_BUFFER1  0x100   .lcomm USER_MEM_BUFFER2  0x100     .end   3.0 code explanation   In the code, you have to define the main function, after the core has executed the code ResetISR(void), which is defined in startup_mcxn847_cm33_core0.c, it jump to main() function   The example code implement the function to initialize CTimer, GPIO and NVIC, SYSCON module so that the CTImer can generate interrupt, in the ISR of CTimer, a LED is toggled. After you run the code, you can see that the led is toggled. The peripheralInit Subroutine is used to initialize the CTimer, NVIC, GPIO, SYSCON module so that the CTimer can fire an interrupt and toggle a LED.The CTIMER4_IRQHandler is an ISR of CTimer4, which is defined in startup_mcxn847_cm33_core0.   The MyFunc function and testCal  Subroutines are just for testing a specific assembly instruction, and test how to establish and call a subroutines, they do not have a specific target.

Sometimes connecting things requires a lot of cables because the component you need alone doesn't have the correct connector to mount on an evaluation board.   A few weeks ago, we needed to connect this display Adafruit 1.54" 240x240 Wide Angle TFT LCD Display to some FRDM boards. We started using cables but ended up making a small card to mount the board and plug it directly into the PMOD port of the FRDM board.   We decided to make it available in case you have the same problem 😊   Adafruit 1.54" 240x240 Wide Angle TFT LCD Display PMOD Adapter Gerber files for fabrication are here Final Assembly   3D render     This is how it looks connected to a FRDM-RW612 board  enjoy!    

1. Overview The MCX N947 chip is a highly integrated microcontroller with robust processing capabilities, extensive peripheral support, and advanced security features, making it suitable for various complex applications. One of its critical peripherals is FlexSPI. FlexSPI is an expandable serial peripheral interface mainly used to connect solid-state storage devices such as QuadSPI NOR Flash, QuadSPI NAND Flash, and HyperRAM. FlexSPI is a comprehensive, flexible, high-performance solution that can be configured in different modes to support various storage devices. The NXP FRDM-MCXN947 board is a low-cost design and evaluation board based on the MCXN947 device. NXP provides tools and software support for the MCXN947 device, including hardware evaluation boards, integrated development environment (IDE) software, sample applications, and drivers. By default, the FlexSPI interface on this board connects to an MT35XU512 NOR Flash. In this article, we will explore how to connect HyperRAM to the FlexSPI interface of the MCXN947 board. Hardware environment:   Development Board: FRDM-MCXN947   HyperRAM：W956D8MBYA Software environment:   IDE：MCUXpresso IDE v11.9.0   SDK：SDK Builder | MCUXpresso SDK Builder (nxp.com) 2. HyperRAM Schematic Below is the official eight-line Flash schematic from the FRDM-MCXN947. Since the HyperRAM W956D8MBYA package is a TFBGA 24-Ball 5 x 5 Array, it can be directly replaced. Based on the above schematic, the signal connections for the HyperRAM memory are summarized in Table. HyperRAM Signal Connection Table HyperRAM Chip Pin Function Connected to MCXN947 CS CS Chip Select Signal P3_0/FLEXSPI0_A_SS0_b SCK SCK Clock Signal P3_7/FLEXSPI0_A_SCLK DQS DQS Signal P3_6/FLEXSPI0_A_DQS DQ0 OSPI Data Signal D0 P3_8/FLEXSPI0_A_DATA0 DQ1 OSPI Data Signal D1 P3_9/FLEXSPI0_A_DATA1 DQ2 OSPI Data Signal D2 P3_10/FLEXSPI0_A_DATA2 DQ3 OSPI Data Signal D3 P3_11/FLEXSPI0_A_DATA3 DQ4 OSPI Data Signal D4 P3_12/FLEXSPI0_A_DATA4 DQ5 OSPI Data Signal D5 P3_13/FLEXSPI0_A_DATA5 DQ6 OSPI Data Signal D6 P3_14/FLEXSPI0_A_DATA6 DQ7 OSPI Data Signal D7 P3_15/FLEXSPI0_A_DATA7 3. HyperRAM Configuration Process 3.1 Clock configuration The clock for FlexSPI needs to be correctly configured.   During the programming phase, it is safer to choose a lower frequency; here, we select 75MHz. 3.2 FlexSPI Initialization Configuration Structure Next, we configure the FlexSPI-related settings. We can call FLEXSPI_GetDefaultConfig to obtain some default configurations for the FlexSPI feature structure flexspi_config_t, which has a certain degree of universality and is compatible with most FlexSPI devices. For the W956D8MBYA HyperRAM, on the basis of the default configuration, add the following parameters: config.ahbConfig.enableAHBPrefetch = true; config.ahbConfig.enableAHBBufferable = true; config.ahbConfig.enableReadAddressOpt = true; config.ahbConfig.enableAHBCachable = true; config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; (1) enableAHBPrefetch: Whether to enable AHB prefetching. When enabled, FlexSPI reads more data than the current AHB burst read. (2) enableAHBBufferable: Whether to enable AHB write buffer access. After executing a write command, it returns without waiting for its completion, allowing subsequent instructions to continue executing, enhancing system concurrency. (3) enableReadAddressOpt: Controls whether to remove the AHB read burst start address alignment restriction. If enabled, burst read addresses are not restricted by byte alignment. (4) enableAHBCachable: Enables AHB bus cacheable reads. If a hit occurs, data is read from the cache, but data consistency must be ensured. (5) rxSampleClock: The clock source used for reading data. For HyperRAM, HyperRAM provides a read strobe pulse and inputs it through the DQS pin. 3.3 Detailed Explanation of FlexSPI External Device Configuration Structure When FlexSPI communicates with external devices, it often needs to coordinate communication timing with the device, such as clock frequency and data validity duration. NXP's software library provides the flexspi_device_config_t structure specifically for configuring these parameters. typedef struct _flexspi_device_config { uint32_t flexspiRootClk; bool isSck2Enabled; uint32_t flashSize; flexspi_cs_interval_cycle_unit_t CSIntervalUnit; uint16_t CSInterval; uint8_t CSHoldTime; uint8_t CSSetupTime; uint8_t dataValidTime; uint8_t columnspace; bool enableWordAddress; uint8_t AWRSeqIndex; uint8_t AWRSeqNumber; uint8_t ARDSeqIndex; uint8_t ARDSeqNumber; flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; uint16_t AHBWriteWaitInterval; bool enableWriteMask; } flexspi_device_config_t; (1) flexspiRootClk = 75000000, this parameter matches the previously set FlexSPI clock frequency. (2) flashSize = 0x2000, the size of the Flash in kilobytes. For W956D8MBYA, 64Mb = 8MB = 8 * 1024KB. (3) CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, this parameter configures the time unit for the interval between CS signal lines. (4) CSInterval = 2, this parameter configures the minimum time interval for switching between valid and invalid states of the CS signal line, measured in the units defined by the above CSIntervalUnit member. (5) CSHoldTime = 3, this parameter sets the hold time for the CS signal line, measured in FlexSPI root clock cycles. (6) CSSetupTime = 3, this parameter sets the setup time for the CS signal line, measured in FlexSPI root clock cycles. According to the MCXNx4x datasheet,T_CK = 6ns，the minimum T_CSS = 8.3ns，and the minimumT_CSH = 9.8ns。The clock period for 75MHz is approximately 13.3 nanoseconds. Therefore, both CSHoldTime and CSSetupTime should be greater than or equal to 1, So they can be configured to 3 (1) dataValidTime=2，Registers DLLACR and DLLBCR are used to configure the valid data time in communication, with the unit being nanoseconds. (2) columnspace = 3，which is the width of the low-order column address. For this HyperRAM, it uses row and column addresses for access, with a column address width of 3 bits. (3) enableWordAddress = true，this parameter is configured whether the 2-byte addressable function is enabled. Once enabled, HyperRAM will be accessed using a 16-bit data format. (4) AWRSeqIndex = 1，this parameter is the index of the write timing sequence in the LUT. (5) AWRSeqNumber =1，this parameter configures the number of sequences for AHB write commands. (6) ARDSeqIndex = 0，this parameter is the index of the read timing sequence in the LUT. (7) ARDSeqNumber =1，this parameter configures the number of sequences for AHB write commands. (8) enableWriteMask = true，this parameter is used to set whether to drive the DQS bit as a mask when writing to external devices via FlexSPI. This feature is used for address alignment when accessing data widths of 16 bits. 3.4 LUT table configuration Below is a code example of the LUT table configuration for HyperRAM read and write timing. const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* Read Data */ [4 * PSRAM_CMD_LUT_SEQ_IDX_READDATA] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * PSRAM_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07), [4 * PSRAM_CMD_LUT_SEQ_IDX_READDATA + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), /* Write data */ [4 * PSRAM_CMD_LUT_SEQ_IDX_WRITEDATA] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * PSRAM_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07), [4 * PSRAM_CMD_LUT_SEQ_IDX_WRITEDATA + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), }; (1) We are using an 8-line differential HyperRAM, which is utilized on both edges of the clock, hence the number of data lines used for communication with external memory is kFLEXSPI_8PAD. (2) HyperRAM and HyperFlash are memory products designed based on the HyperBus&#8482; interface specification by Cypress Semiconductor. This operand is defined in the specification, therefore the read operation operand is fixed at 0xA0, and the write data operand is fixed at 0x20. (3) CADDR_DDR column address: Since the number of bytes transferred in one transmission must be a multiple of 8, if the row and column addresses you provide exceed the maximum rows and columns of a specific size HyperRAM, FlexSPI will automatically set the higher bits to 0. The table above shows that the lower 16 bits are the column address, with 3 valid bits, and the upper 13 bits are reserved for compatibility and need to be set to 0. Therefore, the timing parameter for the column address here needs to be filled with 16, i.e., 0x10. (4) RADDR_DDR row address: As shown in the figure, if the FLSHxxCR1[CAS] bit is not zero, then the FlexSPI peripheral will split the actual mapped Flash Address (i.e., the memory's own offset address) into a row address FA[31:CAS+1] and a column address [CAS:1] for transmission during transfer timing. For word-addressable flash devices, the last bit of the address is not needed because the flash is read and programmed in two-byte units. FlexSPI considers one word as two bytes; thus, if alignment to two bytes is required, one less bit address is needed. The sum of row and column addresses should be one bit less. W956D8MBYA has 64Mbit, which is 2^26; with 3 bits for the column address, theoretically, 26-1-3=22 bits are needed for the row address to access the entire HyperRAM. Then, align it to 8 bits; otherwise, FlexSPI will pad zeros at the lower bits, which would not be the address we want to access. Therefore, the parameter is 0x18, i.e., 24 bits. 4. Experimental Verification We can use simple AHB read and write operations to verify whether this HyperRAM is functional. The code is as follows. for (i = 0; i < sizeof(s_psram_write_buffer); i++) { s_psram_write_buffer[i] = i; } memcpy((uint32_t*)(EXAMPLE_FLEXSPI_AMBA_BASE), s_psram_write_buffer, sizeof(s_psram_write_buffer)); memcpy(s_psram_read_buffer,(uint32_t*)(EXAMPLE_FLEXSPI_AMBA_BASE) , sizeof(s_psram_read_buffer)); if (memcmp(s_psram_read_buffer, s_psram_write_buffer, sizeof(s_psram_write_buffer)) == 0) { PRINTF("AHB Command Read/Write data successfully !\r\n"); }   When your serial port prints "AHB Command Read/Write data successfully!", it indicates that your FlexSPI connection to the HyperRAM is functioning properly.

The open source hardware community is please to offer ECAD schematic symbols for the new MCX A153 and MCX N947 microcontrollers.     The MCX A153 schematic library has the QFP32, QFN48 and LQFP64 variants. The MCX N947 schematic library has the BGA184 and LQFP100 variants. The symbols were generated using data from the MCUXpresso Pin Config tool to ensure accuracy. The pin names include all pin mux options to make it easy to see all available peripheral functions and further simplify the symbol for your own design purpose The symbol data is provided in the open source KiCad V7 format and is attached to this post. The symbols can be imported into commercial tools such as Altium Designer. Enjoy!  

An open-source PCB template for creating a custom shield for the FRDM-MCXA153  

An open-source PCB template for creating a custom shield for the FRDM-MCXN947  

FRDM Boards Enclosures (3D Print)   Hi NXP FRDM enthusiasts! we want to share some 3D files that you can use to 3D print your own enclosures for the FRDM-MCX family!    FRDM-MCXN947 case step files are here   FRDM-MCXA153 case step files are here   FRDM-MCXW71 case step files are here

These two lab guides provide step-by-step instructions on how to take a quantized TensorFlow Lite model and use the Neutron Conversion Tool found in eIQ Toolkit to convert the model to run on the eIQ Neutron NPU found on MCX N devices.  The eIQ Neutron NPU for MCUs Lab Guide - Part 1 - Mobilenet.pdf document focuses on using the eIQ Toolkit GUI method to convert a model and then import that converted model into an eIQ MCUXpresso SDK example. It is recommended to go through this lab first.    The eIQ Neutron NPU for MCUs Lab Guide - Part 2 - Face Detect.pdf document focuses on using the eIQ Toolkit command line utilities to convert a model for the eIQ Neutron NPU and integrate that newly converted model into the Face Detect demo found on the Application Code Hub. Both labs were designed to run on the FRDM-MCXN947 but the same concepts can be applied to other MCX N boards.  Also be sure to also check out the Getting Started community post for more details on the eIQ Neutron NPU. --- Updated November 2024 for eIQ Toolkit 1.13.1

1. RS485 hardware connection RS-485 is a multiple drop communication protocol in which the LPUART transceiver's driver is three-stated unless LPUART is driving. The transmitter can uses the RTS_B signal to enable the driver of a transceiver. The polarity of RTS_B can be configured by firmware to match with the polarity of the transceiver's driver enabling signal. The following figure shows the receiver enabling signal asserted. This connection can also connect RTS_B to both DE and RE_B. The transceiver's receiver is disabled when the uart transmitter is sending char. A pullup can pull RXD to a non-floating value during this time. You can refine this option further by operating LPUART in Single-Wire mode, freeing the RXD pin for other uses.     When the uart transmits character via TXD pin, the RTS_b signal is asserted automatically, after the RS-485 transceiver, the urat transmitter can drive the differential signals Y/Z. When the uart dose not transmit character, the RTS_b signal is unasserted, so the RS-485 transceiver is in tr-state, the differential signal Y/Z is NOT driven by this RS-485 transceiver. For receiver part of the RS-485 transceiver, if the RTS_b sigbal is connected to the RE_b pin of receiver of RS-485 transceiver directly or via an inverter depending on the required logic of the RS-485 transceiver , when the uart transmits character, the receiver of  RS-485 transceiver is disabled, the RO pin of the RS485 is in tri-state, so a pull-up resistor is required on the RO pin and the RXD pin of LPUart can not receive any character from it’s own transmitter.  The RTS_B signal can function as hardware flow control, but note the application uses RTS_b signal to control RS485 enabling instead of hardware flow control. )   2. RTS_b pin assigmnet.   For the uart module of MCXN family, the FCx_P0 is RXD pin of UARTx module, the FCx_P1 is TXD pin of UARTx module, the FCx_P2 is RTS_b of UARTx module. For MCXN94x family, the P1_8 pin can function as FC4_P0 or RXD pin of UART4; the P1_9 pin can function as FC4_P1 or TXD pin of UART4; the P1_22 pin can function as FC4_P2 or RTS_b pin of UART4 with setting up PORT1_PCR22[MUX] bits as decimal 3;   3)software 3.1 pin assignment void BOARD_InitPins(void) {     /* Enables the clock for PORT1: Enables clock */     CLOCK_EnableClock(kCLOCK_Port1);       const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */                                                     kPORT_PullDisable,                                                     /* Low internal pull resistor value is selected. */                                                     kPORT_LowPullResistor,                                                     /* Fast slew rate is configured */                                                     kPORT_FastSlewRate,                                                     /* Passive input filter is disabled */                                                     kPORT_PassiveFilterDisable,                                                     /* Open drain output is disabled */                                                     kPORT_OpenDrainDisable,                                                     /* Low drive strength is configured */                                                     kPORT_LowDriveStrength,                                                     /* Pin is configured as FC4_P0 */                                                     kPORT_MuxAlt2,                                                     /* Digital input enabled */                                                     kPORT_InputBufferEnable,                                                     /* Digital input is not inverted */                                                     kPORT_InputNormal,                                                     /* Pin Control Register fields [15:0] are not locked */                                                     kPORT_UnlockRegister};     /* PORT1_8 (pin A1) is configured as FC4_P0 */     PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);       const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */                                                     kPORT_PullDisable,                                                     /* Low internal pull resistor value is selected. */                                                     kPORT_LowPullResistor,                                                     /* Fast slew rate is configured */                                                     kPORT_FastSlewRate,                                                     /* Passive input filter is disabled */                                                     kPORT_PassiveFilterDisable,                                                     /* Open drain output is disabled */                                                     kPORT_OpenDrainDisable,                                                     /* Low drive strength is configured */                                                     kPORT_LowDriveStrength,                                                     /* Pin is configured as FC4_P1 */                                                     kPORT_MuxAlt2,                                                     /* Digital input enabled */                                                     kPORT_InputBufferEnable,                                                     /* Digital input is not inverted */                                                     kPORT_InputNormal,                                                     /* Pin Control Register fields [15:0] are not locked */                                                     kPORT_UnlockRegister};     /* PORT1_9 (pin B1) is configured as FC4_P1 */     PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);       //* PORT1_22 (pin L4) is configured as FC4_P2 with ALT3*/       const port_pin_config_t port1_22_pinC3_config = {/* Internal pull-up/down resistor is disabled */                                                        kPORT_PullDisable,                                                        /* Low internal pull resistor value is selected. */                                                        kPORT_LowPullResistor,                                                        /* Fast slew rate is configured */                                                        kPORT_FastSlewRate,                                                        /* Passive input filter is disabled */                                                        kPORT_PassiveFilterDisable,                                                        /* Open drain output is disabled */                                                        kPORT_OpenDrainDisable,                                                        /* Low drive strength is configured */                                                        kPORT_LowDriveStrength,                                                        /* Pin is configured as FC4_P1 */                                                        kPORT_MuxAlt3,                                                        /* Digital input enabled */                                                        kPORT_InputBufferEnable,                                                        /* Digital input is not inverted */                                                        kPORT_InputNormal,                                                        /* Pin Control Register fields [15:0] are not locked */                                                        kPORT_UnlockRegister};        /* PORT1_9 (pin B1) is configured as FC4_P1 */        PORT_SetPinConfig(PORT1, 22U, &port1_22_pinC3_config); }   The   //P1_22 function as RTS_b signal void RTS_b_init(LPUART_Type *base) {  base->MODIR |=LPUART_MODIR_TXRTSE(1); //                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)   }   4)uart timing tested by scope   Conclusion: From the above scope screen shot, you can see that when the uart transmitter sends char, the RTS_b signal becomes low, so it can function as RS485 transceiver enabling signal.  

The Serial Peripheral Interface (SPI) is ubiquitous in embedded systems for interfacing to external peripherals such flash memories, EEPROMs, analog to digital converters and sensors. SPI controllers are essentially shift registers. When combined with DMA, SPI can be used for interesting use cases. In this paper we will look at an LED lighting application and hint at some other interesting use cases such as PDM audio streams.

When deploying a custom built model to replace the default models in MCUXpresso SDK examples, there are several modifications that need to be made as described in the eIQ Neutron NPU hands-on labs. Here are some common issues and error messages that you might encounter when using a new custom model with the SDK examples and how to solve them. If there is an issue not covered here, then please make a new thread to discuss that issue.    “Didn't find op for builtin opcode ‘<operator_name>’” Need to add that operator to MODEL_GetOpsResolver function found in source\model\model_name_ops_npu.cpp A full list of operators used by a model that can be copy-and-pasted into that file is automatically generated by Neutron Converter Tool with the dump-header-file option. Make sure to also increase the size of the static array s_microOpResolver to match the number of operators   “resolver size is too small” Need to increase the size of the static array s_microOpResolver in MODEL_GetOpsResolver function found in source\model\model_name_ops_npu.cpp to match the number of operators     “Failed to resize buffer” The scratch memory buffer is too small for the model and needs to be increased. The size of the memory buffer is set with the kTensorArenaSize variable found in the model data header file   “Internal Neutron NPU driver error 281b in model prepare!” or “Incompatible Neutron NPU microcode and driver versions!” Ensure the version of the eIQ Neutron Converter Tool used to convert the model is the correct one that is compatible with the NPU libraries used by the SDK project.  eIQ Toolkit v1.10.0 should be used with MCXUpresso SDK for MCX N 2.14.0. The Neutron Converter Tool version is 1.2.0+0X84d37e1f     Camera colors are incorrect on FRDM-MCXN947 board Modify solder jumpers SJ16, SJ26, and SJ27 on the back of board to move them to the left (dashed line side) to connect camera signals properly.             This modification will disable Ethernet functionality on the board due to a signal conflict with EZH D0 and ENET_TXCLK. If your project needs both camera and Ethernet functionality, then only move SJ16 and SJ26 to the left (dashed line side) and then connect a wire from P1_4 (J9 pin 😎 to the left side of R58. Then in the pin_mux.c file in the project, instead of using PORT1_PCR4 for EZH_Camera_D0, use PORT3_PCR0.                           

Using external PSRAM on the MCX N FlexSPI port can enable a large degree of application flexibility. In this paper we show how to add 8MB of Octal DDR PSRAM to the MCXN947 and execute baseline performance tests.

The NXP MCXA153 is a useful microcontroller for small, embedded USB devices. Combined with the USB stack built into the SDK, or with the open source TinyUSB stack,  it is easy to creak your own USB protocol bridges and test tools. In this paper we showed to how to integrate TinyUSB into an MCUXpresso project and demonstrated  with a USB CDC / WebUSB application for a BLDC Motor controller test application.

Part 1: Introduction The eIQ Neutron Neural Processing Unit (NPU) is a highly scalable accelerator core architecture that provides machine learning (ML) acceleration. Compared to traditional MCUs like the Kinetis series and LPC series, the MCX N series marks the first integration of NXP's eIQ® Neutron NPU for ML acceleration. The eIQ Neutron NPU offers up to 42 times faster machine learning inference performance compared to a standalone CPU core. Specifically, the MCX N94 can execute 4.8G (150MHz * 4 * 4 * 2) INT8 operations per second. The eIQ Portal, developed in exclusive partnership with Au-Zone Technologies, is an intuitive graphical user interface (GUI) that simplifies vision based ML solutions development. Developers can create, optimize, debug and export ML models, as well as import datasets and models, rapidly train and deploy neural network models and ML workloads for vision applications. Hardware Environment: Development Board: FRDM-MCXN947 Display: 3.5" TFT LCD (Part Number: PAR-LCD-S035) Camera: OV7670 Software Environment: eIQ Portal: eIQ® ML Software Development Environment | NXP Semiconductors MCUXpresso IDE v11.9.0 Application Code Hub Demo：Label CIFAR10 image   Part 2: Basic Model Classification Training and Deployment The main content is divided into three steps: model training, model converting, and model deployment. 1. Dataset Preparation The dataset is prepared for a simple demonstration of binary classification between apples and bananas. The training set and test set are split in an 8:2 ratio. This follows the guidelines mentioned in section 3.3.2 Structured Folders Dataset of the eIQ_Toolkit_UG.pdf: The folder structure is as follows:   Note: The dataset needs to be organized according to the above folder structure. 2. Create Project and Import Dataset into eIQ a. Open the eIQ Portal tool, click on "CREATE PROJECT" -> "Import dataset". b. Import using "Structured folders" as follows: c. After clicking "IMPORT", select the project save path and click "Save".   3. Select Base Model for Training a. After the dataset is imported, click on "SELECT MODEL" and choose a base model. Modify the "Input Size" to 128, 128, 3.   b. Click on "Start Training". Note: Other parameters can be set according to your needs, and here the "learning rate", "batch size", and "epoch" are set to their default values. This is a demonstration and trains the model for one epoch. Users can train the model as needed to meet application requirements. Upon completion of training, it will look like this: If the accuracy does not meet the required standard, you can modify the training parameters or update the training data, and then click "CONTINUE TRAINING" to continue the training process. 4. Model Evaluation "VALIDATE" a. Click on "VALIDATE" to enter the model evaluation stage. Set the parameters including "Softmax Threshold", "Input Data Type", and "Output Data Type". Currently, the MCXN series Neutron NPU only supports the int8 data type. It should look like this:   b.After setting the parameters, click on "VALIDATE" and wait for the confusion matrix to be generated. The confusion matrix provides a clear view of how different categories are classified. In the diagram, the x-axis represents the predicted labels, while the y-axis represents the actual labels. You can see the correspondence between the predicted and actual labels for each image, as shown below:   5. Model Export to TensorFlow Lite a. Click on "DEPLOY", set the "Export File Type", "Input Data Type", and "Output Data Type". Turn on "Export Quantized Model", and then click on "EXPORT MODEL", as shown below: b. Set the location to save the model and click "Save". 6. Convert to TensorFlow Lite for Neutron (.tflite) a. After saving, click on "OPEN MODEL" to view the model structure, as shown below:   b. Click on "Convert" and select "TensorFlow Lite for Neutron (.tflite)" as shown below:   c. Select the "Neutron target", click on "Convert", and set the save path. It should look like this:   7. Deploy the Model to the Label CIFAR10 Image Project This example is based on a machine learning algorithm supported by the MCXN947, which can label images captured from a camera and display the type of object at the bottom of the LCD. The model is trained on the CIFAR10 dataset, which supports 10 categories of images: "Airplane", "Automobile", "Bird", "Cat", "Deer", "Dog", "Frog", "Horse", "Ship", "Truck". a. Open MCUXpresso IDE and import the Label CIFAR10 Image project from the Application Code Hub, as follows:   b. Select the project, click on "GitHub link" -> "Next", as shown below:   c. Set the save path, click "Next" -> "Next" -> "Finish", as shown below:   d. After successful import, click on the "source" folder -> "model" folder, open "model_data.s", and copy the model file converted through eIQ into the "model" folder. Modify the name of the imported model (the name of the converted model) in "model_data.s", as shown below:   Note: The model imported into the project is the one obtained after multiple training sessions. e. Click on the "source" folder -> "model" folder -> open the "labels.h" file. Modify the "labels[]" array to match the order of labels displayed in the dataset in eIQ, as shown below:     f. Compile the project and download it to the development board.   Part 3: Experimental Results     Part 4: Summary By efficiently utilizing the powerful performance of the eIQ Neutron NPU and the convenient tools of the eIQ Portal, developers can significantly streamline the entire process from model training to deployment. This not only accelerates the development cycle of machine learning applications but also enhances their performance and reliability. Therefore, for developers looking to implement efficient machine learning applications on MCX N-series edge devices, mastering these technologies and tools is crucial.   We can also refer to the video for detailed steps. https://www.bilibili.com/video/BV1SS411N7Hv?t=12.9 

The table below contains notable updates to the current release of the Reference Manual. The information provided here is preliminary and subject to change without notice. Affected Modules Issue Summary Description  Date MCXNx4x Pinout xlsx Attachment Defeature PF* pins Erroneous pinouts to PF* signals on ALT11 are removed.  Before:    After:    01 March 2024 System Boot ROM API Missing Boot Modes sections in ROM API chapter of System Boot New sections added: 15.3 Boot modes 15.3.1 Master boot mode Master boot mode supports the following boot devices: Internal flash memory boot FlexSPI NOR flash memory boot SPI 1-bit NOR recovery boot Secondary bootloader boot Table 229. Image offsets for different boot media   Boot media Image offset Internal flash memory boot 0h FlexSPI NOR flash memory boot 1000h SPI 1-bit NOR recovery boot 0h Secondary bootloader boot 0h   15.3.2 Secondary bootloader mode   The Secondary bootloader mode can be enabled by setting the CMPA[BOOT_SRC] as 2, the image loaded in the Bank1_IFR0 region (0x0100_8000 to 0x0100_FFFF) will be set as primary boot mode, and the secondary boot image will boot first after the device reset. The secondary boot image type can be plain, crc or signed image, but cannot set as the SB file.   Based on the CMPA[OEM_BANK1_IFR0_PROT](0x01004004[5:7]) setting, after the secondary boot image boot, the Bank1_IFR0 region will be configured with different MBC setting:   Lifecycle CMPA[OEM_BANK1_IFR0_PROT] Secondary bootloader mode MBC IFR0 recovery boot MBC Develop (0x3) NA GLABC0 GLBAC0 Develop2 (0x7), In-field (0xF), In-field Locked (0xCF), Field Return OEM (1F) 0 GLBAC4 GLBAC4   1 GLBAC4 2 GLBAC2 3 GLBAC6 4 GLBAC4 5 6 7     01 March 2024 Input Multiplexing (INPUTMUX) Clarification to CMP trigger input registers Update to the CMPx_TRIG Register function description for the following registers: CMP0_TRIG (260h), CMP1_TRIG (4EOh), and CMP2_TRIG (500h)  Before:  Function This register selects the CMPx trigger inputs   After: Function This register selects the CMPx SAMPLE/WINDOW input 01 March 2024  

  The MCX  N series are MCUs with an integrated flash memory like many traditional MCU series. Having an embedded flash memory is particularly useful, as facilitates board design, development, simplifies BOM, software development.  However, the size of the embedded flash might not meet applications required memory footprint. Some customers simply need more flash memory. For example, Graphical applications require store large image buffers in a non-volatile memory. Data logger devices that need to store large amounts of data. Or heavy inference models for object recognition.  Applications that need to store backup versions of their firmware or are way too complex and big. To solve this requirement the MCX N94x provides the capability to interface a great variety of wider and external memories. There are several traditional options to expand flash storage, but the one we are addressing is the use of external NOR  flash memories. To access an external memory the MCX N94x integrates modules that support external memory interfacing, those are  FlexIO and the FlexSPI. The FlexSPI module is capable of communicating with several kinds of memories. One of them is the Serial NOR flash which can be used as booting device. The goal of this article is to present the solution of a customer case scenario: How to run code from an external flash memory. Demonstrating the flexibility of the MCX N94x platform as well as introducing several tools, peripherals, and concepts that a developer will need to be familiar with while developing an application that runs from an external flash memory. The below figure illustrates the goal of this article, Run code from an external flash memory. The same hello world application can be run from the internal and external memory, for example, a NOR serial QuadSPI memory, without any functionality changes. The core simply will fetch and execute the instructions, using dedicated peripherals like FlexSPI.   Figure 1 Executing same code from internal memory vs external memory. The MCX N94x series integrates a FlexSPI module, which enables running code from an external NOR flash memory.   Figure 2 MCX N94x block diagram To follow this article, you will need the  FRDM-MCXN947 Development board. Which is the evaluation board for the MCX N94x and N54x MCUs. The FRDM-MCXN947 integrates a W25Q64JVSSIQ QuadSPI flash memory. Therefore, this platform is perfect for creating an application that runs from an external flash memory. Figure 3 External NOR flash memory on FRDM-MCXN947   Boot, PFR, and SPSDK   With the boot ROM  that the MCX  N integrates you can erase, program, and read the on-chip or external flash memory, which means you can use the boot ROM to download a boot image into the on-chip or external flash memory via the ISP interfaces. This article shows how to load a customized led_blinky demo, from the SDK  to the external flash memory using the boot ROM. However, other application projects may be used as well. Also, the boot ROM takes responsibility for the boot flow. It selects whether to boot from on-chip flash memory, external flash memory, or ISP mode.  The figure below shows an extremely simplified boot flow, which gives an overall understanding of the chip boot flow.  For more details on the boot flow mechanism refer to the section Top-level boot flow of the MCX Nx4x Reference manual.   Figure 4 Simplified boot Flow After the reset handling routine, the boot ROM will take control of the chip’s boot flow. It will begin with pertinent chip’s initialization. Then will check the status of the ISP pin. If the ISP pin is currently asserted, the ISP boot handling routine will be executed. ISP or  In-system programming is an execution mode where the boot ROM will wait for commands from an external host, over protocols like UART or USB, to do actions like read and write the chip memory, burn fuses, and many more. If the ISP pin is not asserted, the boot ROM will continue to determine the boot mode. Boot mode can be controlled with the CMPA[BOOT_SOURCE] bit of the CMPA of the PFR or eFUSES. If  CMPA[BOOT_SOURCE]= 01b the boot ROM will run FlexSPI NOR boot handling routine. If CMPA[BOOT_SOURCE] is 00b or 11b internal flash memory handling routine is executed. After the boot mode selection, the image will be validated. If it is not valid, for example, is not present in memory, is corrupted, or does not have proper format,  the ISP boot handling routine is executed. If the image is valid, finally the boot ROM will perform the jump to the user´s application. The default boot flow is by internal flash, most of the SDK examples will be configured to boot from internal flash, as CMPA[BOOT_SOURCE] equals zero by default, or when CMPA area is erased. According to the Simplified bot Flow diagram, we need to make boot ROM go to FlexSPI NOR boot handling routine, to boot from the external flash. Therefore, we need to make   CMPA[BOOT_SOURCE] = 01b. The PFR holds critical boot and security settings that are monitored by the boot ROM after every reset. As just described earlier, the CMPA area can be used to control boot mode. Therefore, PFR areas need to be carefully configured, as they control boot flow and also security features of the chip. The below figure shows a very minimalistic representation of the PFR containing the CMPA, next to the internal flash.   Figure 5 PFR's CMPA area   For specific details of the PFR  please refer to the MCXNx4x_IFR.xlsx, attached to the MCX Nx4x Reference Manual. To facilitate writing into the CMPA and other areas of the  PFR, signing applications, burning fuses.  programming applications, NXP already developed several host command tools, APIs, and applications and integrated into a python tool called SPSDK. The below figure shows all the tools contained by the SPSDK. To get  details on the SPSDK and description of APIs, Applications, and tools  refer to SPSDK documentation at  https://spsdk.readthedocs.io/en/latest/spsdk.html#   Figure 6 SPSDK API modules, applications, and tools The above figure highlights 3 applications, provided by the SPSDK,  that is going to be used to configure the chip to boot from the external flash memory those are: nxpdebugmbox, PRF, and BLHOST. Detailed step-by-step usage of these applications will be described later on.  The nxpdebugmbox application sends interfaces with the chip’s debug mailbox over SWD. The purpose of this tool is set MCU into ISP mode, without having to set low ISP pin,  also to make a mass erase to the chip's memory and PFR. Once the MCU enters ISP mode the host PC will be able to communicate with the boot ROM over UART or USB protocols. This enables the use of PFR and BLHOST applications. The PFR application will be used to write the CMPA[BOOT_SOURCE] = 01b and enable FlexSPI, port to probe and let the chip communicate with the external flash, in the CMPA area of the PFR. The BLHOST application will be used to erase the chip and program application image, in this particular case,  a led_blinky demo.    External Serial NOR flash interfacing   The following terms are critical to understand how we can execute code in an external NOR flash memory with the MCX N94x. First of all, Execute-in-Place refers to the capability that the MCU core has to fetch and execute instructions directly from the external memory. It refers to the capability that an MCU has to execute code from the flash memory instead of an internal and traditional flash. To do XIP the MCX  N94x requires a capable peripheral with the ability to fetch instructions from the external memory. The FlexSPI module is capable of doing this. The FlexSPI does support several types of external memories. One of them is Serial NOR Flash. To interface the external memory with the FlexSPI supports SPI. SPI is an excellent serial protocol for short-distance and high-speed communications. The term QuadSPI could be simply understood as an implementation of the SPI protocol, where instead of having a single Data line, there are 4 data lines. SPI also supports two, and eight data lines. Flexible Serial Peripheral Interface (FlexSPI) memory controller supports connection to external serial NOR, NAND, and RAMs. It supports two SPI channels and up to four external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines). Flexible sequence engine (LUT table) to support various vendor devices (serial NOR, serial NAND, HyperBus, FPGA, etc). Memory-mapped read/write access by AHB Bus AHB RX Buffer implemented to reduce read latency. Total AHB RX Buffer size: 1024 Kbytes 8 flexible and configurable buffers in AHB RX Buffer Software triggered Flash read/write access by IP Bus IP RX FIFO implemented to buffer all read data from External device. FIFO size: 1024 Bytes IP TX FIFO implemented to buffer all Write data to External device. FIFO size: 1024 Bytes DMA support to fill IP TX FIFO DMA support to read IP RX FIFO   Figure 7 FlexSPI block diagram   FlexSPI system memory map regions are remapped to different addresses at the FlexSPI sub-module:   Figure 8 FlexSPI memory map FlexSPI can support serial devices compliant with JESD216. Pre-requisites You will need the following Hardware: FRDM-MCXN947 evaluation board. USB C cable. Windows or Linux PC. You will need to install the following Software. MCUXpresso IDE v11.9.0 or above.  FRDM-MCXN947 SDK v2.15.0 or above.  SPSDK and python.     SPSDK installation and virtual environment   We recommend to run the SPSDK on a python virtual environment, as this simplifies the installation of the SPSDK. Before proceeding with installation steps for the SPSDK we recommend to create a folder in your computer. This is where the virtual environment will be running, the SPSDK tools will be called,  and all the files generated by the SPSDK will be stored. Open a terminal, command, or Power Shell prompt  and navigate to your folder and follow the SPSDK installation  commands listed in this guide: Installation Guide — SPSDK documentation            To double check installation of the SPSDK run the following command in your virtual environment. spsdk --version         This figure shows the example of this command and the spsdk version used for this document.   Figure 9 SPSDK version.  Setup  This chapter describes all steps to generate and boot an image from the external memory.  To run the commands listed in this document you will need use your python’s virtual environment. Use the virtual environment you created during SPSDK installation.  PFR settings This section describes the settings that need to be done in the MCX N94x PFR and bootable image.        Create CMPA and CFPA yaml  templates   In the following steps, we are going to focus on editing CMPA area since it contains boot-related fields for external execution.  CFPA area is not required to be edited.            Note:The commands used to generate the templates are based on ‘pfr’ tool  For details on the capabilities of these commands, visit: User Guide - pfr — SPSDK documentation First we are going to use pfr to create our yml CMPA/CFPA templates. These templates contain only the default configurations specified for the CMPA and CFPA areas of  device. If the command run successful the templates will be generated. As shown in figure this figures   Figure 10 Yaml template created.   Edit the CMPA and CFPA yaml templates   Open CMPA   template in any text editor and follow the below steps. Set DEFAULT_BOOT_SOURCE to FLEXSPI_FLASH_XIP_0b01 Set FLEXSPI_AUTO_PROBE   to ENABLE Save the changes in the CMPA template.      Create and write the  CMPA and CFPA binaries         After editing the cmpa yaml, you will generate the CMPA/CFPA binaries from the yml templates.     Import and edit image   This section shows how to create an XIP bootable image from the  MCUXpresso SDK  led_blinky example.    Import the led_blinky demo from the SDK.  Click on “Import SDK example(s)…” (1), then search and select the FRDM-MCXN947 (2), and click “Next” (3). Inside the “SDK import wizard” search and select the “led_blinky  demo (4) and click on “Finish” (5)     Figure 11 Import the blinky example.      Once the demo project is imported open the project properties. Do a right-click in the project’s name (1), then click on “Properties” option (2) and open the project properties(3)   Figure 12 Project ´properties Navigate to the Properties> C/C++ Build > MCU settings section       Figure 13 MCU settings window Make sure that there are two  Flash areas for the external memory: QSPI_FLASH and             QSPI_FCB as shown in Figure 14. If the areas are missing add them as shown in the next step.     Figure 14 External flash areas in the linker.     Add the two flash areas for the  QSPI_FLASH and QSPI_FCB in the “Memory details” table, the move them to the Top.  Click in “Add Flash”  (1) twice, then click on “Move selected memory up in table” (2), the two newly created flash areas should be placed at the top.   Note: Moving a memory area to the top of the “Memory details” table indicates the linker that text and data should be placed preferably in that area. Update the newly created flash areas name and parameters with the ones from the below table.   Type Name Alias Location Size Driver Flash QSPI_FLASH Flash 0x80001000 0xFFFF000 MCXN9xx_SFDP_FlexSPI.cfx Flash QSPI_FCB Flash 2 0x80000400 0x400 MCXN9xx_SFDP_FlexSPI.cfx     Make sure that the flash areas match the ones shown in the Figure 15.     Figure 15 Configured flash areas    Click “Build” (1), once compilation is finished, should return 0 errors (2).   Figure 16 Successfully compiled image.                                      Note: You should see that the QSPI_FLASH section is being used and that the PROGRAM_FLASH section is not. Generate the binary. Navigate to the project’s debug folder and locate generated .axf (1). Then do a right-click in the .axf, and click on Binary utilities > Create Binary.   Figure 17 Create binary.   7 The binary should appear in the debug folder. Get  easily get the binary location by doing a right click on the binary and navigating to  “Show in>System Explorer”   Figure 18 Get created binary with ease. 8. Paste the binary into the workspace where you created the cmpa_bin.bin. This step is only to simplify the commands shown later on.   Erase and ISP mode entry        ISP (In system programming ) is a mode where a host is able to instruct the ROM bootloader to program a new image or the PFR. The which holds the CMPA field with our configuration to do XIP from the external flash memory. Basically, the Host computer sends commands to the ROM bootloader to program the PFR using NXP’s BLHOST. To enter into ISP mode there are two options: ISP pin entry and Debugger mailbox. ISP pin entry requires keeping ISP pin asserted during reset sequence and de-asserting this pin after reset has been completed. Debugger mailbox only requires to use of a SWD debugger to make the ROM entry ISP mode. To enter into ISP mode over ISP pins follow is necessary keep ISP pin asserted during reset sequence and de-assert this pin after reset has been completed. To use the debugger mailbox is only needed having a debugger. For simplicity, the communication protocol will be USB. However, UART can be used as well. Erase the flash memory and enter ISP mode using the nxpdebugmbox. Proceed to run each command nxpdebugmbox erase  nxpdebugmbox ispmode -m 0   This figure shows the expected output when running the two commands from above.   This operation will erase the contents on the internal and external flash memory. Also the PFR contents. Repeating this operation can be useful to get the chip to boot from internal flash memory. Note:  nxpdebugmbox commands need to be run using a SWD-JTAG debugger. For this example on-board debugger of the FRDM-MCXN947 is used. Ping rom Bootloader  Run the following command to ping the rom Bootloader, this way we can ensure that the device was set correctly in ISP mode. blhost  -t 2000 -p COMxxx,115200 -j -- get-property 1     Figure 19 Ping rom Bootloader From now on, an external debugger is not strictly required. The communication with the rom bootloader can be done over UART or USB. For simplicity, the UART protocol-based commands are used from now on in the rest of this document. Write  image and PFR and run demo   We are going to follow the steps to write image.  1 Write CMPA binary. pfr write -p COMxxx,115200 -t cmpa -f mcxn9xx -b cmpa_bin.bin   2 Write CFPA binary. pfr write -p COM140,115200 -t cfpa -f mcxn9xx -b cfpa_bin.bin   3 Provide FlexSPI flash memory configuration blhost  -t 2000 -p COMxxx,115200 -- fill-memory 0x20000000 0x04 0xc0000405   4 Configure and fill memory. blhost  -t 2000 -p COMxxx,115200 -- configure-memory 0x09 0x20000000 blhost  -t 2000 -p COMxxx,115200 -- fill-memory 0x20003000 0x04 0xf000000f   5 Erase flash blhost  -t 2000 -p COMxxx,115200 -- flash-erase-region 0x80000000 0x100000   6 Configure memory. blhost  -t 2000 -p COMxxx,115200 -- configure-memory 0x09 0x20003000    7 Write image. blhost  -t 2000 -p COMxxx,115200 write-memory 0x80001000 frdmmcxn947_led_blinky.bin   8 Reset. blhost  -t 2000 -p COMxxx,115200 reset You might use this command or directly press the reset button from the FRDM board. The below image shows the successful execution of each command. Your FRDM-MCXN947  should be blinking by now. Figure 20 Successful image write and reset. Once the board is reset you will notice that the loaded example will begin to execute.    Double-check execution from external flash    To double-check that the image is executing from the external flash you can use the disassembly view from MCUXpresso. 1  Attach the debugger to the running target and place a breakpoint at any part of the code.   Figure 21 Attach debugger to a running target. Once your debug probe is discovered, click “OK.”   Halt the processor execution. Use the debug button.   Figure 22 halt execution. Reset processor. Use the “Restart button”. The program should be stop at the first line of the main function.   Figure 23 Breakpoint at main. Find and open the disassembly view. Click on “Instruction Stepping Mode” button or search for disassembly. Any option will open the MCUXpresso “Disassembly” view.   Figure 24 Open "Disassembly" view Processor must be running at 0x8000_0000 address space. On the disassembly view you can check that the instructions are executed from address on the range of 0x8000_xxxx which is assigned for external flash.   Figure 25 Running code from external flash. If you want to return the device to run from internal memory, then you need to go back to default values. If there are no modifications, to the ones shown in this document,  to the CMPA and CMPA areas, the nxpdebugmbox command can be executed.      

Introduction The MCX N has a Programmable Logic Unit (PLU) capable of creating combinational and sequential logic circuits that operate independently of the cores. The PLU does this by preprogramming look up tables or LUTs that dictate the behavior of designated outputs for all inputs of the PLU. The features of the MCX N PLU module includes: An array of 26 inter-connectable, 5-input look-up table (LUT) elements. 4 flip-flops. Six primary inputs pins. Eight primary output pins. An external clock to drive the four flip-flops if a sequential network is implemented. Capability to generate interrupts and wakeup requests from Sleep and Deep Sleep modes.   Module architecture The PLU is composed of 3 main elements: Look Up Tables (LUTs), Multiplexers and Flip Flops. Look Up Tables are used to create the actual logic of the PLU’s network, while multiplexers route these logic signals to and from other LUTs, as well as the PLU’s input and output pins. Flip Flops provide a method of gating logic signals from LUT elements to a shared clock input, adding a mechanism of synchronization and delay to the logic network.   Look Up Table (LUT) The PLU module has 26 inter-connectable Look Up Tables (LUTs), which can implement any combinational function with up to five inputs at once. The LUTs work by storing a pre-programmed output for every combination of inputs. This allows the look up tables to reproduce a specific output of logical 0 or 1 as soon as the input is changed without any processing required. By interconnecting LUT elements with one another, more complex programmable networks can be achieved, providing functionality of many logic gates at once.   Multiplexers The PLU module includes a variety of multiplexers that select the inputs and outputs for each Look Up Table (LUT) element. Each LUT element has 5 input multiplexers that route a signal to each of its 5 inputs. The available input signals for each LUT include: PLU Input pads. Other LUT element outputs. State Flip Flop outputs.   The PLU also has one output multiplexer for each PLU output pad (eight in total) that selects what Look-Up Table or Flip Flop state will drive each output pad.   Flip Flops The final PLU element is a type D flip flop that allows for retention of data, providing the means for sequential logic circuits and simple state machines.   The PLU module has 4 flip flops that are connected to the outputs of LUTs[3:0] as well as the external PLU_CLKIN signal that is used for timing and synchronization between flip flops. In order to use the flip flop elements, a clock signal must be supplied via the PLU_CLKIN pad. Note that since the flip flops are directly connected to the outputs of the first 4 LUT elements, the corresponding LUT elements must be set up in order to use each Flip Flop element.     PLU Setup The following steps must be done in order to achieve a logic network on the PLU module: Enable clocks for the PLU using the SYSCON_SYSAHBCLKCTRLx register and then toggle the PLU Reset bit from the SYSCON_PRESETCTRLx register. Assign pins using the PORTx_PCRn registers. Create logic network using the following steps: Write the logic behavior in the truth table register for each of the LUT elements that will be used. Program the input multiplexer registers to select the source of up to five inputs presented to each LUT. Program the output multiplexer register to select up to eight primary outputs from the PLU module. (Optional) Set the wakeup behavior by using the WAKEINT_CTRL register to select the outputs to be used as wakeup sources, as well as setting a deglitching method.   Creating logic networks Basic logic gates With a simple configuration of two inputs and one output on a single LUT element, all of the basic logic gates can be achieved. This would be achieved, for example, using a configuration of PLU_IN0 and PLU_IN1 pads as inputs and PLU_OUT0 pad as output for LUT0.   The first step of creating any logic network is to understand the truth table of the desired logic circuit. For a single AND gate using the previous configuration, the truth table would equate to the following: #   PLU_IN1 PLU_IN0 PLU_OUT0 0   0 0 0 1   0 1 0 2   1 0 0 3   1 1 1   The LUT would have to be set up in a way were the output is HIGH only when PLU_IN1 and PLU_IN0 are both HIGH, which is coincidentally the third combination of the LUT inputs for the previous truth table. Therefore, we need to program the LUT to output HIGH for combination #3. We can program this logic gate by writing a '1' on bit number 3 of the LUT’s truth table register. This way, when both LUT0 inputs are HIGH, the LUT element will “look up and find” a ‘1’, so it will output HIGH. On the other hand, for every other combination it will find a ‘0’ and output LOW. Combination # (Input) Truth table register (Output) 0 (0b00) 0 1 (0b01) 0 2 (0b10) 0 3 (0b11) 1   Taking this into account, it is easy to see that all the LUT element does is "look up" each combination of inputs on a predefined table to know what logic to output. This table is programmed via the 32 bit LUTa_TRUTH register for each LUT element. The 32 bit value required for the previous logic gate expressed in hexadecimal would then be as follows: AND gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 1 0 0 0 → 0x00000008 And, for the rest of the basic logic gates: OR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 1 1 1 0 → 0x0000000E   XOR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 0 1 1 0 → 0x00000006   NAND gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 0 1 1 1 → 0x00000007   NOR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 0 0 0 1 → 0x00000001   XNOR gate LUT inputs[1:0] 11 10 01 00     LUT0_TRUTH 1 0 0 1 → 0x00000009   NOT gate LUT inputs[0] 1 0     LUT0_TRUTH 0 1 → 0x00000001   Buffer gate LUT inputs[0] 1 0     LUT0_TRUTH 1 0 → 0x00000002   Note that the truth table value for a NOR gate and a NOT gate is the same in this case, as both require an output of ‘1’ for the first combination of inputs and ‘0’ for the rest. This demonstrates how the PLU does not actually create an array of logic gates but rather, simply outputs predefined values from a table of all possible combinations of inputs. The previous tables show the register values to achieve all of the basic logic gates with the previous setup of LUT0. However, in order to achieve this configuration with input pins PLU_IN0 and PLU_IN1 as well as output pin PLU_OUT0, the multiplexers would have to be set up in the following manner:   In order to achieve this, pin PLU_IN0 must be routed as input[0] of LUT0 and PLU_IN1 as input[1] of LUT0. Additionally, the output of LUT0 will be routed to the PLU_OUT0 pad. This configuration to set up both input sources, route the output source and write the truth table register to result in an AND gate can be achieved with the following code:   /* Select input pin PLU_IN0 as LUT Input 0 (Input MUX0) for LUT0 on module PLU0 */ PLU_SetLutInputSource(PLU0, kPLU_LUT_0, kPLU_LUT_IN_0, kPLU_LUT_IN_SRC_PLU_IN_0); /* Select input pin PLU_IN1 as LUT Input 1 (Input MUX1) for LUT0 on module PLU0 */ PLU_SetLutInputSource(PLU0, kPLU_LUT_0, kPLU_LUT_IN_1, kPLU_LUT_IN_SRC_PLU_IN_1); /* Set Truth Table 0x08 for LUT element 0 on module PLU0 */ PLU_SetLutTruthTable(PLU0, kPLU_LUT_0, 0x08); // This will result in an AND gate /* Select LUT0 output as driver for PLU_OUT0 pin on module PLU0 */ PLU_SetOutputSource(PLU0, kPLU_OUTPUT_0, kPLU_OUT_SRC_LUT_0);   Conclusion The PLU module of the MCX N is modest when it comes to the complexity of the inner components as it is only made up from a series of look-up tables, multiplexers and flip flops. In spite of that, more elaborate and powerful logic networks can be achieved from those basic elements, providing on-chip solutions to many essential digital circuits and avoiding the need of external components for these digital applications. Not only that, but its interruption and wake up capabilities also enable the PLU to be a simple but effective addition to many low power applications. The PLU’s flexibility and built-in features enable this module to be a very effective addition to the MCX N series of MCUs that should not be overlooked. More information as well as example codes for combinational, sequential, and low-power applications can be found on the full article on Application Code Hub.

Ⅰ、Introduction MCXA153 supports Read Out Protection (ROP) to protect code from reading from the device internal flash. This read out protection is a mechanism that allows user to enable different levels of protection in the system. This article explains in detail the configuration of the four ROP levels as well as the relationships between the different levels and the corresponding life cycles. Ⅱ、Four levels of Read Out Protection (ROP) The ROP is controlled by ROP_STATE bits, It is a 32-bit field stored in IFR0. It can be programmed by customer. Below is an introduction to the four ROP levels： 1.ROP_LEVEL0 ROP_STATE = 0xFFFF_FFFF (erased FLASH value), No ROP. Default for blank state. 2.ROP_LEVEL1 ROP_STATE = 0x0000_0003 Debug is disabled and unlocked, however it can be modified by customer, only limited debug mailbox commands are available. 3 .ROP_LEVEL2 ROP_STATE = 0x0000_0001 Debug is disabled and locked, it cannot be modified by customer, only limited debug mailbox commands are available. 4.ROP_LEVEL3 ROP_STATE = 0x0000_0000 Debug is disabled and locked, it cannot be modified by customer, no debug mailbox commands are available NOTE：Anything else = ROP3-like behavior (Debug disabled/Locked, ISP disabled). When the ROP level is 0, we can change the ROP level to 1, 2, and 3 by modifying the value of ROP_STATE in IFR0.When the ROP level is 1 or 2, we can change the ROP level to 0 through the ISP or DM-AP command. ROP level 3 is a one-way trip, so be careful. Below is a diagram of the relationship between the four levels：   Ⅲ、Life cycle and ROP When the chip is delivered to the customer from NXP, the life cycle is “NXP Provisioned”, we can also call it “OEM Open”, ”OEM Field return”, “NXP Field Return”. Because at this point, the chip is completely blank, and ISP and debugging functions are allowed. Of course, the ROP level at this point is 0. In this lifecycle, customers can develop and debug. During customer production, customers can impose certain restrictions on ISP and debugging based on their needs through ROP. Customers can choose between ROP level 1 or ROP level 2. The lifecycle at this point is “OEM Closed”. In this lifecycle, when there are some quality issues, customers can use the ISP or DM-AP command to erase the entire chip, or use the DM-AP command “set FA” to transfer the chip life cycle to the initial state, and return it to NXP’s factory for analysis without storing any IP assets. In some scenarios, customers may need to completely disable ISP and debugging functions. In that case, customers can set the ROP level to 3, and the chip’s lifecycle is “OEM No Return”. Please note that at this point, even NXP cannot restore the chip. So once there are some CQC issues, our factory cannot conduct further analysis. Also, we can transfer the chip to a ‘Bricked’ state in any lifecycle. During “Bricked” lifecycle, the chip will not be booted and will become a brick. The following table shows the relationship between life cycle and ROP: Ⅳ. Impact of different ROP levels on SWD and ISP The supported SWD and ISP commands are different at different ROP levels. From ROP0 to ROP3, fewer commands are supported. The following figure shows the commands supported by SWD and ISP at different ROP Levels. ISP commands supported in ROP0-ROP3:   SWD DM-AP commands supported in ROP0-ROP3:   Ⅴ、Configure ROP with SEC tool We can configure ROP through the MCUXpresso Secure Provisioning( SEC) tool. The MCUXpresso Secure Provisioning Tool is a GUI-based application provided to simplify generation and provisioning of bootable executables on NXP MCU devices. Hardware requirements: FRDM-MCXA153 board、Type-C USB cable Software requirements: MCUXpresso Secure Provisioning (MCUXpresso Secure Provisioning v8_b240110 or later.) Configuration steps: Step1. Create a new workspace After opening the software, click File->New Workspace, select "MCX A14x/A15x" -> MCXA153 -> Click "create". Refer to the following figure: Step2. Connection with Target Processor Enter ISP mode：Press and hold SW3(ISP key) => Press and release SW1 (RESET key) => Release SW3 Go to your workspace and click “Target”->Connection, the Connection with Target Processor window is displayed. Here, we make Connection through UART and select port and baud rate. Refer to the following figure: We can click "Test connection" to check whether the connection is successful. If the connection is successful, the result will display "OK". We can also see the life cycle of the current board: OEM Open. Refer to the following figure: Step3.Select Life Cycle Settings ROP Click on the toolbar "OEM Open" According to the requirements, select the appropriate ROP, in this case ROP 2. NOTE: Use ROP 3 with caution. Refer to the following figure: Step4. Build image After completing the above operations, we need to load the .s19 or .hex file generated by MCUXpresso IDE into the Source executable image. After the file is loaded, the start address is automatically identified. If the start address is not 0x00000000, you cannot "built image". Then click on "built image". Refer to the following figure: After completing the built image, "SUCCECC: built image" will be displayed. Click "close". Refer to the following figure: Step5. Write image We can see that the required .bin file has been generated automatically in "write image", or we can import the corresponding .bin file we wrote by "import". The Image path file will be automatically loaded. Clicking "write image" will pop up to confirm, and then click "ok" to run the script automatically. After the file is successfully written, the message "SUCCESS: write image" is displayed. Refer to the following figure: Step6. Check When we complete the configuration of ROP 2, we can check the status of registers through "PFR configuration". The used registers cannot be read out and unknown is displayed, as shown in the following figure: Finally, by pressing the RESET key on the board to exit ISP mode. At this point, the board has entered ROP 2, debug is disabled. The method of entering other ROP levels is the same. So how do we get back to the other ROP levels? ROP 2 state debugging is disabled, even the IDE cannot operate, we can only use ISP command and SWD command to operate. The SEC tool integrates SWD bulk erase command to return to ROP 0. However, we can also use the Blhost software to use ISP command, enter the ISP mode, enter “blhost -p comxx -- flash-erase-all” and return to ROP 0. Next, we'll look at using the SWD bulk erase command. Click on the toolbar "Dbg": The Select Debug Probe window is displayed. Refer to the following figure: Select “Probe: ”and click “erase”. After the erase succeeds, the following message is displayed: Flash mass erase succeeded! So we've successfully returned to ROP 0. Ⅶ、Summary ROP function protects the security of the chip, users can set different levels of ROP according to the requirements of their own applications. Using MCUXpresso Secure Provisionin simplifies the ROP configuration process. Configuring different ROPs requires modifying the status bits of ROP_STAT and ROP_STAT_DP in CMPA. The SEC tool helps us automate this work through a GUI interface.