If you accidentally erase the kickstart or S1L boot loaders on the Embedded Artists LPC3250 board, this procedure can be used to restore them. Note the boot loaders provided in this restoration method might be newer than the versions provided with the Embedded Artists board. The original versions of the boot loaders can also be downloaded from the Embedded Artists 's website when you register your board.   Restoration of the boot loaders on the board require no special hardware (ie, JTAG) and are performed with boot loaders and tools built or included in the LPC32x0 Common Driver Library. However, you will need a PC with a USB port to perform the update procedure.   Restoring the kickstart loader and is a 2-step process. The kickstart loader is restored first and then is restored. The serial loader is used to transfer the application and the burner images (which is used to program the application into NAND FLASH). The LPC32x0 will automatically burn the image into NAND FLASH after it has been downloaded and then provide a status.   Step 1: Download the pre-built boot software and restoration images for the Embedded Artists LPC3250 board from the Resources page. Step 2: Extract the files on a Windows based PC Step 3: Connect a USB cable between the Embedded Artists boards USB serial connector and the PC. Power up the board and install and USB serial drivers if necessary. These drivers are included with the software included with the board. Step 4: Start the Serial loader software (LPC3250_Loader.exe) included in the pre-built boot software package. Step 5: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_kickstart_nand_large_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the kickstart_nand_large_block_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Embedded Artists board.   NOTE: The pre-built binaries may have slightly different names than those listed in steps 5 and 7, depending on the tool used to build the binaries. If the binaries were build with GNU instead of Realview, the 'rvw' field in each name will contain the 'gnu' identified instead. Change the filenames as necessary for you binaries you have.   Step 6: Press the 'Load bin's / Start primary' button on the Serial loader and power on the board. The burner image and the kickstart loader image should transfer to the board and the kickstart loader will then be programmed into NAND FLASH block 0 for boot from the boot ROM by the burner application. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status / Terminal output window of the Serial loader tool, you should see the following output. Waiting for BootID .. 5 .. found! Sending 'A' .. done! Expect 2-nd BootId .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting kickstart into flash... Verifing data......Successfully NAND flash is programmed Successfully     Step 7: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_s1app_nand_large_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the s1l_from_kick_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Embedded Artists board.   Step 8: Press the 'Load bin's / Start primary' button on the Serial loader and reset the board. The burner image and the image should transfer to the board and will then be programmed into NAND FLASH block 1 (and on) for boot from the kickstart loader. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status Terminal output window of the Serial loader tool, you should see the following output.     Waiting for BootID .. 5 .. found! Sending 'A' .. done! Expect 2-nd BootId .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting S1 image into flash... NAND flash is programmed Successfully Step 8: Close the Serial loader and open a terminal program, then reset the board Close the serial loader tool and open a terminal program such as Teraterm. Reset the board and should start. 5 Embedded Artist 3250 Board Build date: May 21 2010 15:12:06 Autoboot in progress, press any key to stop ea3250 >

If you already have S1L on your FDI board, you can update to a previous or later version of S1L with the following procedure. This procedure should not be used to update the kickstart loader in block 0. Step 1: Boot the system to the S1L prompt. Have your updated version of S1L ready. Step 2: At the S1L prompt, type 'load term raw 0x90000000' to start the binary receive in S1L of the new image. On your terminal program, send the S1L file (ie, s1l_from_kick_gnu.bin) to the board as a binary file. Step 3: Once transfer completes, send a break to the board to return to the prompt. In TeraTerm, a break can be sent from the Control menu or by pressing ALT-B. Step 4: Erase the blocks in FLASH used for S1L storage. These are blocks 1 to 24. Be very careful not to erase block 0, which is used for the klickstart loader. The 'erase 1 24' command can be used to erase the blocks. Step 5: Write the loaded S1L image into the S1L area starting at block 1. The S1L image is usually between 56K and 80K, so it will easily fit in 1 block. The command 'write 0x90000000 64 64' will perform this operation. The write command take sectors (not blocks) - sector 64 is where block 1 starts. Step 6: Reset the board to verify the S1L image has been updated. The entire sequence is shown below. You can see a different version of S1L is running by examining the build date of S1L when it boots. FDI3250 Kickstart v1.00 NAND Flash Initialized Running Stage 1 Loader ... Future Designs, Inc. DK-xTS-LPC3250 Board Build date: Sep 10 2010 10:12:22 Autoboot in progress, press any key to stop linux>load term raw 0x90000000 Starting terminal download, send break to stop File loaded successfully linux>erase 1 24 Operation will overwrite bootloader - ok?(y/n): Starting block erase linux>write 0x90000000 64 64 linux>FDI3250 Kickstart v1.00 NAND Flash Initialized Running Stage 1 Loader ... Using default system configuration Future Designs, Inc. DK-xTS-LPC3250 Board Build date: Sep 13 2010 11:20:12 FDI3250

These instructions explain how to use the CodeSourcery GNU tools to build a LWIP project and variant. GNU builds are based on the free CodeSourcery Codebench Lite version. Download the CodeSourcery Lite GNU tools Prior to building the code, you'll need to CodeSourcery GNU tools. These can be download from Mentor Graphics. There are multiple versions of the tools that can be download. Make sure you download the EABI version of the tools with CodeBench. These will be identified similar to "Sourcery CodeBench Lite 2011.09-69 for ARM EABI". The IA32 Windows Installer version was used to generate the projects included in the LWIP packages. After the tools are downloaded, install the tools onto your build machine. Build system and source code modifications Before you can build the projects, a few manual modifications of the source code and a few make related files are needed. lpc177x_8x_emac.c Locate the lpc177x_8x_emac.c and open it for editing. Wrap "#if 0/#endif" clauses around the ENET_IRQHandler function. This will prevent build problems when using the interrupt handler of the same name as part of the LWIP driver. makeconfig Locate the makeconfig file in the makesection folder.If needed, change the path and version number to what's been installed for your host machine. #GNU_INSTALL_ROOT    =C:/Program Files (x86)/CodeSourcery/Sourcery G++ Lite GNU_INSTALL_ROOT    =C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI GNU_VERSION               =4.3.3 make.LPC177x_8x.gnu Locate the make.LPC177x_8x.gnu file in the makesection/LPC177x_8x folder. Make changes as needed to this file for your build. For example, only the changes below were needed. OPTIM            = s CC                 = $(GNUTOOLS)/arm-none-eabi-gcc #CC               = $(GNUTOOLS)/arm-none-eabi-gcc-$(GNU_VERSION) Build procedure Add make tools to system environment path Once the changes have been made, open up a CMD (cmd.exe) shell for your Windows host machine. In the shell, switch to the directory with the example project (ie, ea1788_tcpecho_sa) and then into the gnu subfolder in that project. Run theaddtoolpath.bat script to add the tools path to your shell's environment. C:\dev\git\lwip_work\updated\lpc177x_8x\lwip_lpc\nxpcommon\examples\ea1788\ea1788_tcpecho_sa\gnu>set PATH=..\..\..\..\..\..\makesection\tools;..\..\..\..\..\..\makesection\tools;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files\TortoiseGit\bin;C:\Keil421\ARM\BIN40;C:\Program Files (x86)\doxygen\bin;C:\Program Files (x86)\Enterprise Vault\EVClient\;C:\Program Files (x86)\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI\bin;C:\Program Files (x86)\CodeSourcery\Sourcery G++ Lite\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files\TortoiseGit\bin;C:\Keil421\ARM\BIN40 C:\dev\git\lwip_work\updated\lpc177x_8x\lwip_lpc\nxpcommon\examples\ea1788\ea1788_tcpecho_sa\gnu> Make the image Then type make to build the project. If your project builds without errors, you should get a hex file that can be programmed into the board usng the Flash Magic tool. port/sdram_k4s561632j.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/sdram_mt48lc8m32lfb5.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/sensor_smb380.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/transceiver_sn74lvc16245.o C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../BoardSupport/uda1380.o   lpc_emac.o lpc_emac_zcbuffs.o lpc_phy.o lpc_debug.o sys_arch.o Serial.o lpc177x_8x_systick_arch.o retarget.o ea1788_board.o tcpecho_sa_app.o def.o dhcp.o dns.o init.o mem.o memp.o netif.o pbuf.o raw.o stats.o sys.o tcp.o tcp_in.o tcp_out.o timers.o udp.o autoip.o icmp.o igmp.o inet.o inet_chksum.o ip.o ip_addr.o ip_frag.o etharp.o echo.o  -static -mcpu=cortex-m3 -mthumb -mthumb-interwork -Wl,--start-group  -L'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/lib/gcc/arm-none-eabi/4.3.3/thumb2' -L'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/arm-none-eabi/lib/thumb2' -lc -lg -lstdc++ -lsupc++  -lgcc -lm  -Wl,--end-group   -Xlinker -Map -Xlinker \ea1788_tcpecho_sa.map -Xlinker -T   linker/ldscript_dram_zc_gnu.ld -o ea1788_tcpecho_sa.elf 'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'/arm-none-eabi-objcopy -O ihex  ea1788_tcpecho_sa.elf ea1788_tcpecho_sa.hex 'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'/arm-none-eabi-objcopy -O srec  ea1788_tcpecho_sa.elf ea1788_tcpecho_sa.srec C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mkdir -p GCC\Flash C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.map GCC\Flash\ea1788_tcpecho_sa.map C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.elf GCC\Flash\ea1788_tcpecho_sa.elf C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.hex GCC\Flash\ea1788_tcpecho_sa.hex C:/dev/git/lwip_work/u2/lpc177x_8x/lwip_lpc/nxpcommon/examples/ea1788_tcpecho_sa/gnu/../../../../../makesection/tools/mv -f ea1788_tcpecho_sa.srec GCC\Flash\ea1788_tcpecho_sa.srec 'C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'/arm-none-eabi-size GCC\Flash\ea1788_tcpecho_sa.elf    text    data     bss     dec     hex filename   70376     216 4611064 4681656  476fb8 GCC\Flash\ea1788_tcpecho_sa.elf Once the image has been built, you can use Flash Magic to program the image into internal FLASH using the generated HEX file.

If you accidentally erase the kick start or S1L boot loaders on the Phytec LPC3250 board, this procedure can be used to restore them. Note the boot loaders provided in this restoration method might be newer than the versions provided with the Phytec board. The original versions of the boot loaders can also be downloaded from Phytec's website. Restoration of the boot loaders on the board require no special hardware (ie, JTAG) and are performed with boot loaders and tools built or included in the LPC32x0 Common Driver Library. However, you will need a PC with a serial port to perform the update procedure. Restoring the kick start loader and S1L is a 2-step process. The kick start loader is restored first and then S1L is restored. The serial loader is used to transfer the application and the burner images (which is used to program the application into NAND FLASH). The LPC32x0 will automatically burn the image into NAND FLASH after it has been downloaded and then provide a status. Step 1: Download the pre-built boot software and restoration images for the Resource page. Step 2: Extract the files on a Windows based PC Step 3: Connect a serial cable between the Phytec boards' lower serial connector and the PC Step 4: Start the Serial loader software (LPC3250_Loader.exe) included in the pre-built boot software package. Step 5: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_kickstart_nand_small_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the kickstart_nand_small_block_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Phytec board. NOTE: The pre-built binaries may have slightly different names than those listed in steps 5 and 7, depending on the tool used to build the binaries. If the binaries were build with GNU instead of Realview, the 'rvw' field in each name will contain the 'gnu' identified instead. Change the filenames as necessary for you binaries you have.   Step 6: Press the 'Load bin's / Start primary' button on the Serial loader and power on the board. The burner image and the kickstart loader image should transfer to the board and the kickstart loader will then be programmed into NAND FLASH block 0 for boot from the boot ROM by the burner application. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status / Terminal output window of the Serial loader tool, you should see the following output.   Waiting for BootID? .. þ5 .. found! Sending 'A' .. done! Expect 2-nd BootId? .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting kickstart into flash... Verifing data......Successfully NAND flash is programmed Successfully Step 7: Setup the 'Primary boot (IRAM)' file in the Serial loader to the burner_s1app_nand_small_block_rvw.bin file. Setup the 'Secondary Executable (SDRAM)' file in the Serial loader to the s1l_from_kick_full_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Phytec board.   Step 8: Press the 'Load bin's / Start primary' button on the Serial loader and reset the board. The burner image and the S1L image should transfer to the board and S1L will then be programmed into NAND FLASH block 1 (and on) for boot from the kickstart loader. After the files have transferred, press the 'Enable terminal mode' button to see the program status. In the Status / Terminal output window of the Serial loader tool, you should see the following output.   Waiting for BootID? .. 5 .. found! Sending 'A' .. done! Expect 2-nd BootId? .. 5 .. found! Sending 'U','3'.. done! Expect 'R' .. R .. found! Sending startaddress .. done! Sending size .. done! Sending code .. done! --- Loading Secondary executable --- Wait for 'X' .. X .. found! -- Sending command .. p ..done! Sending startaddress .. done! Sending size .. done! Wait for acceptance from primary boot .. o ..OK! Sending code .. done! Expect final 't' .. t .. found, ---- Secondary Executable loaded. --- --- Enabling terminal mode --- Formatting blocks... Format complete Writting S1 image into flash... NAND flash is programmed Successfully Step 8: Close the Serial loader and open a terminal program, then reset the board Close the serial loader tool and open a terminal program such as Teraterm. Reset the board and S1L should start.   5 Phytec 3250 Board Build date: May 21 2010 12:43:21 PHY3250>

A simple programming API is available that allows custom development of programming algorithms for different memory types such as NOR or NAND FLASH or EEPROM based memory. By mixing programming algorithms and different program images as different steps with the DFUSec tool, a single programming sequence could program all non-volatile memories and memory regions in a single DFUSec programming cycle via USB! This section explains the process of creating a new programming algorithm. Programming algorithm creation process A programming algorithm is an executable program that runs on the target hardware and is download via DFUSec to the board using the LPC18xx/43xx's DFU boot capability. Each programming algorithm has unqiue code for handling the memory it will program. To create a new programming algorithm requires the following steps: Download the DFUSec programming API examples (here). This provides the DFU streaming code that calls the programming API, several reference drivers (emulated IRAM, internal FLASH, SPI FLASH), and several projects to build an executable programming algorithm image. The examples require the LPC18xx CMSIS library attahced below. Although the example builds inside the LPC18xx CMSIS source tree, the generated binaries should executed on the LPC43xx device (as it's using the M3 instruction set) with common peripherals. Write a new driver for the new memory type with the supported API functions Compile the driver with the DFU streaming code to get a programming algorithm executable in binary form Using the DFUSec RAW/HDR mode tab, generate a binary with a header attached to it Programming API functions The dfusec_programming_api.h header file contains the function prototypes and shared data structures that must be developed for the DFU streamer code driver. The driver requires one global function that initializes the non-volatile memory interface and device and prepares the data structure that defines the non-volatile's devices memory regions and callback functions. The structure provides five additional functions (via indirect calls) that handle region erase, full erase, program, verify, and address check.Not all of these functions are required to do something. Programming API - algo_flash_init() function The first function that needs to be provided is the algo_flash_init() function. This function is called by the DFU streamer to initialize the non-volatile memory device, return the pointer and size of the DFU streaming buffer, and return the FLASH configuration structure and callbacks.The function has the following prototype:/* Initializes device programming capability */ DFUPROG_REGION_T *algo_flash_init(void **buffer, int32_t *buffer_size); style="color:rgb(100, 100, 100);font-family:Arial, sans-serif;font-size:12px" The buffer size must be a multiple of 64 bytes (DFU max packet size) typedef struct {     int32_t num_regions; /* Number of program regions on the device */     /* Buffer should be 32-bit aligned */     void *buffer;     /* This must be a minimum of 64 bytes or DFU max packet size and must        be a factor (1x, 2x, 3x, etc.) of max packets size */     uint32_t buffer_size;     const PROGALGOS_T *pprogalgos;     const DFUPROG_REGZONE_T *pregions; /* Address and region size array */ } DFUPROG_REGION_T; /* Function pointer types and function array */ typedef int32_t (* progalgo_flash_erase_region) (uint32_t, uint32_t); typedef int32_t (* progalgo_flash_erase_all) (void); typedef int32_t (* progalgo_flash_write) (uint32_t, uint32_t); typedef int32_t (* progalgo_flash_verify) (uint32_t, uint32_t, uint32_t); typedef int32_t (* progalgo_verify_range) (uint32_t, uint32_t); typedef struct {     progalgo_flash_erase_region erase_region;     progalgo_flash_erase_all    erase_all;     progalgo_flash_write        write;     progalgo_flash_verify       verify;     progalgo_verify_range       vrange; } PROGALGOS_T; Shared DFU streamer programming info structure /* Programming info received from DFUSec for a specific step */ #define DFUPROG_VALIDVAL 0xDB001843 typedef struct {     int32_t stepnum;         /* Step number, 0 - 9 */     uint32_t imagesize;      /* Size of image in bytes */     uint32_t address;        /* Address to start programming of image or start of erase */     int32_t regionsize;      /* Size of region to erase for 'eraseregion' */     int32_t eraseregion;     /* Erase region flag, will erase region if !0 */     int32_t erasefulldevice; /* Erase full device if !0 */     int32_t parameter;       /* Optional parameter value */     uint32_t validatetag;    /* Must be value of DFUPROG_VALIDVAL */ } DFUSEC_PROGINFO_T; extern DFUSEC_PROGINFO_T dfusec_proginfo; Building the programming algorithm The currently available pre-configured projects for building the programming algorithms are only available for the Keil uVision4 toolchain. To build the project with your driver, open one of the pre-configured projects and replace the file under the DFUSec_programming_algorithm group with the new driver. Click build to compile and link the image. The final result of the build cycle will be a binary image with a .bin extension. Adding UART log output support to the programming algorithm LPC18xx/43xx DFUSec programming API tool Build date: Jul 19 2012:15:03:24 Initializing USB interface Initializing DFU Connecting USB stepnum         = 0 imagesize       = 4724 address         = 10080000 regionsize      = 00004000 eraseregion     = 0 erasefulldevice = 0 validatetag     = db001843 Program cycle complete Appending a header to the programming algorithm binary The final step in preparing the programming algorithm for use with the DFUSec tool is to append a boot header to the binary file generated in the previous step. The DFUSec tool cannot boot the binary directly and requires this header. To generate the header, run the DFUSec tool and click on the HDR/RAW modes tab. For the binary box, select the .bin file to create the header for. Then click the "Generate binary file with header" button to generate a new file. A new file will be created in the same directory as the .bin file with the .hdr extension. This .hdr file is you programming algorithm file that should be used with the Algo box in the Program mode tab with DFUSec.

    The LPC11U6x USB to I2C Bridge project utilizes NXP’s USB Serial I/O (LPCUSBSIO) library to demonstrate the I2C sensor control via the full speed USB functionality on LPC11U6x. The project is implemented on the LPC11U6x LPCXpresso board as well as the LPC11U68 Development Board. The firmware packages include USB HID and I2C drivers and are implemented with Keil, IAR and LPCXpresso three IDEs . All packages are built with LPCOpen structure and are available for download from the links provided at the end of this project page. Within the Keil and IAR Manley board packages there are two demos. The LCD demo will require a Keil/IAR official license to build. In addition, to use the LPCXpresso IDE, user need to use the latest LPCXpresso IDE 6.1.4 avaialble from down load at the link below. Instructions on how to build and use the LPCXpresso package can be found from this link. A windows based GUI is provided to demonstrate the functionality of the USB to I2C bridging functionality utilizing the NXP LPCUSBSIO library. The LPC11U68 DevelopmentBoard and LPCXpresso board enumerate as HID devices on the windows PC. The GUI program talks to LPC11U6x through USB HID device class protocol. Upon start, this window side application automatically scans the I2C devices found on the hardware. On the Manley board, this GUI can monitor the on board I2C temperature sensor. When demonstrating this implementation with the LPC11U6x LPCXpresso board, the EA LPCXpresso base board should be connected for richer user experience. When the EA LPCXpresso base board exists, this GUI application can control the LEDs on the LPCXpresso base board via the I2C Expander PCA9532 on board. The binary of the GUI application is available for download at the end of this project page. NXP will publish the source code of this application in the next couple weeks. Original Attachment has been moved to: usbsio_v2_06_lpcxpresso_nxp_lpcxpresso_11u68.zip Original Attachment has been moved to: usbsio_v2_06_keil_iar_nxp_lpcxpresso_11u68.zip Original Attachment has been moved to: LPC11U6x_USB_I2C_Bridge_GUI.zip Original Attachment has been moved to: usbsio_v2_06_keil_iar_manley_11u68.zip Original Attachment has been moved to: usbsio_v2_06_lpcxpresso_manley_11u68.zip

Introduction The LPC USB serial I/O (LPCUSBSIO) is a generic API provided to PC applications programmer to develop applications to communicate with serial I/O devices connected to LPC micro-controller. LPCUSBIO library converts all API calls into USB messages which are transferred to LPC micro-controller, which in turn communicates with serial devices using I2C, SPI and GPIO interfaces. To make the USB device install free on host systems LPCUSBSIO uses USB-HID class as transport mechanism. HID class is natively supported by most commercially available host operating systems.    Architecture The framework uses HID_API , a multi-platform library which allows an application to interface with USB HID-Class devices on Windows, Linux, and Mac OS X. The following figure shows how the components of the system are typically organized. The PC/Host may be desktop/laptop machine or an embedded system. The LPC micro-controller and the I2C device would usually be on the same PCB. The LPC micro-controller will operate in I2C master mode. All the I2C device connected to the bus should have unique address on bus. I2C devices that support configurable addresses will have pins which can be hard-wired to give a device an appropriate address; this information may be found in the datasheet of the I2C device chip. LPCUSBSIO Architecture

The LPC-Link 2 Configuration Tool (LCT) has been replaced by LPCScrypt and should no longer be used. This content is provided for informational purposes only. The LPC-Link 2 Configuration Tool (LCT) is a Windows tool that installs the CMSIS-DAP/VCOM/LPCSIO or JLINK firmware on LPCXpresso V2/V3 and LPC-Link 2 boards. This package provides the Link Configuration Tool, all necessary Windows drivers, a User Manual, and the source and project files to rebuild the programming algorithm firmware used by the LCT. The V2 version provides expanded capability for LPCXpresso V2/V3 boards with improvements to CMSIS-DAP, a UART bridge connected to the target processor (LPCXpresso V2/V3 boards only), and a LPCSIO bridge that provides communication to I2C and SPI slave devices on LPCXpresso V3 boards. For LPC-Link 2 boards, an updated version of CMSIS-DAP provides faster programming and more stable operation. This version also adds support for J-Link - please see SEGGER's website for more information: for lpc-link2 boardsand for LPCXpresso V2/V3 boards. Features Firmware included in this package: LPCXpresso V2/V3 boards: CMSIS-DAP debugger + VCOM (UART bridge connected to target processor) + LPCSIO bridge (I2C + SPI + GPIO bridge connected to target processor) LPC-Link 2 boards: CMSIS-DAP firmware LPC-Link 2 and LPCXpresso V2 and V3 boards: J-Link firmware Documentation Userguide: LPC-Link 2 Configuration tool - User Guide (REV 1.0) Supporting information: LPC-Link 2 Configuration Tool - Release Note (REV 0) Downloads Software: LCT Installer 1 (REV 2.02) New

NXP Smartphone Quick-Jack Solution Transform the audio jack of a smartphone into a multi-purpose, self-powered data port. This hardware/software platform, designed for use with iPhone® and Android® smartphones, is the simplest way to design compact sensor peripherals that use the phone’s audio jack for data and power. Whether you are a Smartphone App Developer looking for an easy way to add cool context-aware features to your next app or an End product designer looking for simple way to Monitor or control sensors, the new NXP Smarphone Quick-Jack solution will make it easy to connect external devices to smartphones for self-powered data communications. It gives smartphones app developers an easy way to add context-aware app features, input user or environment data, or connect peripherals and provides end-product designers instant access to smartphones’ convenience, appealing UI, and cloud connectivity, with unmatched simplicity for endless applications. Compatibility The current version of the OM13069 Quick-Jack solution has been tested with the following devices: • iOS: iPhone 4, iPhone 4S, iPhone 5, iPhone 5S • Android: Samsung Galaxy S3. It is not guaranteed to work with other devices. Quick-Jack Solution quick start guide and Application Note: The NXP Smartphone Quick-Jack Solution quick start guide can be found at:  http://www.nxp.com/documents/user_manual/UM10815.pdf The Chinese version of the NXP Smartphone Quick-Jack Solution quick start guide can be found at:  http://www.nxp.com/documents/user_manual/UM10815_ZH.pdf The NXP Smartphone Quick-Jack Solution Application Note can be found at:  http://www.nxp.com/documents/application_note/AN11552.pdf The Chinese version of the NXP Smartphone Quick-Jack Solution Application Note can be found at: http://www.nxp.com/documents/application_note/AN11552_ZH.pdf Useful Links For more information on the solution kit and how to order it please visit: http://www.nxp.com/demoboard/OM13069.html For more information on the LPC812 Series please visit: http://www.nxp.com/products/microcontrollers/cortex_m0_m0/lpc800/ For the LPC800 Promotional web page please visit: http://www.nxp.com/campaigns/lpc800-go/ To Download your iPhone App into your Phone, use this link: https://itunes.apple.com/us/app/nxp-quick-jack/id854875264?mt=8 To Download your Android App into your Phone, use this link: https://play.google.com/store/apps/details?id=com.nxp.HijackU To Download the leaflet use this link; http://www.nxp.com/documents/leaflet/75017571.pdf  To see the Hi-Jack project web page from the University of Michigan, use this link; http://web.eecs.umich.edu/~prabal/projects/hijack/ To Download the Press Release use this link; http://www.nxp.com/news/press-releases/2014/05/nxp-unveils-smartphone-quick-jack-solution-transforming-audio-jack-into-multi-purpose-self-powered-data-port.html Note Concerning iOS Source Code By rule, iOS source code is not allowed to be distributed on public web sites.  Please contact NXP at our technical support centerto inquire about iOS source.

These examples show several possible uses for the DFUSec programming feature of the tool. LPC1857 single bootable image programmed in internal FLASH This example shows how to burn a snigle bootanle image into internal FLASH. When booting from internal FLASH, the boot address is 0x1A000000. The image has been linked for this address with data in IRAM. This operation requires a simple 1-step programming sequence. The operation will do the following: Erase just the area of internal FLASH dedicated to the bootable image (we'll use 64K starting at address 0x1A000000) Program the image (up to 64K) into address 0x1A000000 DFUSec configuration The image below shows the DFUSec configuration and a successful program cycle. This uses the LPC18xx/43xx internal FLASH programming algorithm. The 2nd file box contains the path/filename to the image file to program. The image file already includes the checksum and CRP. The address (0x1A000000) and size (0x10000) designate the erase region, program address, and maximum program size. Since the 'Erase region before programming' option is selected, the FLASH at address 0x1A000000-0x1A00FFFF will be erased prior to programming. After rease completes, the image will be sent to the board (in small chunks) and programmed into FLASH. If the image exceeds 64K (specified by the same size parameter used for region erase), an error will be generated, even if FLASH extended beyond the 64K limit specified. LPC1857 multiple images in internal FLASH This example shows how to burn multiple images into different location in internal FLASH. Although this example is shown using the Keil MCB1857 board, the example can easily be used to separately program (or update) M0 and M4 images into different location in internal FLASH for the LPC4350 dual core device! Either image can be updated later without erasing the entire device or the other image. This operation requires a 2-step programming sequence. Step 1 will erase the entire device and program image_1 into bank A. Step 2 will program image_2 into bank B. Optionally, with step 2, we can program image_2 into another area of bank A if needed. Step 1 DFUSec configuration The internal FLASH programming algorithm is used with the image_1.bin program file. Step 1 will erase the entire device (both bank A and B) before programming. Then image_1 will be placed at the bootup address (0x1A000000). We'll limit the image size to a maximum of 128K for programming. The configuration is show below: Step 2 DFUSec configuration The internal FLASH programming algorithm is used with the image_2.bin program file. Step 2 will place image_2 at the 2nd bank address (0x1B000000). We'll limit the image size to a maximum of 16K for programming. The configuration is show below: Screenshot of the completed DFUSec 2-step program operation

The LPC1500 microcontroller series are optimized for fast, easy, and high-precision motor control. Incorporating all the features required for high-accuracy sensored and sensorless motor control, the LPC1500 enables simultaneous control of multiple motors in highly flexible configurations. Based on the ARM® Cortex™-M3 processor, the LPC1500 series has two 12-bit, 12-channel, 2 Msps ADCs and an on-chip quadrature encoder interface (QEI) to enable highly accurate control of both sensored and sensorless motor combinations. With four on-chip comparators enable fast-response over-current/voltage monitoring and protection and four flexible SCTimer/PWM timers to provide up to 28 PWM channels in a tightly coupled analog and timing subsystem with minimal load on the CPU, the LPC1500 are ideal for use with a wide range of brushless DC (BLDC) motors, permanent-magnet synchronous motors (PMSM), and AC induction motors (ACIM) commonly found in products such as large home appliances, HVAC, industrial pumps and generators, and more. They are also well suited for industrial applications requiring high-precision data sampling and real-time control, such as digital power and instrumentation. The LPC1500 microcontrollers are fully supported by the LPC software ecosystem and an extensive collection of tools, drivers and middleware. With ultra-efficient motor control firmware, easy-to-use GUI-based tuning tools, and two new motor control solution kits, NXP's LPC1500 microcontrollers simplify evaluation and development of motor control applications, without requiring deep motor control experience.   Features of LPC1500 : 72 MHz ARM Cortex-M3 processor Upto 256 kB on-chip flash programming memory Upto 36 kB SRAM 4kB EEPROM Memory Protection Unit(MPU) USB/SPI/I2C drivers DMA drivers C-CAN drivers Four SCTimers/PWM Two 12-bit ADC and One 12-bit DAC   Brushless DC Motor (BLDC) Solution The LPC1549 Brushless DC motor control solution helps you get started with motor control protoyping immediately.  It utilizes the SCTimer/PWM available on the LPC1549 MCU for the motor operation.The SCTimer/PWM combines the features of a timer and a state machine making possible to develop sophisticated solutions in the digital control field. The project is implemented on the LPC1549 BLDC Motor Control Kit, which includes an LPC1549 LPCXpresso board. The joystick present on the motor control kit is used to control the speed and direction of the motor. It is possible to define a more complex sequence of events, having the SCTimer/PWM evolve autonomously through the state machine over time, in response to the time-based or I/O defined events. This typically implies that less CPU interventions are needed, since the SCTimer/PWM is able to handle most of the control sequence in hardware. Using the SCTimer/PWM also reduces the code size. The firmware package contains the project implemented in Keil IDE. The package also contains an application note which decribes the motor control operation using the SCTimer/PWM in detail.     Permanent-Magnet Synchronous Motor (PMSM) Control Solution The LPC1549 PMSM motor control solution provides a Field-Oriented Control (FOC) example to get you started with motor control prototyping. This example utilizes the QEI feature on the LPC1500 to monitor the position and velocity of the motor for both sensor and sensorless modes. The additional advanced features of the LPC1500 including the SCTimer/PWM and high speed ADC ensures easy and reliable control of time critical peripherals, and a mechanism for sychronization of the ADC's with the PWM for exact timing of the sample moments. FOC is a more advanced approach where each phase is driven sinusoidally and permanently powered so the magnetic field inside the motor is regulated to the most optimal value.  The project is implemented on the LPC1549 PMSM Motor Control Kit, which includes an LPC1549 LPCXpresso board. The firmware package contains the project implemented in IAR IDE. The package also contains an application note which decribes the motor control operation using the QEI and SCTimer/PWM in detail. This solution also comes with a GUI interface, which is developed to tune motor parameters in FOC firmware.                                           FOC Control Block Diagram                                                      GUI Interface   Motor Control Solution Overview Video Useful Links : LPC1500 MCU Product Pages LPC1549 LPCXpresso Board LPC1549 BLDC Motor Control Kit  (OM13068) LPC1549 PMSM Motor Control Kit (OM13067) LPC1500 Datasheet LPC1500 User Manual

To use SWIM in Linux, SWIM must have direct access to the frame buffer memory in Linux. This can be done by accessing the /dev/fb device and mapping virtual memory to the device that SWMO will be used. The basic code snippet below shows how to do it. #define XSIZE 240 #define YSIZE 320 int fbdev; Uint16 *fb; /* Assumes frame buffer is 16-bit data */ /* Open frame buffer device */ fbdev = open("/dev/fb0", O_RDWR); /* Get mmap'd pointer to frame buffer */ fb = (Uint16 *) mmap(0, XSIZE * YSIZE * sizeof(Uint16), PROT_WRITE, MAP_SHARED, fbdev, 0); After this code is executed, the variable 'fb' will point to a usable frame buffer in memory that can be directly written to and read from in the Linux application. The next step is to initialize the SWIM window for the size of the display. SWIM_WINDOW_T win1; /* Create window with black background and no border */ if (swim_window_open(&win1, XSIZE, YSIZE, fb, 0, 0, XSIZE - 1, YSIZE - 1, 0, WHITE, BLACK, WHITE) == 0) { fprintf(stderr, "Error opening chat window\n"); close (fbdev); return -1; } /* select the font to use */ swim_set_font(&win1, (FONT_T *)&font_winfreesys14x16 ); /* set the pen color to use */ swim_set_pen_color(&win1, WHITE); A title bar can be easily added to the window. swim_set_title(&s1, "SWIM window demo", LIGHTGRAY); All objects in the window are drawn using logical window coordinates. Positions for pixels/lines and text are independent of each other, so you can draw some text, then do a line, and then if you draw text again, it will place the next where the previous text output ended before the line was drawn. /* Draw a simple box */ swim_put_line(&win1, 10, 10, 50, 10); swim_put_line(&win1, 50, 10, 50, 50); swim_put_line(&win1, 50, 50, 10, 50); swim_put_line(&win1, 10, 50, 10, 10); With Linux, finish the application by closing the frame buffer device. close (fbdev); The SWIM library and application note can be found here.

NXP Semiconductors and OnChip Technologies have partnered to provide USBHostLite software for our LPC1000, LPC2000, and LPC3000 families of microcontrollers with USB host capability. These include members of the LPC17xx series, the LPC23xx series, the LPC24xx series, the LPC29xx series, the LPC31xx series, and the LPC32xx series of microcontrollers. USBHostLite is a stripped-down USB host stack that includes only USB mass storage class support with the bare minimum code to run in an OS-less environment. USBHostLite provides a simple solution for accessing the files on USB mass storage devices such as USB Pen Drives, USB Hard Disk Drives, etc., connected to the USB Host port. Features The USBHostLite supports the following features: Runs without any operating system Contains small memory footprint Source code is written in ANSI C and is independent of IDE Supports control and bulk transfers Supports FAT16 file system Simple File APIs allow file read and write operations Well structured and easily understandable source code Limitations The complimentary USBHostLite software from NXP has following limitations: USBHostLite is currently only ported to and tested on Embedded Artists' LPC2468 OEM board and Keil's MCB1760 board. Classes other than the mass storage are not supported. The mass storage interface must be present in the first configuration. Max Logical Unit Number (LUN) greater than zero not supported. File systems other than FAT16 are not supported. Long filenames are not supported. Files located in folders other than root directory cannot be accesed. The buffer size used in the application must not exceed 4KB. Note: This application note describes the USBHostLite stack in general and its application on the Embedded Artists LPC2468 OEM board in particular. Software USBHostLite for LPC source code is free to NXP customers for unlimited use with NXP LPC2000 and LPC3000 families of microcontrollers only. By downloading or using the USBHostLite software, you agree to use it solely with these NXP microcontrollers.USBHostLite stack ported to the LPC293x devices on the Hitex LPC2939 board: USBHostLite for LPC293x VBeta 0.01 (Jul 28, 2009) - Attached USBHostLite stack ported to the LPC2468 device on the Embedded Artists LPC2468 OEM board: USBHostLite for LPC23xx/LPC24xx V1.00 (Jan 4, 2010) USBHostLite stack ported to the LPC1768 device on the Keil MCB1760 evaluation board: USBHostLite for LPC17xx VBeta 0.01 (Jul 14, 2009) - Attached For customer applications requiring full featured and production quality embedded USB stacks, OnChip Technologies LLC provides embedded USB Host/Device/OTG stacks that are fully compliant with the USB specifications and offers great degree of stability and configurability. More Information Disclaimer This software is provided AS-IS by NXP Semiconductors. NXP Semiconductors does not support or warrant the software contained herein for any purpose other than for informational use. Please contact OnChip Technologies LLC for further assistance including support options and other embedded USB host/device/OTG stacks. For Further Assistance OnChip Technologies LLC Other Professional USB Host Stack Solutions for the LPC3000, LPC2000, and LPC1000 families CMX Systems CMX-USB Host HCC Embedded USB (EUSB) HostLite Stack Micrium μC/USB Host Micro Digital smxUSBH Quadros RTXCusb Software Thesycon Embedded USB Host Stack

The LPC247x microcontrollers have integrated LCD controllers. These microcontrollers support Super-Twisted Nematic (STN) and Thin-Film Transistor (TFT) graphic display panels up to 1024 x 768 pixels, from monochrome up to 24-bit true-color, and with hardware cursor support. This capability is ideal for point-of-sale, industrial, and medical/diagnostic applications. Further, the LCD controller supports Windows CE data formats. Below are LPC247x-based design examples for a selection of common LCD daughter cards. The designs use an LPC247x Validation Board to carry LPC247x-related signals to the LCD daughter card. Each daughter card provides connectors to the universal LCD connector on the LPC247x Validation Board. Also included are LPC247x configuration codes (IAR EWARM), schematics, gerber files, and BOM's for each LCD module. LCD Technology Color Depth Resolution Manufacturer Model STN 4-bit B/W QVGA (320x240) Optrex DMF50840 TFT 18-bit WVGA (800x480) Hantronix HDA700L TFT 24-bit QVGA (320x240) Innolux PT035TN01V6 ADTFT 24-bit TFT QVGA (240x320) Sharp LQ035Q7DB03 Block Diagram Products Below are recommended microcontrollers for use in implementing this design to a system. Comparison Table Product Flash SRAM External Bus 10/100 Ethernet USB 2.0 CAN LCD Controller SD/MMC Package(s) LPC2470 0KB 98KB Full 32-Bit 1 1 2 Y 1 LQFP-208 TFBGA-208 LPC2478 512KB 98KB Full 32-Bit 1 1 2 Y 1 LQFP-208 TFBGA-208 LCD Daughter Cards Optrex LCD Board Datasheet Optrex LCD Board Schematics Optrex LCD Board Example Code Optrex LCD Board Gerber Files Optrex LCD Board Bill of Materials Click here to download Hantronix files (attached) Hantronix LCD Board Datasheet Hantronix LCD Board Schematics Hantronix LCD Board Example Code Hantronix LCD Board Gerber Files Hantronix LCD Board Bill of Materials Click here to download Innolux files (attached) Innolux LCD Board Datasheet Innolux LCD Board Schematics Innolux LCD Board Example Code Innolux LCD Board Gerber Files Innolux LCD Board Bill of Materials Click here to download Sharp files (attached) Sharp LCD Board Datasheet Sharp LCD Board Schematics Sharp LCD Board Example Code Sharp LCD Board Gerber Files Sharp LCD Board Bill of Materials More Information Click here to download LPC247x Validation Board (attached) LPC247x Validation Board Schematics LPC247x Validation Board Gerber Files LPC247x Validation Board Bill of Materials

NicheLite for LPC by InterNiche is a variant of its NicheLite™ product, a full-featured TCP/IP stack optimized for embedded systems, requiring as little as 12 KB of code. An RFC compliant implementation of the TCP/IP protocol suite, NicheLite for LPC includes ANSI C sources for a comprehensive subset of the TCP/IP family of protocols, a "Mini" Sockets API, and a highly effective system optimization and tuning tool. NicheLite for LPC's IP layer can support one hardware interface and is fully instrumented for MIB-II access by SNMP agents. MIB-II tables include: Interfaces, IP, ICMP, TCP and UDP information. Packet data, including headers, are in contiguous buffers to simplify memory management and avoid data copies. Macros to protect critical sections of code are used sparingly to improve throughput and reduce memory requirements. The tunable parameters such as MSS (Maximum Segment Size) and the TCP window size can be left to the runtime logic or may be customized for your application. NicheLite for LPC supports the following protocols: Address Resolution Protocol (ARP) Internet Protocol (IP) Internet Control Message Protocol (ICMP) User Datagram Protocol (UDP) Transmission Control Protocol (TCP) Dynamic Host Configuration Protocol (DHCP) Client Domain Name System (DNS) Client Bootstrap Protocol (BOOTP) Trivial File Transfer Protocol (TFTP) NicheLite for LPC Leaflet (attached) Software Obtaining the Software NicheLite for LPC source code is free to NXP customers for unlimited use with NXP LPC1000, LPC2000, and LPC3000 families of microcontrollers only.Obtaining and using NicheLite for LPC is conditional upon accepting a detailed Software License Agreement (SLA). Please download and carefully read the SLA if you have not done so already: Revision History for NicheLite V1.02 (Jul 17, 2007) (attached) Contents The NicheLite for LPC software package includes: NicheTask™ cooperative multi-tasking scheduler TCP supporting InterNiche's Light Weight API with a Zero-Copy option IPv4 without fragmentation/reassembly ARP ICMP Ping TFTP NicheTool™ NicheFile VFS Mini-Sockets API Single Ethernet interface with device drivers optimized for the LPC17xx, LPC23xx/LPC24xx, and LPC32x0 TFTP client TFTP server Example applications (TFTP client, TFTP server, HTTP listener) NicheLite Reference Manual (not for redistribution) HTML-Formatted User's Guide (intended for distribution to end customers) Clearly written, comment-rich ANSI-"C" source code A header file, required at compile time, articulates the details of the source license which prohibits the end customer from distributing the source for NicheLite for LPC. End-Customer Options and Upgrades Available options and upgrades from InterNiche to NXP customers of NicheLite for LPC include: Technical Support Professional Services HTTP Server PPP SNMP v1, v2c, v3 SMTP Client (Email Alerter) NicheStack SSL POP3 Client FTP Server and Client Upgrade to Full NicheStack IPv4, IPv6, Dual Products   NicheStack HTTPServer™ (Attached) NicheStack SSL™ (Attached) NicheStack IPv4™ (Attached) Contact InterNiche for Details More Information Cortex-M0 Microcontrollers Cortex-M3 Microcontrollers Cortex-M4 Microcontrollers ARM7 Microcontrollers ARM9 Microcontrollers InterNiche Technologies, Inc. Overview Presentation (Attached) InterNiche Technologies, Inc. NicheTask Open Source OS

This is the uCOSIII port for LPC43XX based hitex board with revision A4. The BSP and the applicaton code for the port is attached below. The tools supported to build the package are: a) Keil uVision. It has been tested with V4.53.0.0 There are three attachments on the page containing i)The BSP,application and the CPU port files. ii)OS port for the core. iii) A png file showing the directory structure of the project. Here is a set of instructions to build and test the port: 1) Unzip the uCOSIII_Port.zip attachment and you should have "EvalBoards" and "uC-CPU" folders.Place them in your convinient folder. 2) Download uCOSIII source from http://micrium.com/page/downloads/download_os-III_source_code 3)You should now have a "Source" folder containing uCOSIII sources. Place this folder in The directory structure should look like the one shown in the attached png file. 4)Now, find the project file at 5)Double click "hitex4350_tcpecho_uCOSIII.uvproj" which opens the project. Go ahead and build the project for the required target. 6) Connect the Target "Hitex board" with J-Link. And Power it ON. You can either power it with USB or external supply. The default project is setup to use JLink. 7) You can download the image to the IRAM or flash depending on the target you have built. 😎 Run the image, you should be able to ping and telnet it.( This project uses static IP, so change your IP according to your need in the main.c file before building the image)

To build a project for Keil, select the uvproj file for the example you want to build and deploy. The project will open up in the Keil uVision4 IDE. For the project, select the build variant you want to build. Press F7 to start the build. The image can be programmed into the board's internal FLASH (if it's a FLASH image) using the Flash menu and selecting Download. Optionally, you can download and debug the program using the Debug menu and selecting "Start/stop debug session". Note you need a Keil ULINK JTAG/SWD debugger to debug or download code. If you get an error attempting to program FLASH, check that the FLASH algorithm selected for the device is correct by selecting the FLASH menu and then selecting the Settings box. On the Flash Target driver setup display, select the LPC17xx IAP 256K Flash algorithm for programming. If a debugger isn't available, you can use Flash Magic with the created hex file to burn the image into the board. Before attempting to run Flash Magic, make sure the LPC17xx device is in ISP mode by holding down the SW6 while pressing and releasing the reset button.

To build a project for IAR, select the Workspace file (eww) file for the example you want to build and deploy. The project will open up in the IAR EWARM IDE. For the project, select the build variant you want to build. Press F7 to build the selected project. Each project will generate a hex file in addition to the executable. Locate the hex file and use Flash Magic to program it into the board's FLASH. Before programming, make sure the board/devie is in ISP mode by holding down the SW6 button while pressing and releasing the reset button.

A block diagram of the dual core IRAM demo is shown below. Per the diagram, FreeRTOS runs on both cores with memory for the M4 core in the first 64K of IRAM. The M0 core uses the 32K of IRAM at offset 64K. The M0 and M4 signal each other via the core interrupt event mechanism. IRAM at address 0x10080000 is used for the shared memory queue. The tri-color LED is used to indicate lfe on a specific core. The red LED will blink when the M4 core is running, while the blue LED will blink when the M0 core is running. The green LED will blink at a varying rate when the M0 core is running and data has been supplied in the shared memory queue from the M4 core.

This section explains how to use the MLC extractor tool to get an image with interleaved MLC data from NAND FLASH. The MET runs on the target hardware, so the image to be extracted must be placed on the hardware first. There are detailed swrites in the CDL on how to do this, so this won't be covered here. The program assumes UART 5 (the LPC32x0 boot UART) is used as the UART interface. The most common code extracted with this is the kickstart loader in block 0. This loaded is used to boot the LPC32x0 from NAND, setup the system, and then bootstrap the secondary loader in NAND blocks 1 and on. This example is shown on the Phytex LPC3250 board, although ti will work similar on other boards. Setup the serial loader tool to load the "mlcextractor.bin" file to the board via the serial port. M<ake sure the ServiceN pin on the LPC3250 is pulled low to enable UART boot mode. Press the "Load bin's/Start primary" button on the serial loader dialog window. Reset the board and the serial loader tool will transfer the MLC extractor to the target board. After the image is loaded, you will see a messaeg displaying the number of blocks and pages per block in NAND. If a message appears that says the NAND device coudn't be found, then the image needs to be rebuilt with the NAND IDs that match the NAND device on the target board. Close the serial load tool and open a terminal program that supports XMODEM transfer (ie, Teraterm). Press the space bar to get the MET menu. Pressing the keys defined by the menu allows you to change the starting block and number of blocks to extract the data for. Once they are selected, press 'd' and then 'y' to start the xmodem transfer. Next, setup the terminal program for an XMODE_cChecksum receive session. Once started, the interleaved data and ECC codes will be read from the NAND device and transferred to the file via XMODEM. This resulting file can be used for NAND programming.