Hello, here Jorge. On this post I will explain how to enable MQS1 on i.MX8ULP. As background about how to setup the environment to build the image using Yocto, please take a look on our i.MX Yocto Project User's Guide: Requirements: i.MX 8ULP EVK. Serial console emulator (Tera Term, Putty, etc.). USB Type-C cable. Micro USB cable. Headphones/speakers. Linux PC. Build done in Linux 6.6.23_2.0.0. i.MX8ULP audio subsystem. i.MX 8ULP extends audio capabilities on i.MX 7ULP by adding dedicated DSP cores for voice trigger and audio processing, enabling lower latency and power efficiency to support variety of audio applications. Some of hardware blocks implemented on 8ULP to support audio use cases are the next: Cadence Fusion F1 DSP processor. Cadence HiFi4 DSP processor. PowerQuad hardware accelerator with fixed and floating + FFT. Digital Microphone interface with support of up-to 8 PDM channels. Up-to 8 independent SAI instances. Up-to 2 Medium Quality Sound (MQS). Sony/Philips Digital interface (SPDIF). As is described before, MQS0 and MQS1 are part of real time domain and application domain respectively. I’m going to focus this post on how to enable MQS1 on application domain. Medium Quality Sound (MQS)  This module is basically generates a PWM from PCM audio data. For the major part of typical audio applications will require an external CODEC to deliver the audio quality but, sometimes where the application does not demand this quality, MQS can provide a medium quality audio via GPIO pin that can directly drive the audio output to a speaker or headphone via inexpensive external amplifier/buffer instead of CODEC. The design of the MQS can be described as follows: Input the PCM audio data (from SAI) into a 16-bit register. Up-sample data to match PWM switching frequency. Perform a simple 2nd order Sigma-Delta smooth on the current data versus previous data. Convert the PCM register into a 6-bit PWM width register and output through a GPIO pin.   How to enable it? By default, our BSP does not enable clock for MQS1. This clock is controlled on CGC1 (AD), specifically on MQS1CLK (Multiplexer to select the audio clock connected to the MQS clock input). So, it is needed to modify imx8ulp-clock.h and clk-imx8ulp.c. Please take a look on patch attached at the end of this post to see the modification in drivers easily. These drivers have the definition/configuration for MQS1_SEL in CGC1 and needs to be added as follows: MQS1_SEL definition needs to be added in imx8ulp-clock.h: #define IMX8ULP_CLK_MQS1_SEL 56 #define IMX8ULP_CLK_CGC1_END 57 MQS1_SEL configuration needs to be added in imx8ulp_clk_cgc1_init of clk-imx8ulp.c: clks[IMX8ULP_CLK_MQS1_SEL] = imx_clk_hw_mux2("mqs1_sel", base + 0x90c, 0, 2, sai45_sels, ARRAY_SIZE(sai45_sels)); Also, it is necessary to configure MQS1 on device tree of i.MX8ULP. Add this in soc: soc@0 of imx8ulp.dtsi: mqs1: mqs@0x29290064 { reg = <0x29290064 0x4>; compatible = "fsl,imx8qm-mqs"; assigned-clocks = <&cgc1 IMX8ULP_CLK_MQS1_SEL>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; clocks = <&cgc1 IMX8ULP_CLK_MQS1_SEL>, <&cgc1 IMX8ULP_CLK_MQS1_SEL>; clock-names = "core", "mclk"; status = "disabled"; }; And create a new device tree, in this case is going to be named imx8ulp-evk-mqs.dts and is as follows: #include "imx8ulp-evk.dts" / { sound-simple-mqs { compatible = "simple-audio-card"; simple-audio-card,name = "imx-simple-mqs"; simple-audio-card,frame-master = <&sndcpu>; simple-audio-card,bitclock-master = <&sndcpu>; simple-audio-card,dai-link@0 { format = "left_j"; sndcpu: cpu { sound-dai = <&sai4>; }; codec { sound-dai = <&mqs1>; }; }; }; }; &cgc1 { assigned-clock-rates = <24576000>; }; &iomuxc1 { pinctrl_mqs1: mqs1grp { fsl,pins = < MX8ULP_PAD_PTF7__MQS1_LEFT 0x43 >; }; }; &mqs1 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mqs1>; status = "okay"; }; &sai4 { #sound-dai-cells = <0>; assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI4_SEL>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; status = "okay"; }; Let’s apply these changes on our BSP, in my case I’m going to create a new layer in Yocto to add these modifications with a patch that can be found at the end on this post, here the steps: Install essential Yocto Project host packages: $ sudo apt install gawk wget git diffstat unzip texinfo gcc build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping python3-git python3-jinja2 python3-subunit zstd liblz4-tool file locales libacl1 Install the “repo” utility: $ mkdir ~/bin $ curl https://storage.googleapis.com/git-repo-downloads/repo > ~/bin/repo $ chmod a+x ~/bin/repo $ export PATH=~/bin:$PATH Set up Git: $ git config --global user.name "Your Name" $ git config --global user.email "Your Email" $ git config –list Download the i.MX Yocto Project Community BSP recipe layers and create build folder: $ mkdir imx-yocto-bsp $ cd imx-yocto-bsp $ repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-scarthgap -m imx-6.6.23-2.0.0.xml $ repo sync $ DISTRO=fsl-imx-wayland MACHINE=imx8ulp-lpddr4-evk source imx-setup-release.sh -b 8ulp_build Create the new layer: $ cd ~/imx-yocto-bsp/sources $ bibake-layers create-layer meta-mqs $ cd meta-mqs conf/layer.conf should be as follows: BBPATH .= ":${LAYERDIR}" BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ ${LAYERDIR}/recipes-*/*/*.bbappend" BBFILE_COLLECTIONS += "meta-mqs" BBFILE_PATTERN_meta-mqs = "^${LAYERDIR}/" BBFILE_PRIORITY_meta-mqs = "6" LAYERSERIES_COMPAT_meta-mqs = "nanbield" Let’s change the recipe: $ sudo rm -r recipes-example $ mkdir -p recipes-kernel/linux/files 0001-8ULP-MQS-Enable.patch should be copied to ~/imx-yocto-bsp/sources/meta-mqs/recipes-kernel/linux/files Add an append (on this case is called “linux-imx_%.bbappend”)to change the recipe with next content: FILESEXTRAPATHS:prepend := "${THISDIR}/files:" SRC_URI += "file:// 0001-8ULP-MQS-Enable.patch " addtask copy_dts after do_unpack before do_prepare_recipe_sysroot do_copy_dts () { if [ -n "${DTS_FILE}" ]; then if [ -f ${DTS_FILE} ]; then echo "do_copy_dts: copying ${DTS_FILE} in ${S}/arch/arm64/boot/dts/freescale" cp ${DTS_FILE} ${S}/arch/arm64/boot/dts/freescale/ fi fi } The next step is add the layer and build the image: $ cd ~/imx-yocto-bsp/8ulp_build $ bitbake-layers add-layer ~/imx-yocto-bsp/sources/meta-mqs Confirm that the layer has been added: $ bitbake-layers show-layers Build the image: $ bitbake imx-image-multimedia i.MX8ULP EVK limitations The i.MX8ULP has the next MQS1 pins available: But, in the EVK board, the mayor part of these pins are used for other functions such as: - Push button: - MIPI DSI:  - Etc… So, take the output signal of MQS1 pins of EVK board is difficult, in this article, I’m going to configure PTF7 only (MQS1_left) for practicality. If you are working with this board and you need to use these pins for MQS function you will need to manipulate the traces and take the required signals. If you are designing a custom board, planning is essential to avoid this issue. Flash the board. One the build has been finished, we will have the necessary files to flash the board and test it. If you are not too familiarized with this process I suggest you take a look on this post. First, put the board in serial download mode changing the boot configuration switches on the board:   The next step is connecting the power cable, micro-USB cable on the debug port and USB-C type cable to USB0 connector on the board. Then, turn-on the board and run the next command in terminal of build directory: uuu -b emmc_all imx-boot-imx8ulpevk-sd.bin-flash_singleboot_m33 imx-image-multimedia-imx8ulpevk.wic Now, power-off the board, change the boot mode to single boot-eMMC and power it on to test it. Test MQS1 in i.MX8ULP. To test MQS1 it is needed to change the device tree we created, we can do it with the next commands in U-boot: u-boot=> setenv fdtfile imx8ulp-evk-mqs.dtb u-boot=> saveenv u-boot=> boot Now we can test MQS1 on i.MX8ULP EVK, let's confirm that the clock is active in MQS module with the next command: $ cat /sys/kernel/debug/clk/clk_summary -n As you can see mqs1_sel is active and running at 24576000 Hz: And the card appears if we run the next command: $ aplay -l To play audio through MQS we can do it as any sound card: $ speaker-test -D sysdefault:CARD=imxsimplemqs -c 2 -f 48000 -F S16_LE -t pink -P 3 The signal should look like this in the pin output: And like this after a filter, for example the filter used in i.MX93 EVK.   With this post we have been able check the general operation of MQS, configure and compile the image with the required changes to enable MQS1 on EVK board and measure the output on the board. There is a considerable limitation on EVK board since we cannot test left and right outputs without intervene the base board, but this can be helpful as a reference to who would like to use this audio output on i.MX8ULP processor. Best regards. References. Yocto Project customization guide - NXP Community How to add a new layer and a new recipe in Yocto - NXP Community Flashing Linux BSP using UUU - NXP.  i.MX8ULP reference manual. Embedded Linux Projects Using Yocto Project Cookbook.

Note, the tools described in this page are deprecated and are no longer maintained.  For the latest maintained i.MX 6/7 series DDR tools, the user can find these here: i.MX 6/7 Series DDR Tool Release Hi All, DDR_Stress_Tester is a software application for fine tuning DDR parameters and verifying DDR performance on i.MX6 boards. It performs write leveling, DQS gating, read/write delay calibration on the target board to match the layout of the board and archive the best DDR performance. In addition, the stress test can help the user to verify the DDR performance on their boards.   The following are the features supported: • Support i.MX6Q, i.MX6D, i.MX6DL, iMX6S, i.MX6SL, and i.MX6SX DDR calibration. • Support DDR3 write leveling, DQS gating, Read/Write Delay auto-calibration. • Support LPDDR2 Read/Write Delay auto-calibration. • Support 16 bits, 32 bits, and 64 bits data bus. • Support fixed-mapping 2-channel LPDDR2. • Support DDR stress test between the frequency 135MHz and 672 MHz   If  USB OTG port is not available on customer board, please use the images in DDR_Stress_Tester_V1.0.3_UART1_for_SDboot&JTAG.zip. The bin files in the packages can be loaded by uboot and elf files are used by JTAG load.  Please note when the image is loaded by u-boot, the DDR is initialized by u-boot (reference flash_header.S).   To run ddr stress test from u-boot, CONFIG_SPLASH_SCREEN must be disabled in u-boot. Because when enter self refresh mode in ddr stress test, DRAM access will be blocked. If splash screen in u-boot is enabled, IPU will continuously access DRAM, so the system will hang up. If you have other DMA access in u-boot, it must be disabled.   If customer uses different RX/TX pin for UART, please contact FAE.   UART1 6DQ 6DL 6SL 6SX TX CSI0_DAT10/ALT3 CSI0_DAT10/ALT3 UART1_TXD/ALT0 GPIO1_IO04/ALT0 RX CSI0_DAT11/ALT3 CSI0_DAT11/ALT3 UART1_RXD/ALT0 GPIO1_IO05/ALT0   The commands to run ddr test in i.MX6Q uboot: U-Boot > fatload mmc 2:1 0x907000 ddr-stress-test-mx6dq.bin U-Boot > go 0x907000     For i.MX6Q/6D 4K interleaved LPDDR2, please use version v1.0.3.1. i.MX6 DDR Stress Test Tool V1.0.3.1 for LPDDR2 4K interleaved mode For i.MX6/i.MX7 DDR Stress Test Tool with GUI interface, please use version V2.x: i.MX6/7 DDR Stress Test Tool V2.10   History V1.0.3:  i.MX6SoloX is supported.

What is CMA   The Contiguous Memory Allocator (CMA) is a framework, which allows setting up a machine-specific configuration for physically-contiguous memory management. Memory for devices is then allocated according to that configuration. The main role of the framework is not to allocate memory, but to parse and manage memory configurations, as well as to act as an in-between between device drivers and pluggable allocators. It is thus not tied to any memory allocation method or strategy.  Various devices on embedded systems have no scatter-getter and/or IO map support and as such require contiguous blocks of memory to operate. They include devices such as cameras, hardware video decoders and encoders, etc. Such devices often require big memory buffers (a full HD frame is, for instance, more then 2 mega pixels large, i.e. more than 6 MB of memory), which makes mechanisms such as kmalloc() ineffective. Some embedded devices impose additional requirements on the buffers, e.g. they can operate only on buffers allocated in particular location/memory bank (if system has more than one memory bank) or buffers aligned to a particular memory boundary. Development of embedded devices have seen a big rise recently (especially in the V4L area) and many such drivers include their own memory allocation code. Most of them use bootmem-based methods. CMA framework is an attempt to unify contiguous memory allocation mechanisms and provide a simple API for device drivers, while staying as customisable and modular as possible.   Why use it in default release   Most of the i.MX SoC does not have IOMMU for specific IP who requires larger contiguous memory for operations, like VPU/GPU/ISI/CSI. Or they have IOMMU, but performance is not that good. In the default i.MX BSP, we still allocate physical contiguous memory for those IP drivers for DMA transfers. In arm64 kernel, the DMA allocation API would allocate memory in a various way which depends on the device configurations (in dts or gfp flags). The below table shows how the DMA allocation API (w/o IOMMU enabled device) works to find a proper way for pages (by order, coherent pool -> CMA -> Buddy -> SWIOTLB): Allocator (by order) Configurations (w/o IOMMU) Comments Mapping Coherent Pool device dma is not coherent GFP flag is not allow blocking By __alloc_from_pool() Already mapped on boot when coherent pool init in VMALLOC CMA device CMA or system CMA is present GFP flag is allow blocking: __GFP_DIRECT_RECLAIM set By cma_alloc() map_vm_area, mapped in VMALLOC Buddy No CMA (device or system) or GFP not allow blocking By __get_free_pages(), which can only allocate from the DMA/normal zone (lowmem), 32bits address spaces Already mapped in the lowmem area by kernel on boot SWIOTLB No contiguous pages from buddy or return buffer area region > device dma_mask By map_single() Already mapped on boot when SWIOTLB init   Also a diagram shows how it works (DMA allocation path):     By default, kernel uses CMA as a backend of DMA buffers allocation for most of the cases. That's why i.MX BSP use CMA in the default release for GPU/VPU/CSI/ISI or other buffers for DMA transfers.   CMA Pros & Cons   Pros Well designed for large contiguous memory allocation even under memory fragment condition. Pages in CMA can be shared by buddy system, not a reserved pool Can be device specific CMA area, only used by this device and share to system Easy to configure it's start addr and size on runtime w/o re-compile kernel Cons Allocation process slow when migration pages needed Easy to be corrupted by system memory allocation. Customer may meet cma_alloc failure when system is out of memory, which would cause bad user experiences when foreground application wants graphic buffers for rendering and RVC wants buffers for CAR reverse. Potential dead lock when cma_alloc() need to migrate some pages, which is still flushing to storage (Some customers already met deadlock when one page is under writeback path by FUSE file system, and cma_alloc wants to migrate it). This is the initial motivation to write this documentation.   Why get rid of CMA   Read cons statement above. The key point is to reserve memory for critical path of allocation like GPU graphic buffers and camera/VPU preview/recording buffers to keep a good user experience from allocation failure which would cause black screen, preview stuck, etc. Also avoid potential dead lock when CMA and FUSE work together.   How to get rid of CMA   To get rid of CMA, the basic idea is to cut off the CMA way in the DMA allocation, turn to coherent pool (atomic pool). Please not that coherent pool can only be used by DMA allocation API, it's not shared to system buddy.   1. Enable coherent pool Add “coherent_pool=<size>” in command line, Coherent pool is actually allocate from system default CMA, so CMA size > coherent_pool. There's no reference for this size, as it's various from system to system and use cases to use cases: The biggest consumer of DMA is GPU, it's usage can be monitored by gmem_info tool. Monitor the gmem_info under the typical use cases, and settle down the GPU required memory. Checking for 2nd consumer of DMA: ISI/Camera, depends on the V4l2 reqbuf size and numbers Checking VPU, depends on the multimedia frameworks Plus alsa snd, USB, fec usage The size must be verified by test to make sure system stable.   2. DMA allocation hack Hack to arch/arm64/mm/dma-mapping.c, remove the gfpflags_allow_blocking check in the __dma_alloc() function: diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 7015d3e..ef30b46 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -147,7 +147,7 @@ static void *__dma_alloc(struct device *dev, size_t size, size = PAGE_ALIGN(size); - if (!coherent && !gfpflags_allow_blocking(flags)) { + if (!coherent) { // && !gfpflags_allow_blocking(flags)) { struct page *page = NULL; void *addr = __alloc_from_pool(size, &page, flags);   3. ION allocator In both Android and Yocto release, ION allocator (android staging driver) is used for VPU buffers. And it default goes into the ION CMA heap. This means ION request for contiguous memory is direct to CMA. To avoid CMA, we can use carveout heap instead of CMA heap in ION:   3.1 Android Enable CARVEOUT heap, disable CMA heap: CONFIG_ION=y CONFIG_ION_SYSTEM_HEAP=y -CONFIG_ION_CMA_HEAP=y +CONFIG_ION_CARVEOUT_HEAP=y +CONFIG_ION_CMA_HEAP=n Adjust the carveout reserved heap base address and size in the dts: / {  reserved-memory {  #address-cells = <2>;  #size-cells = <2>;  ranges;    carveout_region: imx_ion@0 {  compatible = "imx-ion-pool";  reg = <0x0 0xf8000000 0 0x8000000>;  };  }; };   3.2 Linux Kernel - refer to attached patch for i.MX8QM. Almost same as Linux, but ION carveout heap driver need to be patched. Gstreamer - apply below patch to make allocate from carveout: yocto/build-8qm/tmp/work/aarch64-mx8-poky-linux/gstreamer1.0-plugins-base/1.14.4.imx-r0/git: diff --git a/gst-libs/gst/allocators/gstionmemory.c b/gst-libs/gst/allocators/gstionmemory.c index 1218c4a..12e403d 100644 --- a/gst-libs/gst/allocators/gstionmemory.c +++ b/gst-libs/gst/allocators/gstionmemory.c @@ -227,7 +227,8 @@ gst_ion_alloc_alloc (GstAllocator * allocator, gsize size,    }    for (gint i=0; i<heapCnt; i++) { -       if (ihd[i].type == ION_HEAP_TYPE_DMA) { +       if (ihd[i].type == ION_HEAP_TYPE_DMA || +             ihd[i].type == ION_HEAP_TYPE_CARVEOUT) {                heap_mask |= 1 << ihd[i].heap_id;          }    }   References "Aarch64 Linux Kernel memory management" "CMA documentation"

     

Running Zephyr on i.MX9 A55 core brings a high performance, real-time (short interrupt, scheduler latency, etc.) OS experiences as well as the fast boot, small memory footprint features. This article provide all the information on how to run the Zephyr v4.1 on Cortex-A55 cores to support below features: Supported Features FRDM-IMX93 FRDM-IMX91 Description Zephyr RTOS code base     Based on Zephyr v4.1 FRDM-IMX93 board configure Yes   Board configuration, build, device tree files FRDM-IMX91 board configure   Yes Board configuration, build, device tree files Hello world Yes Yes   Dual Ethernet Yes   TY8521 Ethernet PHY support Display Yes   LCDIF, MIPI DSI, Waveshare 1024x600 7inch DSI LCD(C) Camera Yes   MIPI-CSI, ISI, AP1302 sensor Audio Yes   I2S with eDMA (Driver only) uSDHC Yes   SD card only USB Yes   USB CDC device class   The code has been release on github: Zephyr samples/drivers: https://github.com/nxp-zephyr/zephyr Zephyr HAL: https://github.com/nxp-zephyr/hal_nxp Tag: FRDM-IMX93-v4.1 How to doc is attached.  

In the IMX8MM SDK unfortunately we cannot find any example about of use a GPIO as an input with interrupt.  To use a GPIO as input with interrupt we need to keep in mind how the GPIO IRQs works in the ARM Cortex M4.   We can find in Table 7-2 (CM4 Interrupt Summary) of IMX8MMRM (IMX8MM Reference Manual) the GPIOs IRQs are divided by two parts:     Combined interrupt indication for GPIOn signal 0 throughout 15  Combined interrupt indication for GPIOn signal 16 throughout 31    This basically means, the pines of GPIOn from 0 to 15 are handled by Combined interrupt indication for GPIOn signal 0 throughout 15 and the pines from 16 to 31 are handled by Combined interrupt indication for GPIOn signal 16 throughout 31.    In SDK we can find these definitions in:  <SDK root>/devices/MIMX8MM6/MIMX8MM6_cm4.h (Remember this is for IM8MM SDK)    In this example I will use GPIO5_IO12 (ECSPI2_MISO) as Input with IRQ and GPIO5_IO11 (ECSPI_MOSI) as Output of IMX8MM-EVK. I will connect the Output to the Input and will see the behavior of the IRQ in Rising and Falling edge.    For this example I will connect ECSPI2_MOSI (GPIO5_IO11) to ECSPI_MISO (GPIO5_IO12):   See the below definitions:   #define IN_GPIO   GPIO5  This define the GPIO base of the IN pin  #define IN_GPIO_PIN  12u  This define the pin number (for in)  #define IN_IRQ  GPIO5_Combined_0_15_IRQn  This define the IRQ number (72 in this case)  #define GPIO_IRQ_HANDLER  GPIO5_Combined_0_15_IRQHandler  This is a "pointer" to function that will handle the interrupt  #define IN_NAME  "IN GPIO5_IO12"  This is only a name or description for the pin    See below definitions:    #define OUT_GPIO  GPIO5  This is the GPIO base of OUT pin  #define OUT_GPIO_PIN  11u  This define the pin number (for out)  #define OUT_NAME  "OUT GPIO5_IO11"  This is only a name or description for the pin      Now the below section is the IRQ handler (which was defined before)😞   The GPIO_ClearPinsInterruptFlags(IN_GPIO, 1u << IN_GPIO_PIN); refers to GPIOx_ISR register:      For this example, the IRQ Handler will print "IRQ detected ............" in each interrupt.    We will create two different GPIOs config, one for Output and other one for Input with IRQ Falling edge:    Then configure the GPIOs and IRQ:     EnableIRQ refers to enable the 72 IRQ.   GPIO_PortEnableInterrupts refers to GPIOx_IMR: Finally, the example put the out GPIO5_IO11 in High state and then in low state many. First the IRQ is configured as Falling edge, then as Rising edge.     I will attach the complete source file.    To compile it you can use ARMGCC toolchain directly, but I like to use VSCode with MCUXpresso integration.  Once, when you have your .bin file (in my case igpio_led_output.bin) you can load to board with UUU tool: In your Linux machine: sudo uuu -b fat_write igpio_led_output.bin mmc 2:1 gpio.bin In U-boot board: u-boot=> fastboot 0   Then, when the .bin file was loaded, you can load to the CORTEX M4 in U-boot with: u-boot=> fatload mmc 2:1 ${loadaddr} gpio.bin 7076 bytes read in 14 ms (493.2 KiB/s) u-boot=> cp.b 0x80000000 0x7e0000 0x10000 u-boot=> bootaux 0x7e0000 ## No elf image ar address 0x007e0000 ## Starting auxiliary core stack = 0x20020000, pc = 0x1FFE02CD... u-boot=>   NOTE: You can load the binary to cortex m4 with Custom bootscripts for practicity.   Once the binary loaded in M4 core you should see in seria terminal this logs (Remember GPIO5_IO11 and GPIO5_IO12 must be connected to get the same logs):    And the logs when you disconnect the GPIO5_IO11 and GPIO5_IO12 in execution time:  🔴Disconnection (Red color) 🔵Reconnection (Blue color)   I hope this can helps.     Best regards!    Salas. 

Traditional non-matter devices cannot directly join the matter network. But Matter Bridge solves the problem. Matter bridge can join a Matter network as a Matter device and nonmatter devices need to be mapped to Matter network as a dynamic endpoint. In this way, other Matter devices can communicate with non-matter devices through dynamic endpoints. The Guide is a Matter Zigbee Bridge implement based on i.MX93 + K32W0.     Feature List • Matter over Ethernet • Matter over Wi-Fi • Register and Remove Zigbee Deivces • Connect Zigbee devices into Matter ecosystem seamlessly • Zigbee Devices • On/Off cluster • Temperature Sensor Cluster • Matter Actions • Start Zigbee Network • Zigbee Network Permit Join • Factory Reset • No limitation if migrating to other i.MX MPU like i.MX6ULL, i.MX8MP • OTBR and Zigbee bridge can be integrated into one single device

Hello! In this post, we’ll cross-compile a kernel module for Linux 6.12.    This can be done either using a standalone kernel or a Yocto-built kernel.    Requirements:  A compiled Linux kernel 6.12.  A board running the same kernel version (Linux 6.12 in this case).  A cross-compiler toolchain.    This process applies to any i.MX processor, including i.MX8, i.MX8M, i.MX8MM, i.MX8MN, i.MX8MP, i.MX93, i.MX91, i.MX95, as well as the i.MX6 and i.MX7 families.    Step 1: Compile the Linux Kernel and get the Toolchain    First, you need to compile the Linux kernel (6.12 in this case).    You can do this in a standalone environment or using Yocto.     If you are using a Standalone environment, please refer to the Chapter 4.5.12 How to build U-Boot and Kernel in standalone environment of i.MX Linux User's Guide.  Also, in that document section, you will see how to obtain the cross-compiler toolchain.    NOTE: To get the toolchain you need use Yocto at least once (for more information please refer to i.MX Yocto Project User's Guide😞  $ DISTRO=fsl-imx-xwayland MACHINE=Target-Machine bitbake core-image-minimal -c populate_sdk   At the end of the building, you can install your toolchain populated under:    yocto-bsp/build/tmp/deploy/sdk     There you will find a file called:    fsl-imx-wayland-glibc-x86_64-imx-image-core-armv8a-your-machine-name-toolchain-6.12-walnascar.sh    Execute with:  $ sudo ./fsl-imx-wayland-glibc-x86_64-imx-image-core-armv8a-your-machine-name-toolchain-6.12-walnascar.sh   If you use the default installation, you will have your toolchain under /opt in your host machine.      (If you will use the compiled kernel from Yocto, you can avoid below step)  Download Standalone Kernel source by cloning with:  $ git clone https://github.com/nxp-imx/linux-imx -b lf-6.12.y $ cd linux-imx   To build the kernel in the standalone environment for i.MX 6 and i.MX 7, execute the following commands:    $ make imx_v7_defconfig $ Make   To build the kernel in the standalone environment for i.MX 8 and i.MX 9, execute the following commands:  $ make imx_v8_defconfig $ make   The full kernel compilation is required to generate headers and symbol files required for external module compilation, even if you don't plan to boot this kernel directly.      Step 2: Write a simple Kernel Module to test    Now that your kernel is compiled, you can write a basic kernel module for testing.    Create a new directory. It will have our hello.c and Makefile.    We will create the file hello.c:  #include <linux/init.h> #include <linux/module.h> #include <linux/kernel.h> MODULE_LICENSE("GPL"); MODULE_AUTHOR("Salas"); MODULE_DESCRIPTION("A simple kernel module example for cross-compilation."); MODULE_VERSION("0.1"); static int __init hello_init(void) { printk(KERN_INFO "Hello from the kernel module!\n"); return 0; } static void __exit hello_exit(void) { printk(KERN_INFO "Goodbye from the kernel module!\n"); } module_init(hello_init); module_exit(hello_exit);   Then, create a basic Makefile to compile the modules:    # Module name obj-m += hello.o # Build flags ldflags-y += --strip-debug # Kernel source directory (provided by Yocto) KERNEL_SRC ?= /path/to/your/compiled/kernel # Build target all: $(MAKE) -C $(KERNEL_SRC) M=$(PWD) modules # Clean target clean: $(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean # Install target modules_install: $(MAKE) -C $(KERNEL_SRC) M=$(PWD) modules_install   KERNEL_SRC should be your compiled kernel from your Yocto build:   yocto-bsp/build/tmp/work/your-machine-poky-linux/linux-imx/6.12.20+git/build   Or the Standalone : path/to/linux-imx/     Step 3: Set the toolchain and compile the kernel module    Finally, we can compile the kernel module.    First, set the toolchain (in my case):  $ source /opt/fsl-imx-wayland/6.12-walnascar/environment-setup-armv8a-poky-linux   Then, compile using the makefile:  $ make   f everything goes well, at final you will have the generated files:    hello.ko hello.mod hello.mod.c hello.mod.o hello.o Makefile modules.order Module.symvers   The one we need is the hello.ko (Kernel Object).    We can check if the file was created correctly using:    $ readelf -h hello.ko ELF Header: Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 Class: ELF64 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: REL (Relocatable file) Machine: AArch64 Version: 0x1 Entry point address: 0x0 Start of program headers: 0 (bytes into file) Start of section headers: 33992 (bytes into file) Flags: 0x0 Size of this header: 64 (bytes) Size of program headers: 0 (bytes) Number of program headers: 0 Size of section headers: 64 (bytes) Number of section headers: 41 Section header string table index: 40   We can see the Machine is AArch64 and the Type is a Relocatable file.      Step 4: Running the Kernel Object/Module in the board    Transfer the generated hello.ko file from your host machine to your board.    Then, In your board you can run with:    root@imx93evk:~# ls hello.ko root@imx93evk:~# insmod hello.ko root@imx93evk:~# dmesg | tail [ 5140.547447] Hello world from kernel! root@imx93evk:~# rmmod hello.ko root@imx93evk:~# dmesg | tail [ 5140.547447] Hello world from kernel! [ 5153.415215] Goodbye world from kernel!   I hope this can helps to you.    Best regards,  Salas. 

  Background : Some customer want to test the LPDDR4/X ECC feature based on the i.MX93 chip, But, for now, Our DDR Config Tool do not release this test chosen. And our ECC guide only tell the ECC feature function, does not tell the customer how to test it. So in this article, Will show you more details about ECC feature and how to run the ECC test use uboot command. But I won't put the source code of the test here, You can download the binary run the test on the i.MX93 EVK board.   HW : i.MX93 EVK board with 2GB LPDDR4 SW : 6.1.1-1.0.0   ECC Introduce what is ECC?       ECC is the abbreviation of Error Correction Code. Its function is to automatically detect and repair some minor errors in the memory to prevent data errors. How does ECC work? We can think of it as an "automatic proofreader", and its workflow is roughly as follows:  When writing data: The memory controller generates a "check code" (similar to the fingerprint of the data) for each piece of data. This check code will be stored together with the data. When reading data: The memory controller will recalculate the "fingerprint". Then compare the previously stored check code to see if there is any difference. If a difference is found: If it is just a 1-bit error, ECC can automatically correct it. But, If there are multiple errors, ECC can at least detect them and issue a warning.   ECC test step: 1. Flash the attachment file to the imx93 board. 2. Enter the uboot, run the "ecc --help" command, you will see the below help output message   3. For example : ecc 0x80000000 0x90000000, it will test the ecc feature with on bit error detect and correct , 2 bits errors detect with 256MB DRM size.   if you need this ECC_ test binary file, please contact me, i will share it to you        

Our default BSP code can support below resolution:       https://github.com/nxp-imx/linux-imx/blob/cbfe1a744dc4a794e79396c7079339a54f89c8f2/drivers/phy/freescale/phy-fsl-samsung-hdmi.c If customer want to add new pixel clock about their  panel, they can ask our support to generate the new parameters about it, and then add the result to below struct: const struct phy_config samsung_phy_pll_cfg[] = {}. After add the result to the struct, you need to re-compile the kernel and boot your board, then run the "modetest -c" command Check whether the changes are effective when you run the modetest -c command, the following code show as below, You can see all the resolutions currently supported by your monitor.   How to change the panel display resolution: 1) Run the below command at the uboot period: setenv mmcargs 'setenv bootargs console=${console} root=${mmcroot} video=HDMI-A-1:1920x1080-32@30' video=HDMI-A-1:3840x2160-32@30: Set video output parameters: HDMI-A-1: Specifies the use of the HDMI interface. 3840x2160: The resolution is 3840x2160 (4K). -32: The color depth is 32 bits. @30: The refresh rate is 30Hz. saveenv boot 2) Change the westom.ini file at the /etc/xdg/weston location, Change the resolution you want in [output] part. [output] #name=HDMI-A-1 #mode=640x480@60 #transform=rotate-90 3)Reboot the board, and run the "modetest -p" command see if your change is effective

  This article is an example for users to change the DDR clock on i.MX6ULL board Environment: Hardware : i.MX6ULL EVK board Concept of MMDC controller clock source on i.MX6ull Consult Chapter 18 Clock Controller Module(CCM) in the I.MX 6ull reference manual. The MMDC clock source is shown in Figure 23.3.3.1:   Figure 23.3.3.1 MMDC Clock Source Figure 23.3.3.1 shows the clock source path diagram of MMDC, which is mainly divided into three parts. 1. CBCMR[PRE_PERIPH2_CLK_SEL] : The pre_periph2 clock selector, which is the pre-selector of periph2_clkd, is controlled by the PRE_PERIPH2_CLK_SEL bit (bit22:21) of the CBCMR register. 2. CBCDR[PERIPH2_CLK_SEL] : periph2_clk clock selector, controlled by the PERIPH2_CLK_SEL bit (bit26) of the CBCDR register,When it is 0, pll2_main_clk is selected as the clock source of periph2_clk. When it is 1, periph2_clk2_clk is selected as the clock source of periph2_clk. 3. CBCDR[FABRIC_MMDC_PODF] : It is a frequency divider. The frequency division value is set by the FABRIC_MMDC_PODF bit (bit5:3) of the CBCDR register. It can be set to 0~7, corresponding to 1~8 frequency divisions respectively. To configure the clock source of the MMDC to 396MHz, it must be set to 1 here, so FABRIC_MMDC_PODF=0. The above is the clock source setting of MMDC. Implementation Step 1 : git clone the uboot code from NXP github web $ git clone https://github.com/nxp-imx/uboot-imx.git Step 2 : Modify the different frequencies of DDR by modifying the following files : uboot-imx/board/freescale/mx6ullevk/imximage.cfg As default BSP code, our DDR run frequency is 400MHz (Actually, it's 396MHz), If you want DDR to boot at 132MHz, we need to configurate the CCM_CBCDR[FABRIC_MMDC_PODF] bit,  from this bit content, we need to set it to 010. The frequency division value is 3 based on 396MHz   Change code as following: DATA 4 0x020c4014 0x00018910, Add this code in imximage.cfg file. Step 3 : Re-compile the uboot and flash the uboot to the board. Result Now, We can see that DDR is running at successfully at 132MHz. Before modification:   After modification:      

Hello everyone, in this post we will control one (or more) WS2812 LEDs from a Linux UserSpace application, communicating with Cortex M33 through RPMSG.  Required materials: FRDM-IMX93 WS2812 LED/Strip Attached wsled.c (userspace application) Attached ws2812_m33_project (Source code of firmware for M33)   Environment: Linux Kernel 6.6 arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi SDK 24.12.00   This is the block diagram of the application:        CORTEX M33 SIDE.  From WS2812  LED datasheet, we can see the timing must be precise, that is the reason we will use the Cortex M33 (Real time applications):    As we can see, the timing just accept tolerance of 150ns, that is the reason is preferred to use the Cortex M33 instead of control with Linux that is in charge of other tasks.    The function that we will implement to send Zero and One is:  void WS2812B_send_bit(uint8_t bit) { if (bit) { // Send "1" RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 1); for (int i = 0; i < HIGH_ONE_CYCLES; i++) __asm__("NOP"); RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 0); for (int i = 0; i < LOW_ONE_CYCLES; i++) __asm__("NOP"); } else { // Send "0" RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 1); for (int i = 0; i < HIGH_ZERO_CYCLES; i++) __asm__("NOP"); RGPIO_PinWrite(WS2812B_LED_RGPIO, WS2812B_LED_RGPIO_PIN, 0); for (int i = 0; i < LOW_ZERO_CYCLES; i++) __asm__("NOP"); } }     Testing and measuring the toggle timing with the RGPIO driver of Cortex M33, we could find the best number of NOP instructions to adjust with the required timing according to datasheet, and the results with core running at 200MHz are:    Parameter  Number of NOP times  HIGH_ONE_CYCLES  22  (T1H: 700 ns)  LOW_ONE_CYCLES  12  (T1L: 600 ns)  LOW_ZERO_CYCLES  20  (T0L: 800 ns)  HIGH_ZERO_CYCLES  6    (T0H: 350 ns)      Zero:   One:   Taking in mind this information, we can start to develop our application. From Cortex M33, we created a little protocol, that will wait for instructions to do.    For example, the expected string to fill the RPMSG buffer is:    Index  Purpose  Example  app_buf[0]  Command ('c' or 't')  'c' = store color in buffer  't' = show colors on LEDs  app_buf[1]  Red component (0–255)  0xFF  app_buf[2]  Green component (0–255)  0x00  app_buf[3]  Blue component (0–255)  0x80  app_buf[4]  LED index (target LED position)  e.g. 0, 1, 2    Commands:    'c'  "Color store"  This command stores the RGB color value into a local buffer, targeting a specific LED (app_buf[4]).  It doesn't update the LED strip immediately, it just prepares the data.  Example of RPMSG received buffer from Cortex A (Linux):   app_buf = { 'c', 0xFF, 0x00, 0x00, 2 };  // Store red color for LED 2     't'  "Transfer"  This command sends the full color buffer to the WS2812 strip, updating the LED colors.  The RGB values in the buffer are ignored, it simply triggers an update based on previously stored data.  Example of RPMSG received buffer from Cortex A (Linux):  app_buf = { 't', 0, 0, 0, 0 };  // Transfer the buffered colors to the LED strip     You can modify the code to add your custom commands like change number of LEDs on the strip, or change the GPIO, etc. Currently, the number of WS2812 LEDs supported is defined in software by NUM_RGB_LEDS. As default is 8 LEDs.    I will attach the full code for Cortex M33 firmware, it was tested with arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi and SDK 2_15, SDK 2_16 and SDK 24.    In this example, the EXP_GPIO_IO24 of FRDM-IMX93 was used to control the LED Strip.   CORTEX A55 SIDE.  For Cortex A55 (Linux side), we developed an userspace application, that will create the structure for the buffer to send to the Cortex M33 and send through RPMSG using the imx_rpmsg_tty included on the NXP BSP. You can find the userspace application attached.    As we know, the imx_rpmsg_tty creates the tty channel called ttyRPMSG31 under /dev. So, this userspace application communicates directly with the device /dev/ttyRPMSG31 to send the buffer with the required structure for Cortex M33.    EXAMPLE OF USAGE.    STEP 1. Compile firmware for Cortex M33 and store in FRDM-IMX93 under /lib/firmware to use with remoteproc:   STEP 2.  Compile or cross-compile the userspace application (attached.)  To compile on the platform:  root@imx93evk:~# gcc wsled.c -o wsled root@imx93evk:~# ls wsled wsled.c Also, we can copy the wsled under /bin to practicity. root@imx93evk:~# wsled Error: -c <red> <green> <blue> is required. WS2812 Usage: wsled -c <red> <green> <blue> [-n <led_position>] Load the color of exact LED to the buffer wsled -t Shows the colors to the LEDs   STEP 3. To run the entire example: boot the board and load the firmware for cortex M33 with remoteproc: root@imx93evk:~# cd /sys/class/remoteproc/remoteproc0 root@imx93evk:/sys/class/remoteproc/remoteproc0# echo ws2812_m33.elf > firmware root@imx93evk:/sys/class/remoteproc/remoteproc0# echo start > state  Then, we will receive this from Cortex M33 terminal: RPMSG String Communication Channel FreeRTOS RTOS M33 clock is at: 200000000 Hz Nameservice sent, ready for incoming messages from Cortex-A55! WSLED   Load the imx_rpmsg_tty module in Linux to initialize RPMSG: root@imx93evk:~# modprobe imx_rpmsg_tty   Then, we will have the hello world message from Cortex A (Linux side), but with our buffer format in Cortex M33 console: CMD: h [1]:0x65 [2]:0x6c [3]:0x6c [4]: 111 LEN = 12   Finally, we are ready change colors of the LEDs: Load the buffer (LED 1 = RED, LED 2 = Green, LED 3 = Blue). root@imx93evk:~# wsled -c 0x55 0x00 0x00 -n 1 root@imx93evk:~# wsled -c 0x00 0x55 0x00 -n 2 root@imx93evk:~# wsled -c 0x00 0x00 0x55 -n 3   Show colors on LEDs. root@imx93evk:~# wsled -t    

The use case from one customer we are supporting requires to run i.MX93 M33 code with a combination of DRAM and on chip TCM.  However, the examples in the official MCUXpresso SDK release support to run M33 code in TCM only. So we did some customization to achieve that. User can refer to the the attached slides and patches for the details.

current bsp fixed the lvds pixel clock up to 74.25Mhz for single channel and 148.5Mhz for dual channel, if customer wants to know why and how to change it, maybe can refer to the enclosed file, hope helpful for you

NETC is a TSN capable Ethernet IP, which enables a comprehensive portfolio of Ethernet solutions. One of the major capabilities offered by NETC is the support of Time Sensitive Networking (TSN). TSN is a set of standards developed by IEEE that enables Ethernet to handle time sensitive traffic in addition to best effort traffic. TSN allows time sensitive traffic and best effort traffic to co-exist on the same network, makes Ethernet deterministic with bounded low latency, and with improved reliability and resiliency. This document introduces I.MX95 NETC functional view and capabilities; Analyze IMX95 supported TSN protocols such as 802.1Qbv, 802.1Qav, 802.1Qci, IEEE1588 and stream identifying; Provide Procedures to implement the Qbv use case scenario on I.MX95.

Platform: i.MX8MP EVK, SDK 2.16   The rpmsg debug will stuck at rpmsg_queue_recv/rpmsg_lite_send when we use Step Over debug with JLink. The error log on Linux side: [ 42.422658] remoteproc remoteproc0: kicking vq index: 1 [ 42.524256] imx-rproc imx8mp-cm7: imx_rproc_kick: failed (1, err:-62) [ 42.524286] remoteproc remoteproc0: kicking vq index: 0 [ 42.628566] imx-rproc imx8mp-cm7: imx_rproc_kick: failed (0, err:-62)   The demo source code of rpmsg in SDK uses  RL_BLOCK, this flag will cause communication stuck during debug. while (msg.DATA <= 100U) { (void)PRINTF("Waiting for ping...\r\n"); (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char *)&msg, sizeof(THE_MESSAGE), ((void *)0), RL_BLOCK); msg.DATA++; (void)PRINTF("Sending pong...\r\n"); (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_BLOCK); }   The solution for rpmsg step over debug is that we need to use RL_DONT_BLOCK in sdk.    

Introduction There are some cases where it is needed to flash the image from a removable boot source (e.g. an SD card) to another boot source (e.g. eMMC), according to our documentation this can be done via dd but this does not work in the case you would like to do all the process in the board caused by the eMMC partition structure. Required equipment. i.MX93 FRDM board (this is the selected board for this post, it works for others). Debug USB-C cable. Data USB-C cable. Micro SD (64GB memory used in this test). Personal computer. The default partition configuration for an eMMC device is as follows: Where: - Boot areas are used for bootloader and environment configurations. - Replay-protected memory-block area (RPMB) is used to store secure data. - User area used for application data such as file system, usually divided in two or more partitions. In the case of an image, the eMMC is organized according to the next diagram: - Boot area 1 is used to store SPL and U-boot with no file system in a fixed offset according to each processor as mentioned in i.MX Linux User's Guide section 4.3 Preparing an SD/MMC card to boot. - User area partition 1 uses a FAT format where Kernel and Device Tree files are stored. - User area partition 2 is used for root file system with Ext3/Ext4 format. Exception Our documentation has a method to flash .wic image which contains all the mentioned above or each part manually using an SD card connected to a host Linux machine via dd command: sudo dd if=<image name>.wic of=/dev/sdx bs=1M && sync Or set up the partitions manually such as bootloader: sudo dd if=<U-Boot image> of=/dev/sdx bs=1k seek=<offset> conv=fsync Also, copying the kernel image and DTB file and the root file system as mentioned in i.MX Linux User's Guide. This method works for SD card since the data is stored in user area and the offset changes to burn the bootloader. This fails when we try to flash the image from SD card to eMMC. How to reproduce the issue? First, we need to erase the eMMC, here a post to achieve this task. Format boot partition of eMMC from U-boot - NXP Community How to flash image from SD card to eMMC? With the eMMC erased, we need a boot source to store and flash the image, in this case the SD card. Once the image is flashed into the Micro SD, we need to copy the necessary files such as bootloader and image. By default, our BSP has a User Area space of <>GB and we need to increase it to save the bootloader and the image, here the steps: Verify the device and partition numeration: lsblk The command to increase the size of the partition is the next: parted /dev/<storage unit> unit MiB resizepart <partition> <size in bytes> And the command to apply the changes is: resize2fs /dev/<storage and partition unit>  In this case, the device and partition we need to change is mmcblk0p2 so, the command is as follows: parted /dev/mmcblk0 unit MiB resizepart 2 10000 I increased the partition size by 10000 MB; this will be enough to store the required files. And now, we need to apply the changes: resize2fs /dev/mmcblk0p2 In the board will look like this: Now, let's copy the bootloader and root file system in SD. In this post we will use SCP: Now, we need to boot from SD card and run the next commands: As is mentioned in Linux User's guide, we need to flash the .wic image. This contains all the necessary data to flash the entire image but when flashing from SD card to eMMC we need to follow additional steps to unlock the partition used to store the bootloader: sudo dd if=<image name>.wic of=/dev/sdx bs=1M && sync Disable write protection: echo 0 > /sys/block/<storage and partition unit>/force_ro And flash the bootloader: dd if=<bootloader> of=/dev/<storage and partition unit> bs=1K seek=0 In the board will look like this: With this process now it is needed to reboot the board, change boot mode switches to boot from eMMC, and the board will boot normally, the user can perform an image flashing to simplify development workflow and also an alternative to update OS without external host dependencies.      

Hello, this post describes how you can add Japanese Language to the Yocto BSP. There are just a few steps to achieve. It was tested on the i.MX93-FRDM board, i.MX93-EVK and i.MX8M (Family). And Linux kernel 6.6.36.   The first step before to start your board building according to the Yocto Project User's Guide, is adding the below lines to the local.conf file: GLIBC_GENERATE_LOCALES = "en_US.UTF-8 ja_JP.UTF-8" IMAGE_LINGUAS = "en-us ja-jp" IMAGE_INSTALL:append = " \ glibc-gconv-euc-jp \ glibc-gconv-sjis \ glibc-gconv-utf-16 \ glibc-utils \ fontconfig \ ttf-bitstream-vera \ ttf-dejavu-sans \ "   Where:  glibc-gconv-*: Adds Japanese encoding conversions.   After building, flash the Image to the board and boot it. You can check if the Japanese font was installed successfully with: root@imx93frdm:~# locale -a C POSIX en_US en_US.utf8 ja_JP ja_JP.utf8   We can see it was installed successfully: ja_JP ja_JP.utf8   Then, we can change the Language at Runtime with: root@imx93frdm:~# export LANG=ja_JP.UTF-8 root@imx93frdm:~# export LC_ALL=ja_JP.UTF-8   Finally, probe with a command that supports Japanese outputs like "date": root@imx93frdm:~# date 2024年 2月 27日 火曜日 17:29:11 UTC     I hope this information can helps to you.   Best regards, Salas.

share the document for ov5640 support on imx93 evk with 6.12 bsp

We are pleased to announce that Config Tools for i.MX v25.06 are now available. Downloads & links To download the installer for all platforms, please login to our download site via:  https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX Please refer to  Documentation  for installation and quick start guides. For further information about DDR config and validation, please go to this  blog post. Release Notes Full details on the release (features, known issues...) • DDR – Support for i.MX 91 is added. – Synchronized with BSP Q2 release – Support for the i.MX 91 FRDM board is added. – Support for the i.MX 93 FRDM board is added. – Spectrum support for i.MX 95 and i.MX 943 is spread. – The Address mirroring option in the UI for all mscale devices with DDR3L and DDR4 is exposed. – DDR3L support for i.MX 8M and i.MX 8MM is added. – Linux support for code generation (beta) is added. • SerDes tool – i.MX 943 support (Beta) is added. • Clocks – Support for read-only element settings is added. – Filtering all settings of Initialization modules in the Details view is supported. • Peripherals – A wizard to export the Registers view data in the CSV format is supported. – Performance of the tool is improved. • An ability to export/import Expansion Boards and Expansion Headers is added.