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i.MX Processors Knowledge Base

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i.MX evaluation board can be a simple solution to program i.MX boards in a factory for instance. i.MX evaluation board are not for industrial usage, but you can find plenty of cheap i.MX insdustrial boards on the web. Here I am using an i.MX8QXP rev B0 MEK board and I will program an i.MX6Q SABRE SD board. The first step is to generate your image. Follow the documentation steps to generate the "validation" image. You will have to customize a little bit the local.conf file (in conf/local.conf) to have git, cmake, gcc and other missing package. edit local.conf and add the following lines at the end of the file: IMAGE_INSTALL_append = " git cmake htop packagegroup-core-buildessential xz p7zip rsync" ‍‍‍‍ ‍ I have added rsync package in local, it can replace cp (copy) but with the --progress option you can see the copy progression. P7zip replace unzip for our images archives avaialable on nxp.com as unzip as issues with big files. then rebake your image: bitbake - k fsl - image - validation - imx‍‍‍‍ ‍ When it is done, go in tmp/deploy/image/<your image generated> and use uuu to program your board (I use a sd card; thus I can increase the partition esily): sudo . / uuu - b sd_all imx - boot - imx8qxpmek - sd . bin - flash fsl - image - validation - imx - imx8qxpmek . sdcard . bz2 / * ‍‍‍‍ ‍ As the rootfs can be too small, use gparted under Linux for instance to increase the size of the partition. Put the SD card and start your board. Here here the dirty part... You may know archlinux|ARM websitesite (Arch Linux ARM ), you have a lots of precompiled packages. Thus on the board you can download it, and copy the file in /usr folder (you can use it to have the latest openSSL for  instance!). Plug an ethernet cable on the board and check if it is up: ifconfig - a ifconfig eth0 up‍‍‍‍‍‍‍‍ ‍ ‍ Now you should have access to the internet. On uuu webpage you can find all the packages you need (here I am using a 4.14.98_2.0.0 Linux): mkdir missinglibs cd missinglibs wget http : / / mirror . archlinuxarm . org / aarch64 / core / bzip2 -1.0 . 8 - 2 - aarch64 . pkg . tar . xz wget http : / / mirror . archlinuxarm . org / aarch64 / core / nettle -3.5 . 1 - 1 - aarch64 . pkg . tar . xz wget http : / / mirror . archlinuxarm . org / aarch64 / core / libusb -1.0 . 22 - 1 - aarch64 . pkg . tar . xz wget http : / / mirror . archlinuxarm . org / aarch64 / extra / libzip -1.5 . 2 - 2 - aarch64 . pkg . tar . xz wget http : / / mirror . archlinuxarm . org / aarch64 / core / zlib -1 : 1.2 . 11 - 3 - aarch64 . pkg . tar . xz wget http : / / mirror . archlinuxarm . org / aarch64 / extra / p7zip -16.02 - 5 - aarch64 . pkg . tar . xz cd . . ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ Wait all the archives are downloaded (otherwise you'll decompress before the archive is downloaded) as wget is running in background! Now untar the archives and copy it in the rootfs (dirty): tar - xJf libzip -1.5 . 2 - 2 - aarch64 . pkg . tar . xz tar - xJf libusb -1.0 . 22 - 1 - aarch64 . pkg . tar . xz tar - xJf nettle -3.5 . 1 - 1 - aarch64 . pkg . tar . xz tar - xJf bzip2 -1.0 . 8 - 2 - aarch64 . pkg . tar . xz cp zlib -1 : 1.2 . 11 - 3 - aarch64 . pkg . tar . xz zlib tar - xJf zlib tar - xJf p7zip -16.02 - 5 - aarch64 . pkg . tar . xz cd usr sudo cp - R . / usr cd . . / . . / ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ Download and compile uuu: git clone git : / / github . com / NXPmicro / mfgtools . git cd mfgtools / cmake . make‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ Download an image on nxp.com for instance. I have downloaded on the i.MX6 4.14.98_2.0.0 image and put it on a usb key. then unzip it in the uuu folder: 7z e L4 .14 . 98_2 .0 . 0_ga_images_MX6QPDLSOLOX . zip‍‍‍ ‍ As mentionned before unzip cannot hadle big files... so use 7z as me plug the i.MX6Q SABRE SD to the i.MX8X and program your i.MX6 board: . / uuu uuu . auto - imx6qsabresd‍ uuu ( Universal Update Utility ) for nxp imx chips -- libuuu_1 .3 . 74 - 0 - g64eeca1 Success 1 Failure 0 ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍
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A new version of the Pins Tool for i.MX Application Processors has been released and is available for download as desktop tool from Pins Tool for i.MX Application Processors|NXP. The pins Tool for i.MX Application Processors is used for pin routing configuration, validation and code generation, including pin functional/electrical properties, power rails, run-time configurations, with the following main features: Desktop application Muxing and pin configuration with consistency checking Multicore support ANSI-C initialization code Graphical processor package view Multiple configuration blocks/functions Easy-to-use device configuration Selection of Pins and Peripherals Package with IP blocks Routed pins with electrical characteristics Registers with configured and reset values Power Groups with assigned voltage levels Source code for C/C++ applications Documented and easy to understand source code CSV Report and Device Tree File Localized for English and Simplified Chinese Mostly Connected: On-Demand device data download Integrates with any compiler and IDE What's New Added Label support to give signals a name Added ‘Log’ and ‘Problems’ view to report conflicts between settings Added support for templates to store user configurations as starting point for new configurations Added ability to download and share data for devices, especially for off-network host machines i. MX header files are now automatically part of the device data Import of legacy Processor Expert .pe files Export of register defines Various bug fixes and documentation improvements The release notes of the desktop application are attached to this article. Import Processor Expert Files A new importer has been added to import legacy Processor Expert for i.MX files: Labels Signals can now have user defined labels: Templates, Kits, Boards and Processors When creating a new configuration, it offers Templates, Boards and Processors. Custom configurations can be stored as templates and then used for new configurations. Board Specific Functions With the provided board and kit configurations, there are now pre-configured initialization functions for major blocks on the board: Export Data To simplify downloading the device specific data for the desktop tool, the 'Export' function can be used to download and export the data. The data can be copied that way to another machine or all data for a set of devices can be loaded. Export Registers With the Export command the registers can be exported as text/source: This is used to store the register values: /*FUNCTION********************************************************************** * * Function Name : init_audmux_pins * Description   : Configures pin routing and optionally pin electrical features. * *END**************************************************************************/ #define INIT_AUDMUX_PINS_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_VALUE            0x00000000   /*!< Register name: IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT */ #define INIT_AUDMUX_PINS_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_VALUE         0x00000000   /*!< Register name: IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT */ #define INIT_AUDMUX_PINS_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_VALUE          0x00000000   /*!< Register name: IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT */ #define INIT_AUDMUX_PINS_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_VALUE                  0x00000002   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 */ #define INIT_AUDMUX_PINS_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_VALUE                  0x00000002   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 */ #define INIT_AUDMUX_PINS_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_VALUE                  0x00000002   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 */ #define INIT_AUDMUX_PINS_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_VALUE                  0x00000002   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 */ #define INIT_AUDMUX_PINS_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_VALUE               0x00000003   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 */ #define INIT_AUDMUX_PINS_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_VALUE               0x00000003   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 */ #define INIT_AUDMUX_PINS_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_VALUE               0x00000003   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 */ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ We hope you will find this new release useful. Thanks for designing with NXP! 
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Using a RAW NAND is more difficult compared to eMMC, but for lower capacity it is still cheaper. Even with the ONFI (Open NAND Flash Interface) you can face initialization issue you can find by measure performance. I will take example of a non-well supported flash, I have installed on my evaluation board (SABRE AI). I wanted to do a simple performance test, to check roughly the MB/s I can expected with this NAND. One of a simplest test is to use the dd command: root@imx6qdlsolo : ~ # time dd if = / dev / mtd4 of = / dev / null 851968 + 0 records in 851968 + 0 records out 436207616 bytes ( 436 MB , 416 MiB ) copied , 131.8884 s , 3.3 MB / s ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ As my RAW was supposed to work in EDO Mode 5, I could expect more than 20MB/s. To check what was wrong, read you kernel startup log: Booting Linux on physical CPU 0x0 Linux version 4.1 . 15 - 2.0 . 0 + gb63f3f5 ( bamboo@yb6 ) ( gcc version 5.3 . 0 ( GCC ) ) # 1 SMP PREEMPT Fri Sep 16 15 : 02 : 15 CDT 2016 CPU : ARMv7 Processor [ 412fc09a ] revision 10 ( ARMv7 ) , cr = 10c53c7d CPU : PIPT / VIPT nonaliasing data cache , VIPT aliasing instruction cache Machine model : Freescale i . MX6 DualLite / Solo SABRE Automotive Board [ . . . ] Amd / Fujitsu Extended Query Table at 0x0040 Amd / Fujitsu Extended Query version 1.3 . number of CFI chips : 1 nand : device found , Manufacturer ID : 0xc2 , Chip ID : 0xdc nand : Macronix MX30LF4G18AC nand : 512 MiB , SLC , erase size : 128 KiB , page size : 2048 , OOB size : 64 gpmi - nand 112000 . gpmi - nand : mode : 5 , failed in set feature . Bad block table found at page 262080 , version 0x01 Bad block table found at page 262016 , version 0x01 nand_read_bbt : bad block at 0x00000a7e0000 nand_read_bbt : bad block at 0x00000dc80000 4 cmdlinepart partitions found on MTD device gpmi - nand Creating 4 MTD partitions on "gpmi-nand" : ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ On line 13 you can read "mode:5, failed in set feature", meaning you are not in mode 5... so you have the "relaxed" timing you have at boot. After debuging your code (I have just remove the NAND back reading security check), you can redo the test: root@imx6qdlsolo : ~ # time dd if = / dev / mtd4 of = / dev / null 851968 + 0 records in 851968 + 0 records out 436207616 bytes ( 436 MB , 416 MiB ) copied , 32.9721 s , 13.2 MB / s‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ So you multiplied the performances by 4! Anyway, you have a better tool to measure your NAND performance, it is mtd_speedtest, but you have to rebuild your kernel. In Yocto, reconfigure your kernel (on your PC of couse!): bitbake virtual / kernel - c menuconfig‍‍ ‍ Choose in the menu "Device Drivers" -> "Memory Technology Device (MTD) support" -> "MTD tests support" , even it it not recommended! bitbake virtual / kernel - f - c compile bitbake virtual / kernel - f - c build bitbake virtual / kernel - f - c deploy‍‍‍‍‍‍ ‍ ‍ ‍ Then reflash you board (kernel + rootfs as tests are .ko files): Then you can do more accurate performance test: insmod / lib / modules / 4.1 . 29 - fslc + g59b38c3 / kernel / drivers / mtd / tests / mtd_speedtest . ko dev = 2 == == == == == == == == == == == == == == == == == == == == == == == == = mtd_speedtest : MTD device : 2 mtd_speedtest : MTD device size 16777216 , eraseblock size 131072 , page size 2048 , count of eraseblocks 128 , pages per eraseblock 64 , OOB size 64 mtd_test : scanning for bad eraseblocks mtd_test : scanned 128 eraseblocks , 0 are bad mtd_speedtest : testing eraseblock write speed mtd_speedtest : eraseblock write speed is 4537 KiB / s mtd_speedtest : testing eraseblock read speed mtd_speedtest : eraseblock read speed is 16384 KiB / s mtd_speedtest : testing page write speed mtd_speedtest : page write speed is 4250 KiB / s mtd_speedtest : testing page read speed mtd_speedtest : page read speed is 15784 KiB / s mtd_speedtest : testing 2 page write speed mtd_speedtest : 2 page write speed is 4426 KiB / s mtd_speedtest : testing 2 page read speed mtd_speedtest : 2 page read speed is 16047 KiB / s mtd_speedtest : Testing erase speed mtd_speedtest : erase speed is 244537 KiB / s mtd_speedtest : Testing 2x multi - block erase speed mtd_speedtest : 2x multi - block erase speed is 252061 KiB / s mtd_speedtest : Testing 4x multi - block erase speed mtd_speedtest : 4x multi - block erase speed is 256000 KiB / s mtd_speedtest : Testing 8x multi - block erase speed mtd_speedtest : 8x multi - block erase speed is 260063 KiB / s mtd_speedtest : Testing 16x multi - block erase speed mtd_speedtest : 16x multi - block erase speed is 260063 KiB / s mtd_speedtest : Testing 32x multi - block erase speed mtd_speedtest : 32x multi - block erase speed is 256000 KiB / s mtd_speedtest : Testing 64x multi - block erase speed mtd_speedtest : 64x multi - block erase speed is 260063 KiB / s mtd_speedtest : finished == == == == == == == == == == == == == == == == == == == == == == == == = ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ You can now achieve almost 16MB/s, better than the dd test. Of course you cannot achieve more than 20MB/s, but you are not that far, and the NAND driver need optimizations. To redo the test: rmmod /lib/modules/4.1.29-fslc+g59b38c3/kernel/drivers/mtd/tests/mtd_speedtest.ko insmod /lib/modules/4.1.29-fslc+g59b38c3/kernel/drivers/mtd/tests/mtd_speedtest.ko dev=2 To check your NAND is in EDO mode 5, you can check your clock tree: / unit_tests / dump - clocks . sh clock          parent   flags    en_cnt pre_cnt      rate [ . . . ] gpmi_bch_apb   -- -       00000005    0        0        198000000 gpmi_bch       -- -       00000005    0        0        198000000 gpmi_io        -- -       00000005    0        0         99000000 gpmi_apb       -- -       00000005    0        0        198000000 ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ The IO are clocked now at 99MHz, thus you can read at 49.5MHz (20ns in EDO mode 5 definition).
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Important:  If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the   i.MX community.  Please note that any private messages or direct emails are not monitored and will not receive a response. i.MX 6/7 Family DDR Stress Test   i.MX6/7 DDR Stress Test Tool is a PC-based software to fine-tune DDR parameters and verify the DDR performance on a non-OS, single-task environment(it is a light-weight test tool to test DDR performance). It performs write leveling, DQS gating and read/write delay calibration features.   There are three options to run the DDR Stress test. Each of these options are provided in the attached zip files. The following is a high-level overview of each option along with the naming convention of the associated zip file:   Option 1 GUI based: Run the GUI executable and connect your board to the host PC via USB Archive file: ddr_stress_tester_vX.xx.zip The tool will first need to run a DDR initialization script for the specified i.MX SoC (refer to Load Init Script in the GUI tool).  Example initialization scripts based on NXP's development boards can be found in this zip file under the script folder.  Note, these scripts may need to be modified for your custom board and memory.   Option 2 DDR Stress Tester: JTAG Interface A hardware debugger connected to the board via the JTAG interface is used to download an elf file into the i.MX SoC OCRAM (internal RAM) and then begin execution. Results are shown on the UART serial port (115200-8-n-1). Archive file: ddr_stress_tester_jtag_vX.xx.zip As with the GUI tool, the JTAG/debugger option will first need to run a DDR initialization script for the specified i.MX SoC. Refer to the GUI tool description above for the location of the example scripts (which are found in the ddr_stress_tester_vX.xx.zip file). Note that the scripts are available either in the RealView ICE format (.inc file) or the DS-5 DSTERAM format (.ds). For other debuggers, the user will have to modify the script's command syntax for their specific debugger. This is also true if converting from a RealView Ice (.inc) format to a DS-5 DSTREAM (.ds) format and vice versa. The DDR Stress Tester executable (starting with V2.20) has an auto UART detection feature. If a different UART port for the serial console has been chosen than used on the NXP development tool (EVK, SABRE) specific commands can be added to the DDR initialization script that allows you to configure for the specific UART and then load and run the elf executable. Refer to the FAQ section of this community post and the txt file found in the JTAG archive file for instructions.   Option 3 U-Boot: The boot loader u-boot is running and commands in u-boot are used to download the bin file into SoC OCRAM and begin execution. Results are shown on the UART serial port (115200-8-n-1) Archive file: ddr_stress_tester_uboot_vX.xx.zip When downloading the DDR Stress Tool by u-boot, please copy the ddr-test-uboot-jtag-mxxxx.bin to SD card and load it to IRAM using the 'fatload' u-boot command. For i.MX6, please load the binary to 0x00907000. For i.MX7D, please load the binary to 0x00910000.  It is imperative to first disable the I and D cache in u-boot as shown below as the DDR Stress Test re-configures and re-enables the cache and MMU page table. The following is an example of downloading and running the DDR stress test from u-boot: u-boot> dcache off u-boot> icache off u-boot> fatload mmc 0:1 0x00907000 ddr-test-uboot-jtag-mx6ul.bin u-boot> go 0x00907000   Stress Test Revision Features Comments 3.00 Add i.MX 7ULP support in the GUI version Known issues: USB connection is unstable when under USB HUB or some PC environments 2.92 Minor correction with write leveling calibration code error check to avoid a corner case of flagging an error when none have occurred.  2.91 Resolved issue with write leveling calibration code where a race condition in the code may result in the calibration routine not being able to find any delay values.   Only applies to MX6 series SoCs that support DDR3.   2.90 Reserve write delay line register (MMDC_MPWRDLCTL) configuration as DDR script does when do write calibration. In previous releases, MMDC_MPWRDLCTL would be changed to 0x40404040 by default.  * Further details available in the release notes  _________________________________________________________________________________________________________________________________________    FAQ   Q. I see an error message that states "ERROR: DCD addr is out of valid range.", why is this and how do I resolve? A. Sometimes, when using the register programming aid, there are registers writes that are not supported in the DCD range.  Try looking for the following items and comment them out from the DDR initialization script: wait = on setmem /16 0x020bc000 = 0x30 // disable watchdog (note the address for this may be different between i.MX6x devices)  Q. How do I select the "DDR Density" pull-down menu and what is the purpose of this? A. The DDR Density pull-down menu gives the user the option of testing a DDR density smaller than what they actually have on their board.  The advantage of doing this is to speed up test time to allow the user to perform a "quick test" of their system.  IMPORTANT: it is imperative that the user not set this value higher than the supported density on their board, doing so will cause the stress test to fail and/or lock up. The DDR Density has a different meaning depending on the memory type being tested (DDR3 or LPDDR2): For DDR3, this is the density per CHIP SELECT.  So if your board has two chip selects, and each chip select has 512MB, you would simply select 512MB or lower.  The default setting will simply set this to the detected density per chip select. For LPDDR2, this is the density per CHANNEL.  This is only relevant for MX6 devices that support 2 channel LPDDR2 memories (MX6DQ, MX6DL).  For other MX6 devices that support only one LPDDR2 channel, then this is the total density (for the maximum setting) for that channel. Note that for LPDDR2, the number of chip selects (per channel) is irrelevant when selecting the density to test as the stress test combines both chip-selects into one combined density per channel.  For example, lets say you have a 2GB LPDDR2 device, which 2 channels and 2 chip-selects per channel.  That means you have 512MB per chip select, per channel.  Or, it also means you have 1GB per channel when combining both chip selects per channel.  In this case, you would choose (a maximum setting of) 1GB in the DDR Density drop down menu.  However, this is also the same setting as the default setting (which you are welcome to still choose 1GB to convince yourself that 1GB per channel is indeed being tested). Now let's assume you have only one channel (LPDDR2) and one chip select, with a density of 128MB; in this case, the maximum DDR Density you can select is 128MB. Let's assume you have one channel and two chip selects, each chip select is 128MB;  in this case, the maximum DDR Density you can select is 256MB (a combination of both chip selects).   Note, for the MX7D, an actual density needs to be entered. For the MX6x series, simply leaving this field as Default will cause the DDR stress test to ascertain the supported density from the DDR init script. As the MX7D DDR controller is different, this feature is not supported, hence it is required for the user to enter an actual density (for more details regarding MX7D usage of density and number of chip-selects, see the next FAQ on the DDR CS setting).   Q.  What is the purpose of the "DDR CS" pull-down option? A.  The answer depends on which processor you are testing:   For the i.MX 6x series: This pull down menu gives you the option of testing one chip select (CS0) or ALL (both) chip selects *IF* you have a two-chip select configuration.  If you have a two-chip select configuration, then this allows you to test only one chip select for faster test time; else you can choose to test both chip selects.  Note that if you have a one-chip select configuration and you choose "ALL", the stress test will return an error.   For the iMX 7D: Because the MX7D DDR controller is different, the DDR stress test will need the user to supply the entire supported density found on their board. The chip select field should be left as is (0) as the test will naturally test one chip select to the next. For example, let’s assume you are using two chip selects, with each chip select being 512MB. In this case, you would enter 1GB for the DDR Density field ensuring that both chip selects will be tested. The user is allowed to enter a density less than the density found on their board (for quicker testing), but keeping in mind both chip selects may not be tested in this case.   Q. I run DDR calibration using the DDR Stress Test Tool to obtain the calibration results.  Are these calibration parameters are written to the uboot flash_header.S automatically or manually? A. The calibration values obtained from the DDR Stress Test Tool will need to be manually updated in the flash_header.S file or any other DDR initialization script.   Q. When running the DDR stress test on MX7D and I try to perform calibration, I get an error stating that calibration is not supported, is this expected? A. Yes, calibration is not supported or needed when using MX7.  The reason is, MX7 uses a different memory controller than the MX6 series.  The MX6 series memory controller has built-in support for calibration where the MX7 memory controller does not.   Q. When running the GUI version of the DDR stress test, on MX7 and I leave DDR Density as default, I get an error in the tool stating I must supply a density.  Why is this? A. This is due to the fact that MX7 uses a different memory controller than the MX6 series.  In the MX6 series, it was possible to calculate the memory density from the memory controller register settings.  The MX7 memory controller is different and does not lend itself to easily calculate the supported density based on the register settings.  Instead, the user should verify the density on their board and selected this value in the DDR Density pull-down menu.    Q. I noticed that when I run write-leveling calibration I sometimes see a note that due to the write-leveling calibration value being greater than 1/8 clock cycle that WALAT must be set to 1.  What does this mean? A. In the MMDC chapter of the reference manual for the specific i.MX 6 device, the need to set WALAT is described in the MDMISC register as follows: " The purpose of WALAT is to add time delay at the end of a burst write operation to ensure that the JEDEC time specification for Write Post Amble Delay (tWPST) is met (DQS strobe is held low at the end of a write burst for > 30% a clock cycle before it is released). If the value of any of the WL_DL_ABS_OFFSETn register fields are greater than ‘1F’, WALAT should be set to ‘1’ (cycle additional delay). WALAT should be further increased for any full-cycle delays added by the WL_CYC_DELn register fields. " Therefore, if the write-leveling calibration routine detects any write-leveling delay value greater than 0x1F, it will note to the user that WALAT must be set and the user should update their DDR3 init script to ensure WALAT is set.  Sometimes, a user may find that the write-leveling delay value may fluctuate from one run to the next, which is quite normal.  If it is found that this delay is "borderline" meaning sometimes it is greater than 0x1F and sometimes it might be slightly less, then it is ok to go ahead and set WALAT permanently in your init script as there is no harm in doing so and will ensure you will stay within JEDEC's tWPST.   Q. I sometimes see that after running write-leveling calibration that delay values being reported back are zero'd out (0x00), and then at times I see a non-zero value being reported, why is this? A. It is quite normal to see slight variations in the delay value between write-leveling calibration runs.  The write-leveling calibration routine assumes a majority of users have designed their board such that the DDR3 memories are placed close to the i.MX 6 SoC. There’s a mechanism in NXP’s DDR Stress test write leveling calibration code that checks the returned write leveling value. If the write-leveling calibration routine detects that the returned delay value is greater than ¾ of a clock cycle, it will "zero out" the delay value. It does this because it assumes that such a large delay result is due to the fact that the DQS signal is already delayed relative to the SDCLK, and to align DQS with SDCLK requires the calibration routine to delay DQS even further to align it to the next SDCLK edge, something we ideally would like to avoid.  JEDEC specs that the DQS edge must be within 25% of a SDCLK cycle with respect to the SDCLK edge, so having DQS initially slightly delayed from SDCLK is actually ok, hence why the calibration routine “zero’s” this out when the returned value exceeds ¾ of a clock cycle.  In cases like this, the DQS edge and SDCLK edge are so close together that in some calibration runs, the DQS edge may slightly precede SDCLK (resulting in a very small write-leveling delay value) and other runs, it may be slightly delayed relative to the SDCLK (resulting in a very large write-leveling delay value that will try to align DQS to the next SDCLK edge, hence needs to be zero’d out).   Q. When using the JTAG version of the DDR stress test, how can I select a different UART port for my serial port? A. Under the folder ddr_stress_tester_jtag_v2.52, there's a text file that describes how to add a different UART port by adding a few additional commands to your DDR init script.  The following is an outline of these commands: 1. Ungate UART module clocks (most NXP scripts ungate all of the peripheral clocks at the beginning of the script, so this part is already done) 2. Configure the IOMUX options for the pins you wish the UART to use (normally an IOMUX option for UART_TX and UART_RX, and a daisy chain option for the UART_RX input) 3. Enable the desired UART module via the register UCR1, bit UART_EN 4. Disable other UART modules (UCR1[UART_EN] = 0).  Normally disabling UART1 should be sufficient, but it doesn't hurt to disable all of the other un-used UART options for the purpose of the stress test.   Here's an example in the .ds file vernacular of a set up as follows: MX6DQ, UART4 on KEY_COL0 and KEY_ROW0 (assume clock is ungated to all peripherals): mem set 0x020E01F8 32 0x00000004   #// config_pad_mode(KEY_COL0, ALT4) mem set 0x020E01FC 32 0x00000004   #// config_pad_mode(KEY_ROW0, ALT4); mem set 0x020E0938 32 0x00000001   #// Pad KEY_ROW0 is involved in Daisy Chain. mem set 0x02020080 32 0x00000000   #//disable UART1 in UART1_UCR1 (Note, you can disable other UART modules as well) mem set 0x021F0080 32 0x00000001   #//enable UART4 in UART4_UCR1   Here's another example in the .inc file vernacular of a set up as follows: MX6SX, UART5 on SD4_DATA4 abd SD4_DATA5 (assume clock is ungated to all peripherals): setmem /32 0x020E0294 = 0x2 //IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5, ALT2; UART5_TX_DATA setmem /32 0x020E0290 = 0x2 //IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4, ALT2; UART5_RX_DATA setmem /32 0x020E0850 = 0x00000000 // IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, daisy chain for UART5_RX input to use SD4_DATA4 setmem /32 0x021F4080 = 0x00000001 // Enable UART_EN in UCR1 of UART5 // Disable UART_EN in UCR1 of UART1, UART2, UART3, and UART4 setmem /32 0x02020080 = 0x00000000 // UART1 setmem /32 0x021F0080 = 0x00000000 // UART2 setmem /32 0x021EC080 = 0x00000000 // UART3 setmem /32 0x021E8080 = 0x00000000 // UART4   Related Resources Links: iMX 8M Mini Register Programming Aid DRAM PLL setting  i.MX 8/8X Series DDR Tool Release  i.MX 8M Family DDR Tool Release 
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NOTE: Always de-power the target board and the aggregator when plugging or unplugging smart sensors from the aggregator. NOTE: See this link to instrument a board with a Smart Sensor. This page documents the triple-range "smart" current sensor that's part of a larger system for profiling power on application boards. The smart sensor features a Kinetis KL05Z with three current sense amplifiers. It allows measurement currents in three ranges. Four assembly options allow measurement of rail voltages 0-3.3V (two overall current ranges), 0-6.6V, and 12V. It connects to an aggregator, which powers, controls and aggregates data from a number of smart sensor boards. One of the biggest improvements over the older dual-range measurement system is that the on-sensor microcontroller allows near-simultaneous measurement of all instrumented rails on a board. The dual range profiler can only make one measurement at a time.  These are intended to be used with a microncontroller board to act as a trigger and data aggregator. This aggregator could also be used to reprogram the sensors.  The series resistance added by the smart sensor when in run mode (highest current range) is under 11 milliOhms as measured with 4-point probes and a Keysight B2902B SMU.  A "power oscilloscope" can be made by triggering measurements at regular intervals and presenting the results graphically.... Schematic: Board Layout, Top: Board Layout, Bottom: Here's a photo of two with a nickel is included to show scale. The board measures about 0.5 by 1.3 inches. Connections: The smart sensor header connections are: 5V: powers the 3.3V regulator, which in turn powers everything else on the sensor board 12V: all the gates of all the switching FETs are pulled pulled up to 12V GND: ground connection SCL/TX: I2C clock line  SDA/RX:  I2C data line  SWD_CLK:  line for triggering smart sensors to make measurements RESET_B:  line for resetting the smart sensor board SWD_IO: select line for the smart sensor Theory of operation: Three shunts and current sense amplifiers are used to measure current in three ranges. One shunt/sense amp pair has a 0.002 Ω shunt integrated into the IC package (U1, INA250). The other two sense amps (U2 and U3, INA212) require an external shunt.  FETs Q1, Q2,  and Q3 are used to switch the two lower range shunt/sense amp pairs in and out of circuit. In normal run operation (highest current range), Q1 (FDMC012N03, with Rds(on) under 1.5m Ω ) is turned on, which shorts leaves only U1 in circuit. FETs Q4, Q5 and Q6 translate the voltages to 3.3V so that GPIO on U4 (MCU KL05Z) can control them.  Rail voltage measurement is facilitated via resistors R3, R4, and R12 and Q7. Not all of these are populated in every assembly option. For measuring rail voltages 0-3.3V, R12 is populated. To measure 0-6.6V, R3, R4,and Q7 are populated. When turned on Q7 enables the voltage divider. All of the assembly option population info can be found in the schematic (attached). Regulator U5 (AP2210N) provides the 3.3V supply for all of the components on the board. This 1% tolerance regulator is used to provide a good reference for the ADC in U4.  Microcontroller U4 detects the assembly population option of the board via resistors R9, R10, and R11 so that the same application code can be used across all variations of the sensor boards. GPIO control the FETs and four ADC channels are used to measure the sense amplifier outputs and the rail voltage. Having a microcontroller on the sensor board allows the user to do extra credit things like count coulombs as well as allowing all similarly instrumented rails to measure at the same time via trigger line SWD_CLK. Data communication can be via I2C or UART, since these two pins can do both.  But if multiple sensor boards are to be used with an aggregator, communication needs to be over I2C. Application Code: The latest application code for the KL05Z on the smart sensor resides here: https://os.mbed.com/users/r14793/code/30847-SMRTSNSR-KL05Z/. The latest binary is attached below. In order to re-flash a smart sensor, the modification detailed in the aggregator page needs to be made. Once the modification is completed, leave the aggregator unpowered while pluging the SWD debugger into J5 and the smart sensor to be programmed into JP15. Very old UART-based application code for the KL05Z, built in the on-line MBED compiler (note that it requires the modified mbed library for internal oscillator). This code was used while testing the first smart sensor prototypes. It has since been abandoned. It's published here in the event that a user wants to use a single sensor plugged into JP15 with UART breakout connector J6. /****************************************************************************** * * MIT License (https://spdx.org/licenses/MIT.html) * Copyright 2017-2018 NXP * * MBED code for KL05Z-based "smart" current sensor board, basic testing * of functions via UART (connected via FRDM board and OpenSDA USB virtual * COM port). * * Eventual goal is to have each smart sensor communicate over I2C to an * aggregator board (FRDM board with a custom shield), allowing 1-10 power * supply rails to be instrumented. Extra credit effort is to support * sensors and aggregator with sigrok... * * Because there is no crystal on the board, need to edit source mbed-dev library * to use internal oscillator with pound-define: * change to "#define CLOCK_SETUP 0" in file: * mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/device/system_MKL05Z4.c * ******************************************************************************/ #include "mbed.h" // These will be GPIO for programming I2C address... // not yet implemented, using as test pins... DigitalOut addr0 ( PTA3 ) ; DigitalOut addr1 ( PTA4 ) ; DigitalOut addr2 ( PTA5 ) ; DigitalOut addr3 ( PTA6 ) ; // configure pins for measurements... // analog inputs from sense amps and rail voltage divider... AnalogIn HIGH_ADC ( PTB10 ) ; AnalogIn VRAIL_ADC ( PTB11 ) ; AnalogIn LOW1_ADC ( PTA9 ) ; AnalogIn LOW2_ADC ( PTA8 ) ; // outputs which control switching FETs... DigitalOut VRAIL_MEAS ( PTA7 ) ; // turns on Q7, connecting voltage divider DigitalOut LOW_ENABLE ( PTB0 ) ; // turns on Q4, turning off Q1, enabling low measurement DigitalOut LOW1 ( PTB2 ) ; // turns on Q5, turning off Q2, disconnecting shunt R1 DigitalOut LOW2 ( PTB1 ) ; // turns on Q6, turning off Q3, disconnecting shunt R2 // input used for triggering measurement... // will eventually need to be set up as an interrupt so it minimizes delay before measurement InterruptIn trigger ( PTA0 ) ; // use as a trigger to make measurement... // PTB3/4 can be used as UART or I2C... // For easier development with one smart sensor, we are using UART here... Serial uart ( PTB3 , PTB4 ) ; // tx, rx long int count = 0 ; int n = 25 ; // global number of averages for each measurement int i , temp ; bool repeat = true ; // flag indicating whether measurements should repeat or not const float vref = 3.3 ; // set vref for use in calculations... float delay = 0.25 ; // default delay between measurement bool gui = false ; // flag for controlling human vs machine readable output bool statistics = false ; // flag for outputting min and max along with average (GUI mode only) void enableHighRange ( ) { LOW_ENABLE = 0 ; // short both low current shunts, close Q1 wait_us ( 5 ) ; // delay for FET to settle... (make before break) LOW1 = 0 ; LOW2 = 0 ; // connect both shunts to make lower series resistance VRAIL_MEAS = 0 ; // disconnect rail voltage divider wait_us ( 250 ) ; // wait for B2902A settling... } void enableLow1Range ( ) { LOW1 = 0 ; LOW2 = 1 ; // disconnect LOW2 shunt so LOW1 can measure wait_us ( 5 ) ; // delay for FET to settle... (make before break) LOW_ENABLE = 1 ; // unshort low current shunts, open Q1 VRAIL_MEAS = 0 ; // disconnect rail voltage divider wait_us ( 250 ) ; // wait for B2902A settling... } void enableLow2Range ( ) { LOW1 = 1 ; LOW2 = 0 ; // disconnect LOW1 shunt so LOW2 can measure wait_us ( 5 ) ; // delay for FET to settle... (make before break) LOW_ENABLE = 1 ; // unshort low current shunts, open Q1 VRAIL_MEAS = 0 ; // disconnect rail voltage divider wait_us ( 500 ) ; // wait for B2902A settling... } void enableRailV ( ) { VRAIL_MEAS = 1 ; // turn on Q7, to enable R3-R4 voltage divider wait_us ( 125 ) ; // wait for divider to settle... // Compensation cap can be used to make // voltage at ADC a "square wave" but it is // rail voltage and FET dependent. Cap will // need tuning if this wait time is to be // removed/reduced. // // So, as it turns out, this settling time and // compensation capacitance are voltage dependent // because of the depletion region changes in the // FET. Reminiscent of grad school and DLTS. // Gotta love device physics... } void disableRailV ( ) { VRAIL_MEAS = 0 ; // turn off Q7, disabling R3-R4 voltage divider } // this function measures current, autoranging as necessary // to get the best measurement... void measureAuto ( ) { Timer t ; float itemp ; float tempI = 0 ; float imin = 1.0 ; // used to keep track of the minimum... float imax = 0 ; // used to keep track of the maximum... t . start ( ) ; // use timer to see how long things take... enableHighRange ( ) ; // this should already be the case, but do it anyway... for ( i = 0 ; i < n ; i ++ ) { itemp = HIGH_ADC ; // read HIGH range sense amp output if ( statistics && itemp > imax ) imax = itemp ; // update max if necessary if ( statistics && itemp < imin ) imin = itemp ; // update min if necessary tempI + = itemp ; // add current sample to running sum } tempI = tempI / n * vref / 0.8 ; // compute average we just took... if ( gui ) uart . printf ( "=> %5.3f " , tempI ) ; if ( statistics && gui ) uart . printf ( "[%5.3f/%5.3f] " , imin * vref / 0.8 , imax * vref / 0.8 ) ; // if current is below this threshold, use LOW1 to measure... if ( tempI < 0.060 ) { if ( ! gui ) uart . printf ( "... too Low: %f A, switching to low1 ==>\r\n" , tempI ) ; tempI = 0 ; enableLow1Range ( ) ; // change FETs to enable LOW1 measurement... imin = 1.0 ; imax = 0 ; for ( i = 0 ; i < n ; i ++ ) { itemp = LOW1_ADC ; // read LOW1 sense amp output if ( statistics && itemp > imax ) imax = itemp ; // update max if necessary if ( statistics && itemp < imin ) imin = itemp ; // update min if necessary tempI + = itemp ; // add current sample to running sum } tempI = tempI / n * vref / 0.05 / 1000 ; // compute average we just took... if ( gui ) uart . printf ( "%6.4f " , tempI ) ; if ( statistics && gui ) uart . printf ( "[%6.4f/%6.4f] " , imin * vref / 0.05 / 1000 , imax * vref / 0.05 / 1000 ) ; // if current is below this threshold, use LOW2 to measure... if ( tempI < 0.0009 ) { if ( ! gui ) uart . printf ( "... too Low: %f A, switching to low2 ==>\r\n" , tempI ) ; tempI = 0 ; enableLow2Range ( ) ; // change FETs to enable LOW1 measurement... imin = 1.0 ; imax = 0 ; for ( i = 0 ; i < n ; i ++ ) { itemp = LOW2_ADC ; // read LOW2 sense amp output if ( statistics && itemp > imax ) imax = itemp ; // update max if necessary if ( statistics && itemp < imin ) imin = itemp ; // update min if necessary tempI + = itemp ; // add current sample to running sum } tempI = tempI / n * vref / 2 / 1000 ; // compute average we just took... if ( gui ) uart . printf ( "%8.6f " , tempI ) ; if ( statistics && gui ) uart . printf ( "[%8.6f/%8.6f] " , imin * vref / 2 / 1000 , imax * vref / 2 / 1000 ) ; } } t . stop ( ) ; // stop the timer to see how long it took do do this... enableHighRange ( ) ; if ( ! gui ) uart . printf ( "\r\nCurrent = %f A Current Measure Time = %f sec\r\n" , tempI , t . read ( ) ) ; } // the autoranging should really be done with functions that return values, as should the // functions below... This would make for shorter and more elegant code, but the author // is a bit of a pasta programmer... void measureHigh ( ) { float highI = 0 ; enableHighRange ( ) ; for ( i = 0 ; i < n ; i ++ ) { highI + = HIGH_ADC ; } highI = highI / n ; uart . printf ( "HIghI = %f A\r\n" , vref * highI / 0.8 ) ; } void measureLow1 ( ) { float low1I = 0 ; enableLow1Range ( ) ; for ( i = 0 ; i < n ; i ++ ) { low1I + = LOW1_ADC ; } enableHighRange ( ) ; low1I = low1I / n ; uart . printf ( "low1I = %f A\r\n" , vref * low1I / 0.05 / 1000 ) ; } void measureLow2 ( ) { float low2I = 0 ; enableLow2Range ( ) ; for ( i = 0 ; i < n ; i ++ ) { low2I + = LOW2_ADC ; } enableHighRange ( ) ; low2I = low2I / n ; uart . printf ( "low2I = %f A\r\n" , vref * low2I / 2 / 1000 ) ; } // measure the rail voltage, default being with // a divide by 2 resistor divider // It has to be switched out when not in use or it will // add to the measured current, at least in the low ranges... void measureRailV ( ) { float railv = 0 ; float mult = vref * 2 ; // since divide by 2, we can measure up to 6.6V... float vmin = 5 ; float vmax = 0 ; float vtemp ; enableRailV ( ) ; // switch FETs so divider is connected... for ( i = 0 ; i < n ; i ++ ) { vtemp = VRAIL_ADC ; // read voltage at divider output... if ( statistics && vtemp > vmax ) vmax = vtemp ; // update max if necessary if ( statistics && vtemp < vmin ) vmin = vtemp ; // update min if necessary railv + = vtemp ; // add current sample to running sum } disableRailV ( ) ; // now disconnect the voltage divider railv = railv / n ; // compute average (note this is in normalized ADC [0..1]) // Convert to voltage by multiplying by "mult" if ( ! gui ) uart . printf ( "RailV = %5.3f V " , mult * railv ) ; if ( gui ) uart . printf ( "%5.3f " , mult * railv ) ; if ( statistics && gui ) uart . printf ( "[%5.3f/%5.3f] " , mult * vmin , mult * vmax ) ; uart . printf ( "\r\n" ) ; } // not sure how useful this function is... void measureAll ( ) { measureHigh ( ) ; measureLow1 ( ) ; measureLow2 ( ) ; measureRailV ( ) ; } // test function to see if trigger pin is being hit... // intended for use later to do timed triggering of measurements... void triggerIn ( ) { uart . printf ( "You're triggering me! \r\n" ) ; measureAll ( ) ; } // main... int main ( ) { // set up basic conditions... Timer m ; uart . baud ( 115200 ) ; enableHighRange ( ) ; // default state - only HIGH sense amp in circuit, no divider // signal that we're alive... uart . printf ( "Hello World!\r\n" ) ; // configure the trigger interrupt... trigger . rise ( & triggerIn ) ; while ( true ) { count ++ ; wait ( delay ) ; if ( repeat ) { // if repeat flag is set, keep making measurements... m . reset ( ) ; // reset and start timer... m . start ( ) ; measureAuto ( ) ; // measuring current using auto-ranging... measureRailV ( ) ; // measure rail voltage... m . stop ( ) ; // stop the timer. if ( ! gui ) uart . printf ( " Total Measure Time = %f sec" , m . read ( ) ) ; if ( ! gui ) uart . printf ( "\r\n\r\n" ) ; } // see if there are any characters in the receive buffer... // this is how we change things on the fly... // Commands (single keystroke... it's easier) // t = one shot automeasure // v = measure volt // h = one shot high measure // k = one shot LOW1 measure // l = one shot LOW2 measure (letter l) // r = toggle repeat // R = turn off repeat // + = faster repeat rate // - = slower repeat rate // = = set repeat rate to 0.25 sec // g = use human readable text output // G = use compressed text format for GUI // s = turn statistics output off // S = turn statistics output on (only in GUI mode) // n = decrease number of averages for each measurement // N = increase number of averages for each measurement // // these were for testing FET switching... // 1 = LOW_ENABLE = 0 (the number 1) // 2 = LOW1 = 0 // 3 = LOW2 = 0 // 4 = VRAIL_MEAS = 0 // ! = LOW_ENABLE = 1 // @ = LOW1 = 1 // # = LOW2 = 1 // $ = VRAIL_MEAS = 1 if ( uart . readable ( ) ) { temp = uart . getc ( ) ; if ( temp == ( int ) 't' ) { if ( ! gui ) uart . printf ( "Keyboard trigger: " ) ; measureAuto ( ) ; measureRailV ( ) ; //measureAll(); } if ( temp == ( int ) 'v' ) { uart . printf ( "Keyboard trigger: " ) ; measureRailV ( ) ; } if ( temp == ( int ) 'h' ) { uart . printf ( "Keyboard trigger: " ) ; measureHigh ( ) ; } if ( temp == ( int ) 'k' ) { uart . printf ( "Keyboard trigger: " ) ; measureLow1 ( ) ; } if ( temp == ( int ) 'l' ) { uart . printf ( "Keyboard trigger: " ) ; measureLow2 ( ) ; } if ( temp == ( int ) '1' ) { LOW_ENABLE = 0 ; uart . printf ( "Keyboard trigger: LowEnable = %d\r\n" , 0 ) ; } if ( temp == ( int ) '2' ) { LOW1 = 0 ; uart . printf ( "Keyboard trigger: LOW1 = %d\r\n" , 0 ) ; } if ( temp == ( int ) '3' ) { LOW2 = 0 ; uart . printf ( "Keyboard trigger: LOW2 = %d\r\n" , 0 ) ; } if ( temp == ( int ) '4' ) { VRAIL_MEAS = 0 ; uart . printf ( "Keyboard trigger: VRAILMEAS = %d\r\n" , 0 ) ; } if ( temp == ( int ) '!' ) { LOW_ENABLE = 1 ; uart . printf ( "Keyboard trigger: LowEnable = %d\r\n" , 1 ) ; } if ( temp == ( int ) '@' ) { LOW1 = 1 ; uart . printf ( "Keyboard trigger: LOW1 = %d\r\n" , 1 ) ; } if ( temp == ( int ) '#' ) { LOW2 = 1 ; uart . printf ( "Keyboard trigger: LOW2 = %d\r\n" , 1 ) ; } if ( temp == ( int ) '$' ) { VRAIL_MEAS = 1 ; uart . printf ( "Keyboard trigger: VRAILMEAS = %d\r\n" , 1 ) ; } if ( temp == ( int ) 'r' ) { repeat = ! repeat ; uart . printf ( "Keyboard trigger: repeat toggle: %s \r\n" , repeat ? "true" : "false" ) ; } if ( temp == ( int ) 'R' ) repeat = false ; if ( temp == ( int ) '+' ) { delay - = 0.05 ; if ( delay < 0.05 ) delay = 0.05 ; } if ( temp == ( int ) '-' ) { delay + = 0.05 ; if ( delay > 1 ) delay = 1 ; } if ( temp == ( int ) '=' ) delay = 0.25 ; if ( temp == ( int ) 'g' ) gui = false ; if ( temp == ( int ) 'G' ) gui = true ; if ( temp == ( int ) 's' ) statistics = false ; if ( temp == ( int ) 'S' ) statistics = true ; if ( temp == ( int ) 'n' ) { n - = 25 ; if ( n < 25 ) n = 25 ; } if ( temp == ( int ) 'N' ) { n + = 25 ; if ( n > 1000 ) n = 1000 ; } if ( temp == ( int ) 'N' || temp == ( int ) 'n' ) uart . printf ( "/r/n/r/n Averages = %d \r\n\r\b" , n ) ; } } } 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‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍ ‍
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BlueZ5 provides support for the core Bluetooth layers and protocols. It is flexible, efficient and uses a modular implementation. BlueZ5 has implemented the Bluetooth low level host stack for Bluetooth core specification 4.0 and 3.0+HS which includes GAP, L2CAP, RFCOMM, and SDP. Besides the host stack, BlueZ5 has also supported the following profiles itself or via a third party software. Profiles p rovided by BlueZ: A2DP 1.3 AVRCP 1.5 DI 1.3 HDP 1.0 HID 1.0 PAN 1.0 SPP 1.1 GATT (LE) profiles: PXP 1.0 HTP 1.0 HoG 1.0 TIP 1.0 CSCP 1.0 OBEX based profiles (by obexd): FTP 1.1 OPP 1.1 PBAP 1.1 MAP 1.0 Provided by the oFono project: HFP 1.6 (AG & HF)Supported Profiles BlueZ5 has been supported in the latest Freescale Linux BSP release, so it would be pretty easy to generate the binaries for Bluetooth core stack and its profiles. In order to support A2DP sink on a SabreSD board, the following software should be downloaded and installed onto the target rootfs too. sbc decoder version 1.3 (http://www.kernel.org/pub/linux/bluetooth/sbc-1.3.tar.gz) PulseAudio 5.0 (http://www.freedesktop.org/software/pulseaudio/releases/pulseaudio-5.0.tar.xz) PulseAudio package has some dependencies with bluetooth and sbc packages, and pulseaudio will detect if the two packages have been built and then decide which pulse plugin modules to be generated. So the building order will be 1) bluez5_utils or bluez_utils   2) sbc   3) pulseaudio. After compile and install the above software onto the target rootfs, you should be able to see the following executable under the directory /usr/bin From BlueZ5: bluetoothctl, hciconfig, hciattach (Needed by operating a UART bluetooth module) From PulseAudio: pulseaudio, pactl, paplay If the building dependency has been setup correctly, the following pulse plugin modules should be located under the directory /usr/lib/pulse-5.0/modules module-bluetooth-discover.so      module-bluetooth-policy.so        module-bluez5-device.so   module-bluez5-discover.so Edit the file /etc/dbus-1/system.d/pulseaudio-system.conf, and add the following lines in red: <policy user="pulse">     <allow own="org.pulseaudio.Server"/>    < allow send_destination="org.bluez"/>     <allow send_interface="org.freedesktop.DBus.ObjectManager"/> </policy> Edit the file /etc/dbus-1/system.d/bluetooth.conf, and add the following lines: <policy user="pulse">      <allow send_destination="org.bluez"/>      <allow send_interface="org.freedesktop.DBus.ObjectManager"/> </policy> Adding the following settings at the bottom of the pulseaudio system configuration file which locates in /etc/pulse/system.pa ### Automatically load driver modules for Bluetooth hardware .ifexists module-bluetooth-policy.so load-module module-bluetooth-policy .endif .ifexists module-bluetooth-discover.so load-module module-bluetooth-discover .endif load-module module-switch-on-connect load-module module-alsa-sink device_id=0 tsched=true tsched_buffer_size=1048576 tsched_buffer_watermark=262144 On the system that can automatically detect the alsa cards, the above line #13 should be removed.  Also make sure "auth-anonymous=1" is added to the following line, which can resolve the issue: "Denied access to client with invalid authorization data". load-module module-native-protocol-unix auth-anonymous=1 Selecting a audio re-sampling algorithm and configuring the audio output by adding the following settings to the file daemon.conf locating in /etc/pulse resample-method = trivial enable-remixing = no enable-lfe-remixing = no default-sample-format = s16le default-sample-rate = 48000 alternate-sample-rate = 24000 default-sample-channels = 2 Pulseaudio can be started as a daemon or as a system-wide instance. To run PulseAudio in system-wide mode, the program will automatically drop privileges from "root" and change to the "pulse" user and group. In this case, before launching the program, the "pulse" user and group needs to be created on the target system.  In the example below, "/var/run/pulse" is the home directory for "pulse" user. adduser -h /var/run/pulse pulse addgroup pulse-access adduser pulse pulse-access Because PulseAudio needs to access the sound devices, add the user "pulse" to the "audio" group too. adduser pulse audio Starting bluetoothd and pulseaudio: /usr/libexec/bluetooth/bluetoothd -d & pulseaudio --system --realtime & To verify if the pulseaudio has been set up correctly, you can play a local wave file by using the following command. If you can hear the sound, the system should have been configured correctly. paplay -vvv audio8k16S.wav After setting up the pulseaudio, launch bluetoothctl to pair and connect to a mobile phone. After connecting to a mobile phone, you should be able to see the following information in bluetoothctl console: [bluetooth]# show Controller 12:60:41:7F:03:00         Name: BlueZ 5.21         Alias: BlueZ 5.21         Class: 0x1c0000         Powered: yes         Discoverable: no         Pairable: yes         UUID: PnP Information           (00001200-0000-1000-8000-00805f9b34fb)         UUID: Generic Access Profile    (00001800-0000-1000-8000-00805f9b34fb)         UUID: Generic Attribute Profile (00001801-0000-1000-8000-00805f9b34fb)         UUID: A/V Remote Control        (0000110e-0000-1000-8000-00805f9b34fb)         UUID: A/V Remote Control Target (0000110c-0000-1000-8000-00805f9b34fb)         UUID: Message Notification Se.. (00001133-0000-1000-8000-00805f9b34fb)         UUID: Message Access Server     (00001132-0000-1000-8000-00805f9b34fb)         UUID: Phonebook Access Server   (0000112f-0000-1000-8000-00805f9b34fb)         UUID: IrMC Sync                 (00001104-0000-1000-8000-00805f9b34fb)         UUID: OBEX File Transfer        (00001106-0000-1000-8000-00805f9b34fb)         UUID: OBEX Object Push          (00001105-0000-1000-8000-00805f9b34fb)         UUID: Vendor specific           (00005005-0000-1000-8000-0002ee000001)         UUID: Audio Source              (0000110a-0000-1000-8000-00805f9b34fb)         UUID: Audio Sink                (0000110b-0000-1000-8000-00805f9b34fb)         Modalias: usb:v1D6Bp0246d0515         Discovering: no If you can see the audio sink UUID, you are ready to enjoy the bluetooth music now.
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    Xenomai is real-time framework, which can run seamlessly side-by-side Linux as a co-kernel system, or natively over mainline Linux kernels (with or without PREEMPT-RT patch). The dual kernel nicknamed Cobalt, is a significant rework of the Xenomai 2.x system. Cobalt implements the RTDM specification for interfacing with real-time device drivers. The native linux version, an enhanced implementation of the experimental Xenomai/SOLO work, is called Mercury. In this environment, only a standalone implementation of the RTDM specification in a kernel module is required, for interfacing the RTDM-compliant device drivers with the native kernel. You can get more detailed information from Home · Wiki · xenomai / xenomai · GitLab       I have ported xenomai 3.1 to i.MX Yocto 4.19.35-1.1.0, and currently support ARMv7 and tested on imx6ulevk/imx6ull14x14evk/imx6qpsabresd/imx6dlsabresd/imx6sxsabresdimx6slevk boards. I also did stress test by tool stress-ng on some boards.     You need attached file xenomai-4.14.35-1.1.0-arm-20200818.tgz (which inlcudes all patches and bb file) and add the following variable in conf/local.conf before build xenomai by command bitake xenomai.  XENOMAI_KERNEL_MODE = "cobalt"  PREFERRED_VERSION_linux-imx = "4.19-${XENOMAI_KERNEL_MODE}" IMAGE_INSTALL_append += " xenomai" DISTRO_FEATURES_remove = "optee" or XENOMAI_KERNEL_MODE = "mercury" PREFERRED_VERSION_linux-imx = "4.19-${XENOMAI_KERNEL_MODE}" IMAGE_INSTALL_append += " xenomai" DISTRO_FEATURES_remove = "optee" If XENOMAI_KERNEL_MODE = "cobalt", you can build dual kernel version. And If  XENOMAI_KERNEL_MODE = "mercury", it is single kernel with PREEMPT-RT patch. The following is test result by the command ( /usr/xenomai/demo/cyclictest -p 50 -t 5 -m -n -i 1000 😞 //Mecury on 6ULL with stress-ng --cpu 4 --io 2 --vm 1 --vm-bytes 128M --metrics-brief policy: fifo: loadavg: 6.08 2.17 0.81 8/101 534 T: 0 (  530) P:99 I:1000 C:  74474 Min:     23 Act:  235 Avg:   77 Max:    8278 T: 1 (  531) P:99 I:1500 C:  49482 Min:     24 Act:   32 Avg:   56 Max:    8277 T: 2 (  532) P:99 I:2000 C:  36805 Min:     24 Act:   38 Avg:   79 Max:    8170 T: 3 (  533) P:99 I:2500 C:  29333 Min:     25 Act:   41 Avg:   54 Max:    7069 T: 4 (  534) P:99 I:3000 C:  24344 Min:     24 Act:   51 Avg:   60 Max:    7193 //Cobalt on 6ULL with stress-ng --cpu 4 --io 2 --vm 1 --vm-bytes 128M --metrics-brief policy: fifo: loadavg: 7.02 6.50 4.01 8/100 660 T: 0 (  652) P:50 I:1000 C: 560348 Min:      1 Act:   10 Avg:   15 Max:      71 T: 1 (  653) P:50 I:1500 C: 373556 Min:      1 Act:    9 Avg:   17 Max:      78 T: 2 (  654) P:50 I:2000 C: 280157 Min:      2 Act:   14 Avg:   20 Max:      64 T: 3 (  655) P:50 I:2500 C: 224120 Min:      1 Act:   12 Avg:   15 Max:      57 T: 4 (  656) P:50 I:3000 C: 186765 Min:      1 Act:   31 Avg:   19 Max:      53 //Cobalt on 6qp with stress-ng --cpu 4 --io 2 --vm 1 --vm-bytes 512M --metrics-brief policy: fifo: loadavg: 8.11 7.44 4.45 8/156 1057 T: 0 (  917) P:50 I:1000 C: 686106 Min:      0 Act:    3 Avg:    5 Max:      53 T: 1 (  918) P:50 I:1500 C: 457395 Min:      0 Act:    3 Avg:    5 Max:      49 T: 2 (  919) P:50 I:2000 C: 342866 Min:      0 Act:    2 Avg:    4 Max:      43 T: 3 (  920) P:50 I:2500 C: 274425 Min:      0 Act:    3 Avg:    5 Max:      58 T: 4 (  921) P:50 I:3000 C: 228682 Min:      0 Act:    2 Avg:    6 Max:      46 //Cobalt on 6dl with stress-ng --cpu 2 --io 2 --vm 1 --vm-bytes 256M --metrics-brief policy: fifo: loadavg: 3.35 4.15 2.47 1/122 850 T: 0 (  729) P:50 I:1000 C: 608088 Min:      0 Act:    1 Avg:    3 Max:      34 T: 1 (  730) P:50 I:1500 C: 405389 Min:      0 Act:    0 Avg:    4 Max:      38 T: 2 (  731) P:50 I:2000 C: 304039 Min:      0 Act:    1 Avg:    4 Max:      45 T: 3 (  732) P:50 I:2500 C: 243225 Min:      0 Act:    0 Avg:    4 Max:      49 T: 4 (  733) P:50 I:3000 C: 202683 Min:      0 Act:    0 Avg:    5 Max:      38 //Cobalt on 6SX stress-ng --cpu 4 --io 2 --vm 1 --vm-bytes 512M  --metrics-brief policy: fifo: loadavg: 7.51 7.19 6.66 8/123 670 T: 0 (  598) P:50 I:1000 C:2314339 Min:      0 Act:    3 Avg:    8 Max:      60 T: 1 (  599) P:50 I:1500 C:1542873 Min:      0 Act:   15 Avg:    8 Max:      72 T: 2 (  600) P:50 I:2000 C:1157152 Min:      0 Act:    4 Avg:    9 Max:      55 T: 3 (  601) P:50 I:2500 C: 925721 Min:      0 Act:    5 Avg:    9 Max:      57 T: 4 (  602) P:50 I:3000 C: 771434 Min:      0 Act:    6 Avg:    6 Max:      41 //Cobalt on 6Solo lite stress-ng --cpu 4 --io 2 --vm 1 --vm-bytes 512M  --metrics-brief policy: fifo: loadavg: 7.01 7.04 6.93 8/104 598 T: 0 (  571) P:50 I:1000 C:3639967 Min:      0 Act:    9 Avg:    7 Max:      60 T: 1 (  572) P:50 I:1500 C:2426642 Min:      0 Act:    9 Avg:   11 Max:      66 T: 2 (  573) P:50 I:2000 C:1819980 Min:      0 Act:   11 Avg:   10 Max:      57 T: 3 (  574) P:50 I:2500 C:1455983 Min:      0 Act:   12 Avg:   10 Max:      56 T: 4 (  575) P:50 I:3000 C:1213316 Min:      0 Act:    7 Avg:    9 Max:      43 //Cobalt on 7d with stress-ng --cpu 2 --io 2 --vm 1 --vm-bytes 256M --metrics-brief policy: fifo: loadavg: 5.03 5.11 5.15 6/107 683 T: 0 (  626) P:50 I:1000 C:6842938 Min:      0 Act:    1 Avg:    2 Max:      63 T: 1 (  627) P:50 I:1500 C:4561953 Min:      0 Act:    4 Avg:    2 Max:      66 T: 2 (  628) P:50 I:2000 C:3421461 Min:      0 Act:    0 Avg:    2 Max:      69 T: 3 (  629) P:50 I:2500 C:2737166 Min:      0 Act:    3 Avg:    2 Max:      71 T: 4 (  630) P:50 I:3000 C:2280969 Min:      0 Act:    2 Avg:    1 Max:      33
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-344336 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-341566 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-342877 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-342833 
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[中文翻译版] 见附件   原文链接: i.MX Create Android SDCard Mirror 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-343079 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-343046 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-343116 
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[中文翻译版] 见附件   原文链接: Guide to flash an eMMC from SD Card on i.MX6Q SABRE-SD 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-343344 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-343372 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-343273 
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[中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-343518 
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