The purpose of this document is to specify the maximum LPDDR3, LPDDR4, & LPDDR4X densities that are supported by i.MX 8ULP processor along with a running list of tested memories to aid project feasibility assessment capabilities of customers that are evaluating the SoCs for usage in their products.  It is strongly recommended to consult with NXP and the memory vendor the final choice of the memory part number to ensure that the device meets all the compatibility, availability, longevity and pricing requirements. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs. For any questions related to specific DRAM part numbers please contact the respective DRAM vendor. For any questions regarding the i.MX SoC please contact your support representative or enter a support ticket.  LPDDR4/LPDDR4X Maximum Support Density Please note that the SoC limits the addressable DDR memory map range to 2GB. SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8ULP 32-bit 16Gb/2GB single-rank, dual-channel  device with 16-row addresses (R0-R15) 1, 2, 6,11   LPDDR4 - list of validated memories The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Vendor Validated part number  Notes i.MX 8ULP 16Gb/2GB Micron MT53D512M32D2DS-053 WT:D  10 16Gb/2GB Micron MT53E512M32D1ZW-046 WT:B  8 64Gb/8GB Micron MT53E2G32D4DE-046 WT:A  3, 4, 8 32Gb/4GB Micron MT53E1G32D2FW-046 AUT:B  3, 4, 10 16Gb/2GB Nanya NT6AN512T32AV-J2 3, 7, 8 8Gb/1GB Forsee FL4C2001G-D9  3, 10   LPDDR4x - list of validated memories The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Vendor Validated part number  Notes i.MX 8ULP 16Gb/ 2GB Nanya NT6AP512T32AV-J2  3, 7, 8 4Gb/ 512MB Winbond W66CQ2NQUAFJ  3, 8 8Gb/1GB Alliance AS4C256M32MD4V-062BAN  3, 8 32Gb/4GB Micron MT53E1G32D2FW-046 AUT:B (Z42M) 3, 4, 10 16Gb/ 2GB Micron MT53D512M32D2DS-053 WT:D  10 16Gb/ 2GB Micron MT53E512M32D1ZW-046 WT:B  9   LPDDR3 Maximum Support Density Please note that the SoC limits the addressable DDR memory map range to 2GB. SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8ULP 32-bit 16Gb/2GB Single Channel, Dual Chip Select 5,11   LPDDR3 - list of validated memories The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Vendor Validated part number  Notes i.MX 8ULP 16Gb/2GB Micron  MT52L512M32D2PF-107 WT:B  8   Note 1: The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC and on the memory device used on NXP evaluation boards, and on the JEDEC standards JESD209-4/JESD209-4B (LPDDR4/4X). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 2: Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification). Note 3: The memory part number did not undergo full JEDEC verification however, it passed all functional testing items. Note 4: As the i.MX 8ULP DDR memory map is limited to 2GB, only up to 2GB of the device can be utilized even though the device density exceeds the 2GB range. Note 5: The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC and on the memory device used on NXP evaluation boards, and on the JEDEC standards JESD209-3C (LPDDR3). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.  Note 6: The SoC supports also LPDDR4/4X devices with 17-row address bits however, given the SoC's memory map constraints (see Note 4), full density of those devices cannot be utilized since the dual channel (x32) 17-row address memory devices have the density of 4GB and higher. Note 7: By default, Nanya LPDDR4/4X devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity. If using a Nanya memory device with i.MX8ULP, please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured. Note 8: Part is active. Reviewed July 2025 Note 9: Part is active as MT53E512M32D1ZW-046BWT:B. Reviewed July 2025 Note 10: Part is obsolete. Note 11: i.MX 8ULP does not support Non-Power of 2 Memory densities (e.g. 3,6,12 Gb).

  Purpose Under some situations, need to modify the binary image. Under some situations, no development environment. Under some situations, even no Linux. Only have windows. Board bring up need simple settings, such as simple/tiny rootfs.  Key Features Create small sdcard mirror image All operations are on binary files no need development environment(offline) Set the u-boot environment on binary image Windows OS support Snapshot:   Please download  create_sdcard_mirror_ext.zip.001.zip create_sdcard_mirror_ext.zip.002.zip create_sdcard_mirror_ext.zip.003.zip create_sdcard_mirror_ext.zip.004.zip create_sdcard_mirror_ext.zip.005.zip create_sdcard_mirror_ext.zip.006.zip extract each one to have below files  create_sdcard_mirror_ext.zip.001 create_sdcard_mirror_ext.zip.002 create_sdcard_mirror_ext.zip.003 create_sdcard_mirror_ext.zip.004 create_sdcard_mirror_ext.zip.005 create_sdcard_mirror_ext.zip.006 Put together and extract them.