Setting up the clocks for PCIe is a bit tricky, especially for bare-metal or if not using the Linux BSP. The ENET PLL (PLL6) 100 MHz (SATA) PFD output MUST be enabled in order to access the registers in the PCIe IP block. (To enable this clock, set CCM_ANALOG_PLL_ENET[ENABLE_100M (bit 20)].) This is not well documented in the RM, but follow these steps to insure reliable performance.

Traditional non-matter devices cannot directly join the matter network. But Matter Bridge solves the problem. Matter bridge can join a Matter network as a Matter device and nonmatter devices need to be mapped to Matter network as a dynamic endpoint. In this way, other Matter devices can communicate with non-matter devices through dynamic endpoints. The Guide is a Matter Zigbee Bridge implement based on i.MX93 + K32W0.     Feature List • Matter over Ethernet • Matter over Wi-Fi • Register and Remove Zigbee Deivces • Connect Zigbee devices into Matter ecosystem seamlessly • Zigbee Devices • On/Off cluster • Temperature Sensor Cluster • Matter Actions • Start Zigbee Network • Zigbee Network Permit Join • Factory Reset • No limitation if migrating to other i.MX MPU like i.MX6ULL, i.MX8MP • OTBR and Zigbee bridge can be integrated into one single device

Getting Started for i.MX53 Quick Start Board Here is a quick overview you can follow to get your very first contact with i.MX53 QSB. Introduction Out of box i.MX53 QSB video booting up Ubuntu Original Video: Out of box i.MX53 QSB video booting up Ubuntu with some demo (GPU and VPU) Original Video: How to load a pre-built image Here, you should have loaded your board with the out-of-box SD card. Next step is create your own SD card with some pre-built image. You can find pre-built image packages from Freescale for Linux look for Linux Binary Demo file Please, go to Timesys wikipage[1] and see how to load a pre-built image. You can use some Freescale image or some Timesys image. Both will work! For loading linux OS you need at least 3 images: bootloader image kernel image root file system image or tarball Bootloader For iMX53QSB the default bootloader provided by Freescale is u-boot.You can build your own image using LTIB following the same procedure from here. Kernel You can build a new uImage (kernel binary image to be loaded by u-boot) using LTIB, and you can follow the instructions from here Root File System Root file system is a set of directories and files that become the system environment. How to Built Your Own Image Take BSP package on Freescale i.MX53 QSB web site. Prepare your computer to LTIB installation, see that you need All Boards LTIB. Transfer all images to the SD Card (it will be placed under <ltib_dir>/rootfs/boot). Configure your u-boot environment variable. Boot your board. In case you want to boot via NFS, please follow the next procedure instead. Take BSP package on Freescale i.MX 53 QSB web site. Prepare your computer to LTIB installation, see that you need @all_boards_ltib Configure your computer to be able to provide NFS service: Configure your TFTP server. Configure your NFS server. Configure your u-boot environment variable. Boot your board. Be aware the kernel command line you set on u-boot variable can configure the display.

  Anyone who want to use this solution should get reference design and firmware from Lontium. Hardware Here is the block diagram of LT9611UXC Demo Board. As the MIPI port of our EVK can provide 5V, 3V3 and 1V8.We can remove useless DC-DC chips from reference design. Below is the LT9611UXC Demo Board. Software Download the firmware into LT9611UXC. In Linux side, we need to drive the MIPI to output signals with standard timings of 1080P. Panel type diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 1732b5c72380..c6a829be541f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -696,13 +716,17 @@ &ldb_phy { &mipi_dsi { status = "okay"; + panel@0{ + compatible = "nxp,lt9611uxc"; + reg = <0>; + status = "okay"; }; }; &snvs_pwrkey { diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 4f78bbf63f33..90d99f12515b 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -4997,6 +4997,34 @@ struct panel_desc_dsi { unsigned int lanes; }; +static const struct drm_display_mode lt9611_panel_mode = { + .clock = 148500, + .hdisplay = 1920, + .hsync_start = 1920 + 88, + .hsync_end = 1920 + 88 + 44, + .htotal = 1920 + 88 + 44 + 148, + .vdisplay = 1080, + .vsync_start = 1080 + 4, + .vsync_end = 1080 + 4 + 5, + .vtotal = 1080 + 4 + 5 + 36, +}; + +static const struct panel_desc_dsi lt9611_panel = { + .desc = { + .modes = &lt9611_panel_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 62, + .height = 110, + }, + .connector_type = DRM_MODE_CONNECTOR_DSI, + }, + .flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_SYNC_PULSE, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 4, +}; + static const struct drm_display_mode auo_b080uan01_mode = { .clock = 154500, .hdisplay = 1200, @@ -5201,6 +5229,9 @@ static const struct panel_desc_dsi osd101t2045_53ts = { static const struct of_device_id dsi_of_match[] = { { + .compatible = "nxp,lt9611uxc", + .data = &lt9611_panel, + },{ .compatible = "auo,b080uan01", .data = &auo_b080uan01 }, {

In an earlier topic (Linux fast boot on i.MX6 Sabresd board.) about Linux fast boot on i.MX6 SabreSD board, the demo showed an application startup procedure including u-boot boot, Linux kernel boot, rootfs mount, demo application load and run. Additionally, this demo shows a live video on a LVDS screen from board CSI camera. Its total boot up time is about 1.x seconds. Now, based on Linux fast boot, we integrate it with another demo application: surround view, this demo shows 4 different live videos on LVDS screen from 4 UDP data sockets. In this demo video is drawn by GPU to screen, that means the frame buffers decode by video decoder directly pass to GPU, which is not same as previous demo. The encode video format is also MJPEG in this demo. This demo creates 4 different threads every thread handle one UDP socket, receive buffer, push this buffer to video decoder, get frame buffer from video decoder, pass this buffer to GPU, start GPU render, command GPU draw the render buffer to the screen; this thread needs to occupy one ARM processor to show every video smoothly. So we need a i.MX 6DQ board in this demo. Hardware: i.MX 6DQ SabreSD board Software: 12.09 GA BSP Difference with previous fast boot demo: U-boot difference with previous fast boot demo. 1: Add logo show. (For remove CSI2, V4L2, Capture modules ) Kernel different with previous fast boot demo. 1: Add SMP support. 2: Add Network support. (IPV4, PHY, network driver(FEC)) 3: Remove CSI2, V4L2, Capture. (Remove this need in U-boot procedure Freescale logo show on the screen! ) 4: Add GPU support in kernel. Rootfs difference with previous fast boot demo: 1: Keep rc.s firstly run, while in previous fast boot demo, demo is the firstly running program on rootfs. 2: Get rid of almost all service in rc.conf just keep “mount /proc and /sys” service. Network performance on this demo Software : The default network receive buffer is about 128KB. This default size is too small for this demo; the demo application can't fetch receive buffer in time while kernel network stack will discard some UDP packets if we don't enlarge it. We enlarge this receive buffer through command in inittab before demo running. Hardware: i.MX6 DQ TOI less than 1.2 version has some Ethernet mac layer issue, this issue will also cause some UDP packets lost. So please ensure the SabreSD board i.MX6 DQ chip TOI version is equal 1.2 or more. Attached are some files for your reference. Below patches assume this SabreSD board boot from SD3 and default display port is LVDS1. 1: U-boot and kernel patches based on 12.09. 2: Demo application based on 12.09 vpu test program and vpu test program running configure file. 3: Rootfs startup scripts.

Hello everyone, We have recently migrated our Source code from CAF (Codeaurora) to Github, so i.MX NXP old recipes/manifest that point to Codeaurora eventually will be modified so it points correctly to Github to avoid any issues while fetching using Yocto. Also, all repo init commands for old releases should be changed from: $ repo init -u https://source.codeaurora.org/external/imx/imx-manifest -b <branch name> [ -m <release manifest>] To: $ repo init -u https://github.com/nxp-imx/imx-manifest -b <branch name> [ -m <release manifest>] This will also apply to all source code that was stored in Codeaurora, the new repository for all i.MX NXP source code is: https://github.com/nxp-imx For any issues regarding this, please create a community thread and/or a support ticket. Regards, Aldo.

  It is a Matter Demo setup guide to set up Matter OTBR on i.MX MPU Platfrom. i.MX 2023Q2 release is based on Matter v1.1  Current test solutions. i.MX6ULL + 88W8987(WiFi-BT combo Module) + K32W(OpenThread RCP module) i.MX8MM + 88W8987(WiFi-BT combo Module) + K32W(OpenThread RCP module) i.MX8MM + IW612-RD-EVK (WiFi-BT-Thread tri-radio single-chip module) i.MX93 + IW612 (WiFi-BT-Thread tri-radio single-chip module) Matter Zigbee Bridge  https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Matter-Zigbee-Bridge-base-on-i-MX-MPU-and-K32W/ta-p/1675962   if use imx8mm_k32w_matter.sh or imx93_matter.sh to setup OTBR, you need modify "SSID" and " WIFI_PWD" in the script.    

       Of all the i.MX serials SoC, i.MX28/i.MX6UL/i.MX7D/S use Synchronous Audio Interface(SAI) to support audio applications. SAI supports I2S, AC97, TDM and code/DSP interfaces. The SAI interface consists of these signals: SAI_MCLK         ------------  used to provide working clock for external audio device , such as audio codec. SAI_RX_BCLK  ------------  bit clock for receiving channle. SAI_RX_DATA   ------------  data of receiving channel. SAI_RX_SYNC  ------------  Frame Synchronous signal of Left and right channel for receiving channel. SAI_TX_BCLK  ------------  bit clock for transmitting channel. SAI_TX_DATA   ------------  data of transmitting channel SAI_TX_SYNC  ------------  Frame Synchronous signal of Left and right channel for transmitting channel.         According to above signals, SAI has 2 channels: receive and transmit, and these 2 channels have their own clock: bit clock and frame SYNC, so they can work independently, it means PLAY and CAPTURE can be operated simultaneously, that is to say, SAI works at Asynchronous mode this moment.        In the document, we will discuss several usages of SAI on hardware design when it works at I2S(SYNC) mode. we will take i.MX6UL as an example, and for i.MX7D/S, usages are similar. 1. IOMUX of SAI From i.MX6UL reference manual, there are 3 SAI modules in i.MX6UL: SAI1 , SAI2 & SAI3, see page 2529 in IMX6ULRM.pdf. As common applications, we will use 2 interface of SAIs. 2. Hardware connections for I2S mode Either CPU is Master or Codec is Master, hardware connections are same. (1) Single audio codec or (2) Dual audio codec (3) Audio codec + Bluetooth PCM or (4) Audio codec + Bluetooth PCM + 4G PCM or     [Note]   Attachments are schematics of WM8958 and MAX98089, which are not released by NXP, just for users who are interested in i.MX audio applications reference. If you want to use WM98089 or WM8958, please contact their manufactures and confirm if schematics are correct, so don't use them directly for your solution. NXP China TIC i.MX team Weidong Sun

The document to descript change the u-boot environment variables under the Linux rootfs.  Also provide a demo on i.MX6ull evk of sdcard mirror.  Linux fw_printenv fw_setenv to access U-Boot's environment variables.pdf  --- the document fw_printenv_fw_setenv_demo_iMX6ullevk_L4.14.98_2.0.0_ga.sdcard  --- demo sdcard mirror

In some customers’ design they use the different DRAM from the one used on our reference board. So customers need to customize the DRAM to make it work well on their design. About the i.MX6x hardware design customers can refer to IMX6DQ6SDLHDG.pdf and the section 5 DRAM interface requirements for migration on AN4397. After finishing the hardware design there are two tools important for the DRAM boot up and debug: DRAM Register Programming aid And DRAM Stress Test 1\DRAM Register Programming aid Our expert team create the script to make it easier to work on DDR initialization. You can see all the scripts on different chips and the link is: i.MX Design&amp;Tool Lists The script include 3 sections, when you open it you can see the details. Run basic DDR initialization and test memory and open a debugger memory window pointing to the DDR memory map starting address. Try writing a few words and verify if they can be read correctly. If not, re-check the DDR initialization sequence and if the DDR has been correctly soldered onto the board. It is also recommended to re-check the schematic to ensure the DDR memory has been connected to the SoC correctly. In some cases, a DRAM calibration routine may need to be executed. About the details use and introduction on this script you can refer to Freescale i.MX6 DRAM Port Application Guide-DDR3 After configure the DRAM, you need to use the DRAM Stress Test to perform calibrations the performance and then regulate some parameters. 2\DRAM Stress Test DDR_Stress_Tester is a software application for fine tuning DDR parameters and verifying DDR performance on i.MX6 boards. It performs write leveling, DQS gating, read/write delay calibration on the target board to match the layout of the board and archive the best DDR performance. In addition, the stress test can help the user to verify the DDR performance on their boards. The DDR stress test tool serves two purposes. First, it can perform calibrations for DDR3 to match the MMDC PHY delay settings with PCB for optimal DRAM performance. The process is fully automatic, and therefore the customers can get there DDR3 working in much shorter time. In addition, the tool can run a memory stress test to verify the DDR3 functionality as well as the reliability. The stress test can help verifying the hardware connections, MMDC registers parameters, and DDR3 mode registers setting. The most important purpose of the test is that it allows the customers to verify that the DDR3 operations are stable on their board. The newest version  of DRAM Stress Test tool you can see in our community: i.MX6/7 DDR Stress Test Tool V2.51 And the old version you can see in the follow link: i.MX6 DDR Stress Test Tool V1.0.3 About how to use this tool you can read the use guide. Besides , you also can refer to the Freescale i.MX6 DRAM Port Application Guide-DDR3 By the way, if customers use the different DRAM from our reference design when the use the mfgtool to download the images, they need to build manufacturing images for mfgtool. Take the Linux 3.14.52 BSP as an example: $ bitbake fsl-image-mfgtool-initramfs Hope this can help you.

Overview The purpose of this document is to provide GPU P11.1 upgraded kernel patches and binaries for ICS R13.4-GA or R13.4.1 release. This GPU upgrade fixed some issues and improve the performance, for example chrome browser mess display issue, GUI miss alignment issue, YV12 CTS verifier fail, improve Antutu benchmark performance, improve HTML5 performance, etc. Software and HW platform Software: R13.4-GA or R13.4.1 Android releases Hardware: MX6Dual/Quad SabreSD board or MX6DualLite SabreSD board. Patches You can get the patches from attached zip. For R13.4-GA, please apply the kernel patch and gpu binaries in r13.4-ga-p11.1-gpu-upgrade folder, find them in attach. For R13.4.1, please apply the kernel patch and gpu binaries in 13.4.1-p11.1-gpu-upgrade folder, find them in attach.

Config Tool Introduction and Use From i.MX93 using the Config Tool for the DDR configure. The Config Tools for i.MX is a suite of evaluation and configuration tools that help users from initial evaluation to production software development. Config Tools for i.MX is an easy-to-use way to configure the pins and DDR of the i.MX processor devices. The software, in general, enables you to create, inspect, change, and modify any aspect of the pin configuration and muxing of the device. It also allows you to configure and validate DDR settings. 1 Download and install The link in website: https://www.nxp.com/design/design-center/software/i-mx-developer-resources:IMXSW_HOME   The Config Tools for i.MX is installed as a desktop tool which then loads additional device information through a network connection, but does otherwise not need internet connection. It does not require a project setup, as all the settings are stored in text and generated source files, which then can be easily stored in a version control system or exchanged with other users. Config Tool function For the Config Tool have two function, one is the Pins tool another is the DDR tool functions. 1.1 Pins tool The Pins Tool makes pin configuration easier and faster with an intuitive and easy user interface, which then generates normal C code that can then be used in any C and C++ application. The Pins Tool configures pin signals from multiplexing (muxing) to the electrical properties of pins, and it also creates Device Tree Snippets Include (.dtsi) files and reports in CSV format. Pins Tool Configuration of pin routing/muxing Managing different functions used for routing initialization Configuration of pin functional/electrical properties Generation of code for routing and functional/electrical properties 1.2 DDR Tool   The DDR tool provides two main functionalities: configuration and validation. The DDR configuration provides a user-friendly graphical interface to configure the DDR controller and the DDR PHY. It can be used for tweaking some of the configuration parameters when you want to use different memory modules than the ones received with the board or when you want to optimize the configuration. DDR validation provides different scenarios to verify the DDR performance, by downloading a test image to the processor’s internal RAM through a USB connection. The result is sent to the DDR tool via the UART. DDR validation can help verify DDR stability on the board in a non-OS environment.   DDR Tool The DDR tool is designed for: Configuration of DDR controllers Validation of DDR configuration Support for i.MX 8M and i.MX93 families Configuration: Simplified UI for device configuration Advanced board configuration options Stressing: Stress tests with overnight option Optimization: Sweep ODT configuration and optimization of Vref for DQ and CA Virtual Timing Signal Analysis (vTSA) support: RX and TX data eye, CA BUS signals margin and CA Eye test for LPDDR4 DRAM Generation of C code for U-boot SPL driver The DDR tool allows you to view and configure basic DDR attributes, such as memory type, frequency, number of channels and others and test the DDR configuration by a variety of tests. After you have specified the connection type, you can choose scenarios, tests to run in these scenarios, and view the test results, logs, and summary.         2 Install Download Config_Tools_for_i.MX_v16_x64.exe   Note: In our company PC we need to apply the Admin Manage:   Config Tools for i.MX is available offline (local)  Minimum system requirements One of the following graphical operating systems: – Microsoft Windows 10 (64-bit) – Ubuntu 22.04 LTS Note: Linux-hosted variants of tools are distributed on Linux as 64-bit binaries, which may not work on 32-bit systems. – Supported desktop environments: GNOME – Mac OS X (12.x) 4 GB RAM Display with resolution 1024 x 768 Internet connection for dynamic download from processor database Note: If the MacOS is set to Traditional Chinese, Config Tools for i.MX starts in English and not Chinese. This is intended. 2 The use of the Config tool Configuration of DDR controllers 2.1 Creating a new configuration create a configuration from the Start development wizard or by selecting File > New from the Menubar. If you start creating your development for any NXP board or kit, we recommended you start with example to create a configuration for a board or a kit. Such configuration contains board-specific settings. If you select a processor, the configuration will be empty. 2.2 Run the Config tool Open the Config tool, choose the Creating a new standalone configuration for a processor, board, or kit   Choose the Processor   Choose the i.MX93 part number product     Choose DDR Under the tool select the tools---->DDR Three sections need to mentioned: Make DDR configure right and make the DDR is enabled already.   Two sections are very important the same as the tool we supply before in the old product: DDR paramaters configuration DDR stress test(Validation)   DDR parameters configuration:   This is the UART Port configure, for the i.MX93 EVK Board default use the UART1 for A55 core debug, if in customer’s design use others port can choose here and also need modify the register settings manually.       Advanced parameters config, it is very important:   General advice The I2C connection between MX and PMIC should be consistent with the development board, using the same pad. If choose different , Need to modify I2C     Validation of DDR configuration In the previous DDR stress test tool, only two functions were provided: DDR calibration and stress test. In the new Config tool, more testing items are provided for customers to debug DDR, totaling four items.   When finished the DDR configuration then go to do the validation.     Test DDR initialization script, Perform basic read and write operations   If pass the test, it will be OK. If failed, we need to fail shooting for it. According to the log output information, check boot mode/UART/USB, etc If the test fails, first check the boot mode configuration and UART/USB interface. The previous DDR stress test tool would output statements such as "Please set in serial download mode" or "Please connect UART port", which are obvious. The current Config tool outputs all log information of the code, with a lot of content and no erroneous conclusions. We need to carefully review the log output to identify where the problem lies. Test on the i.MX93 EVK Board, if the boot mode not right and the USB is not connected, when do the test there will be the ERROR Messages in the logs:   Test on the i.MX93 EVK Board, if not with proper UART port, the ERROR Messages in the logs:   Optimization test This requires detailed ODT, driver strength testing, and scanning of all DQ IO configuration options, Test whether each configuration is passed or failed. Finally, output the mapping between the read/write drive strength and ODT output. For the test result when reading, the impedance of DRAM driven strength and PHY ODT cannot be set too big, (Green - pass, Orange - fail)   When determining the optimal ODT/driver strength value for the customer's board, this mapping diagram can be used as a reference, but it cannot be the sole basis for making this decision. If the customer fully references the NXP development board for design, they can first use the default configuration of the development board for testing. Then fine tune it.     VTSA (Virtual Timing Signal Analysis) Generate write and read data eye diagrams by running a series of write/read operations. (Different from using a high-speed oscilloscope for manual physical TSA (pTSA) measurement). Use the DDR controller itself to test margin by writing margin (Diag Write Margin)/diagnosing read margin (Diag Draw a virtual data eye diagram for each DQ channel during the Read Margin test. This tool differs from the actual eye diagram results and is for reference only.     DDR Stress Test The last step, stress test, customer can choose long time test:     Code generate In the right side we can see the lpddr4_timing.c generate, using for the uboot. For this tool, the code can be automatically generated and automatically generated code when the registers change, and do not need to run the test on the board, this is difference with the old tool.   3 i.MX93 UBOOT and Kernel DDR configuration 3.1 The DDR configuration in the Uboot (1) Copy the generated lpddr4x_timing.c to uboot path: board/freescale/imx93_evk/lpddr4x_timing.c       (2) DDR Size setting uboot-imx/include/configs/imx93_evk.h The default size is 2GB for the i.MX93 EVK board.   For the i.MX93EVK uses 2GB LPDDR4X. If using 1GB/512MB LPDDR4, it is important to note that the size of the DDR is related to the memory map address.   According to the Memory map, starting from 0xC000_0000 is 1GB of DRAM space, and starting from 0xA000_0000 is 512MB of DRAM space.               3.2 The DDR configuration align in the Kernel For the 1GB LDDR4/4X device tree modify For the i.MX93 the NPU is accessed through M-core, so a section of DRAM memory is reserved. Regardless of whether NPU is used or not, ethos must be changed here, otherwise starting the kernel may result in errors. Change the address space to within 1GB and appropriately reduce the memory allocation size. arch/arm64/boot/dts/freescale$ vi imx93-11x11-evk.dts         Summary: Config tool is NXP's new DDR script generation/stress testing/OMUX allocation tool, which is required for i.MX93. Other i MX chips can also use this tool. The Config tool provides more DDR testing projects, including testing ODT/driver capabilities and outputting mapping maps, generating DDR virtual eye diagrams, etc., making it easy to test DDR conditions from multiple perspectives. It is recommended to use the Config tool to debug ODT/driver capabilities and other parameters, which is also applicable to all i MX chip, as a debugging tool for reference. The theoretical parameters of the actual board should refer to the simulation results of the board or the measured results of DDR signals. Any questions contact us freely.  

The configuration of DDR is very important. NXP provides a tool for configuring DDR for users of i.MX series products. Here are the details steps for it. Hope can do help for someone. 1\ The DDR part startup and initialization sequence of MX8MM:   The MX 8M series DDR tools include： DDR Register Programming Aid --->Configurate custom DDR initialization MSCALE DDR Tool（DDR Stress Test Tool） --->Test DDR initialization And DDR interface ---> Generate custom DDR initialization code for the u-boot SPL DDR RPA（RPA） is an Excel spreadsheet tool used to develop DDR initialization for specific DDR configurations (DDR device type, density, etc.) of users. RPA generates DDR initialization (in a separate Excel worksheet tab). Detailed explanations and introductions will be provided here. DDR stress testing tool is a software tool based Windows that initializes PHY and generates DDRC configuration Uboot source code to verify whether DDR initialization can be used for u-boot and OS startup. DDR stress testing script, this format is specifically used for DDR stress detection. First, copy the content from this worksheet tab, and then paste it into a text file, naming the document with the ". ds" file extension. Select this file when performing DDR stress testing. 2\i.MX8M series DDR tool work flow           Above is the DDR Tool flow for the i.MX8MM: DDR RPA Tool: Configure DDR parameters to generate DDR Stress Test script ". ds". DDR Sress Test Tool: Test DDR initialization and DDR interface, generate DDR initialization code for the u-boot SPL DDR driver. For the newest DDR RPA version as below：   https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8MMini-m845S-DDR-Register-Programming-Aid-RPA/ta-p/1172443 In the above link, you can download the corresponding DDR configuration tools for i.MX8MM using different DDRs.   3\How to use this script to configure DDR parameters (1)Obtain the required DRAM data sheet from the DRAM supplier firstly. The DDR parameter configuration content will be completed in the "Register Configuration" worksheet tab.   (2)"Register Configuration"，Update the device information table to include DRAM information and system usage. DDR RPA tool:  Register Configuration---->Device Information table   It should be filled out based on the datasheet and relevant hardware circuit design of the selected DDR chip. Specific users can refer to the manual for selecting DDR chips and their own hardware design. Take the i.MX 8M Mini LPDDR4 EVK board as example, it selects the Micron MT53D512M32D2DS-053 WT:D, we can go the Micron website to download the DDR’s datasheet and we can see bellow:   Density per channel (Gb)= Device density (Per Channel Per CS)=8Gb Number of ROW Addresses=R[15:0]=16 Number of Channels=2 (2 Channels i.MX8MM DDR is 32bit) Number of COLUMN Addresses=C[9:0]=10 Total DRAM density(Gb) Automatic calculation：Density per channel (Gb) * Number of Channels * Number of Chip Selects used  =8Gb * 2 * 1=16Gb=2GB Bus Width=M32=32bit: i.MX8MM DDR support 32bit Cycle Freq (MHz)=1500MHZ: The DDR controller clock of the i.MX8MM is set to 1500MHZ. The information filled in is shown in the table below:   (3)Browse through various shaded cells in the spreadsheet to update using data from the DRAM table (pay special attention to the "Legend" table to determine the meaning of different shaded cells; in many cases, these cells may not need to be updated). On the parameter filling page, we can also see the following table, with different colors indicating the need to modify and maintain the original parameters and the affected parameter information. On the register configuration tab, basically only the orange part of the color represents the bit segments that usually need to be updated, and the rest do not need to be modified or configured.   (4)Go to the BoardDataBusConfig tab, fill in the i.MX8MM data bus mapping to the memory device correctly. DDR RPA tool: BoardDataBusConfig ---->Configurate data bus bit   Users should pay special attention to ensuring that this worksheet is configured correctly, otherwise the LPDDR4 system may not function properly. The memory controller of i.MX8MM allows for BYTE internal swapping. For layout convenience, BYTE internal swapping is usually performed, so the BoardDataBusConfig column needs to be configured according to the actual schematic design. We can see the tab in the BoardDataBusConfig, user fill the i.MX8MM data bit connection to associated LPDDR4, the filling in of data bits here should be consistent with the order of our hardware design wiring, which means that if there are swapped data bits, the corresponding relationship must be filled in. Take the LPDDR4 connection to the i.MX8MM as example, the highest 8 bits on the channel B of the LPDDR4   connect to the side of DRAM_DQ00~DRAM_DQ07 of CPU, and the lowest 8 bits on the channel B of the LPDDR4 DRAM_DQ08~DRAM_DQ15 of CPU side，the lowest 8 bits on the channel A of the LPDDR4 connect to the DRAM_DQ16~DRAM_DQ23 of CPU side，the highest 8 bits on the channel A of the LPDDR4 connect to the DRAM_DQ24~DRAM_DQ31 of the CPU side. The i.MX8MM memory controller allows for BYTE internal swapping. For layout convenience, BYTE internal swapping is usually performed, and this needs to be filled in according to the actual wiring in the data bus.       (5)Generate the “.ds” file DDR RPA tool: DDR stress test file ----> “.ds”   Copy the content of the DDR stress test file into a text file and name it a. ds file. For subsequent DDR stress testing purposes.   4\Do the DDR Stress test and Generate the DDR Code The following is the workflow of the DDR tool for the MX8MM series:   Preparation Board: i.MX 8M Mini LPDDR4 EVK Software download: mscale_ddr_tool_v3.31_setup.exe(Install it) PC:Window10 PC file .ds file Hardware requirements for the board: (Please note that these interfaces are necessary when using our stress testing tools) Serial download mode USB OTG port Debug UART port 4.1 Hardware connection   SW1101set 1010xxxxxx go to Serial Download mode, connect the USB-OTG and UART to PC, USB OTG is used for serial download of binary files: UART is used to communicate with users. Note: It is recommended to connect the USB OTG directly to the host PC, rather than through the USB Hub. When power on the board，we can see HID-compliant vendor-defined device and USB Input Device:   UART port are COM3 and COM4:   4.2 Open MSCALEDDR_Tool. exe in administrator mode for DDR parameter calibration and pressure testing：   Select serial port Select Search in Debug UART and you can read that the other two serial ports COM3 and COM4 have been tried. Click on the Connect button. It should be noted that we have two serial ports, one for the A core and the other for the M core. Here, COM4 must be selected to load the script normally. COM4 is used for the A core. Select Target Select the MX8M-mini，speed of CPU chosse1200MHZ, DDR LPDDR4 size 2GB. Select .ds file, Load DDR Script: Copy the generate mx8mm_micron_lpddr4_2gb_2d_1500m_200m_50m_32bit_1cs_RPAv22.ds to the path of the DDR TOOL, then press the Download button. After the download is successful, there will be a print message indicating the successful download and the startup information of the board. We can see the CPU parameters and DDR configuration.   Pres Calibration: This step mainly involves executing the DDR initialization and calibration process. If there is a failure, it is necessary to analyze the DDR problem based on the printed information. If there is no problem, the following interface will appear.   (5) If there are no problems after calibration, perform a pressure test. Only perform this operation when the calibration is passed. Run the test on all frequency set points. If the DDR pressure test passes, you can see that the test has passed successfully. If there is an error, you should search for the problem with the DDR based on the error message.   (6) Generate u-boot timing After the stress test is successfully completed, clicking the Gen Code button will generate a file lpddr4_timing. c, and then the lpddr4_timing. C file can be copied to the u boot directory.     5\ Modifying and configuring DDR frequencies that are not supported by default         The above test is for the frequency point 1500MHZ that is supported by default in our tool. RPA provides default DRAM PLL settings (DRAM frequency) based on the default settings supported in u-boot. If the customer is not using the default supported frequency, in addition to updating the new frequency in RPA, the new DRAM PLL settings should also be manually updated in the u boot SPL. (1) Firstly, in the RPA script, "Clock Cycle Freq (MHz)" is set to the frequency we need (2) Then search for 'memory set 0x30360054' in the RPA DDR stress test file worksheet tab, with a default setting of 1500MHZ.   We can see the DRAM PLL register and bit settings：   For special frequencies, we have a calculation formula here: DDR_freq = [(24MHz x pll_main_div)/(pll_pre_div x 2^pll_post_div)] x 2 1500 = [(24 x 250) / (8 x 2^1)] x 2 Bellow are some special examples of the required configurations for various frequencies:     Finishing configuration, create a. ds test DDR script in the RPA script to specify the frequency of this configuration. （3）After creating a DDR script for the DDR stress testing tool, run the calibration and perform the DDR pressure test. Generating the lpddr4_timing.c, modify the required DDR rate parameters Manually. （4）Modify the DRAM PLL，DRAM_freq = DRAM_PLL x 2 in SPL，u-boot SPL DDR driver can will not automatically change DRAM PLL based on generated code. Therefore, users will need to manually modify the dram_pll_init  for the required DDR PLL parameter.

Some Chinese customers using i.MX series SoC maybe encounter some issues when they download android , u-boot & kernel source code by 'git' command, the following steps will show customer how to get them: 1. Getting repo --No.1 methord # cd ~ # mkdir myandroid # mkdir bin # cd bin # git clone git://aosp.tuna.tsinghua.edu.cn/android/git-repo.git/ <if git failed, use : git clone https://aosp.tuna.tsinghua.edu.cn/android/git-repo.git/> # cd git-repo # cp ./repo ../ --No.2 methord # cd ~ # mkdir bin # curl https://storage.googleapis.com/git-repo-downloads/repo > ~/bin/repo # chmod a+x ~/bin/repo [Note]Customers can select one of above to get "repo" 2. Modifying repo File Open ~/bin/repo file with 'gedit' and Change google address From        REPO_URL = 'https://gerrit.googlesource.com/git-repo' To        REPO_URL = 'git://aosp.tuna.tsinghua.edu.cn/android/git-repo'        like following: ## repo default configuration ## REPO_URL = 'git://aosp.tuna.tsinghua.edu.cn/android/git-repo' REPO_REV = 'stable' 3、Setting email address # cd ~/myandroid # git config --global user.email "[email protected]" # git config --global user.name "weidong.sun" [ Email & Name should be yours] 4、Getting manifest # ~/bin/repo init -u https://aosp.tuna.tsinghua.edu.cn/android/platform/manifest -b android-5.1.1_r1 # cd ~/myandroid/.repo # gedit manifest.xml        Then change the value of fetch to " git://aosp.tuna.tsinghua.edu.cn/android/ ", like following: <manifest>   <remote name="aosp"            fetch="git://aosp.tuna.tsinghua.edu.cn/android/" />   <default revision="refs/tags/android-5.1.1_r1" ...... [Note] android-5.1.1_r1 is version of branch,customer can change it to another. 5、# ~/bin/repo sync          [Note] During runing repo sync, maybe errors will occur like the following: ...... * [new tag]         studio-1.4 -> studio-1.4 error: Exited sync due to fetch errors          Then 'repo sync' exits. But don't worry about it, continue to run the command please ! " ~/bin/repo sync", downloading source code will be continous. 6、Getting Cross Compiler # cd ~/myandroid/prebuilts/gcc/linux-x86/arm # git clone https://aosp.tuna.tsinghua.edu.cn/android/platform/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6 # cd arm-eabi-4.6 # git checkout android-4.4.3_r1 7、Getting linux kernel source code        Probably, customer can't normally get linux kernel by using "git clone" command, she can download it directly from the following weblink:        http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/        At first, create a temperary directory, then download kernel into the directory. see following steps: # cd ~ /Downloads # mkdir linux-kernel   Atfer downloading l5.1.1_2.1.0-ga.tar.gz, use 'tar zxvf l5.1.1_2.1.0-ga.tar.gz' command to decompress it.        Then you can find a subdirectory name " l5.1.1_2.1.0-ga" is created, linux source code is in the directory, we should copy all files in the directory to ~/myandroid/kernel_imx/ # cd ~/myandroid # mkdir kernel_imx # cd kernel_imx # cp -a ~ /Downloads/linux-kernel/l5.1.1_2.1.0-ga ./ 8、Getting uboot source code               Probably, customer can't normally get linux kernel by using "git clone" command, she can download it directly from the following weblink:       http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/        We can use similar way to that of linux kernel to get u-boot source code: # cd ~ /Downloads # mkdir u-boot        Download l5.1.1_2.1.0-ga.tar.gz file, and save it in ~ /Downloads/ u-boot, then decompress it, then u-boot source code will be in ~ /Downloads/ u-boot / l5.1.1_2.1.0-ga/, we should copy all file in the path to ~/myandroid/bootable/bootloader/uboot-imx/ # cd ~/myandroid/bootable/bootloader # mkdir uboot-imx # cd uboot-imx # cp -a ~ /Downloads/u-boot/l5.1.1_2.1.0-ga/* ./ 9、Patch android BSP source code        android_L5.1.1_2.1.0_consolidated-ga_core_source.gz is the name of patch. Run following command to patch android. # copy android_L5.1.1_2.1.0_consolidated-ga_core_source.gz /opt/ # tar zxvf android_L5.1.1_2.1.0_consolidated-ga_core_source.gz # cd /opt/ android_L5.1.1_2.1.0_consolidated-ga_core_source/code/ # tar zxvf L5.1.1_2.1.0_consolidated-ga.tar.gz # cd ~/myandroid # source /opt/ android_L5.1.1_2.1.0_consolidated-ga_core_source/code/ L5.1.1_2.1.0_consolidated-ga/ and_patch.sh # help # c_patch /opt/ android_L5.1.1_2.1.0_consolidated-ga_core_source/code/ L5.1.1_2.1.0_consolidated-ga/ imx_L5.1.1_2.1.0-ga        If everything is OK, the following logs will display on console:               **************************************************************        Success: Now you can build the Android code for FSL i.MX platform               ************************************************************** 10、Patch Freescale extended feathures code        Please refer to chapter 3.3 of Android_User's_Guide.pdf to patch another 2 files:        (1) android_L5.1.1_2.1.0_consolidated-ga_omxplayer_source.gz        (2) android_L5.1.1_2.1.0_consolidated-ga_wfdsink_source.gz [Note]       As for other steps, such as compiling etc, please refer to Android_User's_Guide.pdf that released by NXP. TICS team Weidong Sun 04/01/2016

The Linux L4.9.88_2.0.0 Rocko, i.MX7ULP Linux/SDK2.4 RFP(GA) release files are now available. Linux on IMX_SW web page, Overview -> BSP Updates and Releases ->Linux L4.9.88_2.0.0 SDK on https://mcuxpresso.nxp.com/ web page.   Files available: Linux:  # Name Description 1 imx-yocto-L4.9.88_2.0.0.tar.gz L4.9.88_2.0.0 for Linux BSP Documentation. Includes Release Notes, User Guide. 2 L4.9.88_2.0.0_images_MX6QPDLSOLOX.tar.gz i.MX 6QuadPlus, i.MX 6Quad, i.MX 6DualPlus, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo, i.MX 6Solox Linux Binary Demo Files 3 L4.9.88_2.0.0_images_MX6SLEVK.tar.gz i.MX 6Sololite EVK Linux Binary Demo Files 4 L4.9.88_2.0.0_images_MX6UL7D.tar.gz i.MX 6UltraLite EVK, 7Dual SABRESD, 6ULL EVK Linux Binary Demo Files 5 L4.9.88_2.0.0_images_MX6SLLEVK.tar.gz i.MX 6SLL EVK Linux Binary Demo Files 6 L4.9.88_2.0.0_images_MX8MQ.tar.gz i.MX 8MQuad EVK Linux Binary Demo files 7 L4.9.88_images_MX7ULPEVK.tar.gz i.MX 7ULP EVK Linux Binary Demo Files  8 L4.9.88_2.0.0-ga_mfg-tools.tar.gz Manufacturing Toolkit for Linux L4.9.88_2.0.0 iMX6,7 BSP 9 L4.9.88_2.0.0_mfg-tool_MX8MQ.tar.gz Manufacturing Toolkit for Linux L4.9.88_2.0.0 i.MX8MQ BSP 10 imx-aacpcodec-4.3.5.tar.gz Linux AAC Plus Codec for L4.9.88_2.0.0   SDK:   On https://mcuxpresso.nxp.com/, click the Select Development Board to customize the SDK based on your configuration then download the SDK package.    Target board: i.MX 6QuadPlus SABRE-SD Board and Platform i.MX 6QuadPlus SABRE-AI Board i.MX 6Quad SABRE-SD Board and Platform i.MX 6DualLite SABRE-SD Board i.MX 6Quad SABRE-AI Board i.MX 6DualLite SABRE-AI Board i.MX 6SoloLite EVK Board i.MX 6SoloX SABRE-SD Board i.MX 6SoloX SABRE-AI Board i.MX 7Dual SABRE-SD Board i.MX 6UltraLite EVK Board i.MX 6ULL EVK Board i.MX 6SLL EVK Board i.MX 7ULP EVK Board i.MX 8MQ EVK Board   What’s New/Features: Please consult the Release Notes.   Known issues For known issues and more details please consult the Release Notes.   More information on changes of Yocto, see: README: https://source.codeaurora.org/external/imx/imx-manifest/tree/README?h=imx-linux-rocko ChangeLog: https://source.codeaurora.org/external/imx/imx-manifest/tree/ChangeLog?h=imx-linux-rocko

Introduction EVIS (Enhanced Vision Instruction Set) is an API level program language, which is applicable on GC7000XSVX (i.MX8QM) and VIP8000NanoSi (i.MX8MP). The instructions take advantage of the enhanced vision capabilities in the vision-capble hardware, with low-latency. It provides additional functionality for vision image processing beyond the functions provided through the Khronos Group OpenVX API. In the i.MX8QM/i.MX8MP BSP, the OpenCL compiler also support the EVIS instructions. So, it is also an OpenCL VX Extension API. The source file can found in /usr/include/CL/cl_viv_vx_ext.h. Hardware Requirements i.MX8QM (GC7000XSVX) supports EVIS1. i.MX8MP (VIP8000NanoSi) supports EVIS2. Packed Data Types To fully utilize the computing power of the instructions, the extension API support packed data types. For example, in standard OpenCL, a vector char4 will occupy 4x 32-bit registers, while a packed char16 only occupies 128 bits. Thus use packed data types as possible.  The char, unsigned char, short, unsigned short, integer, unsigned integer, float packed data types are supported. They are defined with vxc_ prefix i.e. vxc_char, vxc_uchar, vxc_short, vxc_ushort, vxc_int, vxc_uint, vxc_float, followed by a literal value n that defines the number of elements in the packed data. Supported values of n are 2, 4, 8, and 16 for all the packed data types. Table 1 List of packed data type Type Description vxc_charn A vector of n packed signed character value vxc_ucharn A vector of n packed unsigned character value vxc_shortn A vector of n packed signed short value vxc_ushortn A vector of n packed unsigned short value vxc_intn A vector of n packed signed integer value vxc_uintn A vector of n packed unsigned integer value vxc_floatn A vector of n packed float value OP_CODE Instructions OP_CODE instructions operate on packed data. The enumeration can be found in /usr/include/CL/cl_viv_vx_ext.h. Only EVIS1 supports instructions: VXC_IAdd VXC_MagPhase VXC_BiLinear VXC_SelectAdd VXC_BitReplace VXC_Filter VXC_DP2x16/VXC_DP2x16_b Objects load and store Packed type image data read/write: supported types are packed 8-bit/16bit integer, 16bit float. Image read/write for image1d_t/image1d_array/image2d_t. Offset should be composed by using VXC_5BITOFFSET_XY(x, y). VXC_OP4(img_load, Dest, Image, Coord, Offset, Info) VXC_OP4_NoDest(img_store, Image, Coord, Color, Info) Parameters:         img_load/img_store    Read/write image data.          Dest                            The destination loading the data to.         Image                          The packed image data read from for img_load. The packed image data writing to for img_store.         Coord                          Coordinates to read/write the image data.         Color                           The image data being written to Image for img_store.         Info                              See more info in VXC_MODIFIER(StartBin, EndBin, SourceBin, RoundingMode, Clamp). VXC_MODIFIER(StartBin, EndBin, SourceBin, RoundingMode, Clamp) Parameters:         StartBin/EndBin           The first bin/the last bin for consecutive packed data.         SourceBin                    Not used.          RoundingMode            0: Toward Zero (truncated), 1: Toward Infinity (rounded up), 2: To Nearest Even, 3: not used.         Clamp                          0: no, result is truncated to fit result type (just the lower bits are copied), 1: yes, result is clamped to fit the result type. For example, int2 coord = (int2)(get_global_id(0), get_global_id(1)); vxc_uchar16 r1; VXC_OP4(img_load, r1, in_image, coord, 0, VXC_MODIFIER(0, 15, 0, VXC_RM_TowardZero, 0)); VXC_Filter This interface applies a specified filter on a 3x3 pixel block. VXC_OP4(filter, Dest, Src0, Src1, Src2, Info) Parameters:         filter                           Filter modes.         Dest                          The filtered image.         Src0                          The first row pixels for 3x3 filter.         Src1                          The second row pixels for 3x3 filter.         Src2                          The third row pixles for 3x3 filter.         Info                            See more info in VXC_MODIFIER_FILTER(StartBin, EndBin, SourceBin, Filter, Clamp). VXC_MODIFIER_FILTER(StartBin, EndBin, SourceBin, Filter, Clamp) Parameters:         StartBin/EndBin        The first bin/the last bin for consecutive packed data.         SourceBin                 Not used.         Filter                          Filter modes are listed in table 2.         Clamp                        0: no, result is truncated to fit result type (just the lower bits are copied), 1: yes, result is clamped to fit the result type. Table 2. List of filter modes: Filter Mode Description VXC_FM_BOX Compute a 3x3 box filter: |1/9, 1/9, 1/9, 1/9, 1/9, 1/9, 1/9, 1/9, 1/9|. VXC_FM_Guassian Compute a 3x3 Gaussian filter: |1/16, 2/16, 1/16, 2/16, 4/16, 2/16, 1/16, 2/16, 1/16|. VXC_FM_SobelX Compute a 3x3 Sobel filter in the x-direction: |-1, 0, 1, -2, 0, 2, -1, 0, 1|. VXC_FM_SobelY Compute a 3x3 Sobel filter in the y-direction: |-1, -2, -1, 0, 0, 0, 1, 2, 1|. VXC_FM_ScharrX Compute a 3x3 Scharr filter in the x-direction: |3, 0, -3, 10, 0, -10, 3, 0, -3|. VXC_FM_ScharrY Compute a 3x3 Scharr filter in the y-direction: |3, 10, 3, 0, 0, 0, -3, -10, -3|. VXC_FM_Max Get the maximum from a 3x3 kernel. VXC_FM_Min Get the minimum from a 3x3 kernel. VXC_FM_Median Get the median from a 3x3 kernel. For example (details in Gaussian Filter examples), int2 coord_in1 = coord + (int2)(-1, -1);\n\ VXC_OP4(img_load, lineA, in_image, coord_in1, 0, VXC_MODIFIER(0, 15, 0, VXC_RM_TowardZero, 0));\n\ int2 coord_in2 = coord + (int2)(-1, 0);\n\ VXC_OP4(img_load, lineB, in_image, coord_in2, 0, VXC_MODIFIER(0, 15, 0, VXC_RM_TowardZero, 0));\n\ int2 coord_in3 = coord + (int2)(-1, 1);\n\ VXC_OP4(img_load, lineC, in_image, coord_in3, 0, VXC_MODIFIER(0, 15, 0, VXC_RM_TowardZero, 0));\n\ int info = VXC_MODIFIER_FILTER(0, 13, 0, VXC_FM_Guassian, 0);\n\ VXC_OP4(filter, out, lineA, lineB, lineC, info); ;\n\ VXC_AbsDiff Calculates a result for the absolute difference between a and b. It works on packed data, so it can compute 16x 8-bit values or 8x 16-bit values. VXC_OP3(abs_diff, Dest, Src0, Src1, Info) Parameters:         abs_diff                 Specify the function of absolute difference.         Dest                      Destination to store the result.         Src0                      The first source to calculate the absolute difference.         Src1                      The second source to calculate the absolute differenece.         Info                       See more info in VXC_MODIFIER(StartBin, EndBin, SourceBin, RoundingMode, Clamp). There are also other interfaces will not be specified here, which can be found in the /usr/include/CL/cl_viv_vx_ext.h, i.e. VXC_IAdd, VXC_IAccSq, VXC_Lerp, VXC_MagPhase, VXC_MulShift, VXC_Clamp, VXC_BiLinear, VXC_SelectAdd, VXC_AtomicAdd, VXC_BitExtract and VXC_BitReplace.  Further Reading: OpenVX Vision Image Extension API Introduction - DP Dot Products

i.MX8X 板级开发包镜像结构 ...................................... 3 2 创建 i.MX8QXP Linux 5.4.24 板级开发包编译环境 ..... 3 2.1 下载板级开发包 ....................................................... 3 2.2 创建yocto编译环境: ................................................. 5 2.3 独立编译 ............................................................... 10 3 i.MX8X SC firmware ................................................. 16 3.1 SC firmware 目录结构 ........................................... 16 3.2 SC firmware 启动流程 ........................................... 18 3.3 SC firmware定制 ................................................... 18 4 i.MX8X ATF .............................................................. 30 5 FSL Uboot 定制 ........................................................ 32 5.1 FDT支持 ............................................................... 33 5.2 DM(driver model)支持 ........................................... 38 5.3 Uboot目录 结构 ..................................................... 52 5.4 Uboot编译 ............................................................. 54 5.5 Uboot初始化流程 .................................................. 55 5.6 uboot 定制 ............................................................ 66 5.7 uboot debug信息 ................................................... 82

Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response.   This is the detailed programming aid for the registers associated with DRAM initialization (DDR3 and LPDDR2) of the MX6UL/ULL/ULZ (consolidated RPA). The last work sheet tab in the tool formats the register settings for use with the ARM DS5/RealView debugger. It can be manually converted by the user to a DCD file format used by uboot or other bootloaders (note the removal of debugger specific commands in this tab). The programming aids were developed for internal NXP validation and development boards.   This tool serves as an aid to assist with programming the DDR interface of the MX6UL/ULL/ULZ and is based on the DDR initialization scripts developed by the R&D team and no guarantees are made by this tool.   The following are some general notes regarding this tool: Refer to the "How To Use" tab in the tool as a starting point to use this tool. Note that in the "DStream .ds file" tab there are DS5 debugger specific commands that should be commented out or removed when using the DRAM initialization for non-debugger specific applications (like when porting to bootloaders). This tool may be updated on an as-needed basis for bug fixes or future improvements.  There is no schedule for aforementioned maintenance.  

The attached patch applies to iMX6_Platform_SDK for i.MX6 Dual and Quad and brings 2 additional SDMA memory to memory scripts: fixed destination address, increasing source address fixed source address, increasing destination address. With this patch, the new scripts are also integrated in the SDMA Test menu of the Platform SDK. I created these scripts starting from the ROM script ap_to_ap. In order to dump the content of the SDMA ROM, I used mxc_printSDMAcontext function which is also included in the attached patch and can be invoked when needed.