DRAM Customization on i.MX6x

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DRAM Customization on i.MX6x

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DRAM Customization on i.MX6x

In some customers’ design they use the different DRAM from the one used on our reference board. So customers need to customize the DRAM to make it work well on their design.

About the i.MX6x hardware design customers can refer to IMX6DQ6SDLHDG.pdf and the section 5 DRAM interface requirements for migration on AN4397.

After finishing the hardware design there are two tools important for the DRAM boot up and debug:

DRAM Register Programming aid And DRAM Stress Test

1\DRAM Register Programming aid

Our expert team create the script to make it easier to work on DDR initialization.

You can see all the scripts on different chips and the link is:

i.MX Design&Tool Lists


The script include 3 sections, when you open it you can see the details.

Run basic DDR initialization and test memory and open a debugger memory window pointing to the DDR memory map starting address. Try writing a few words and verify if they can be read correctly. If not, re-check the DDR initialization sequence and if the DDR has been correctly soldered onto the board. It is also recommended to re-check the schematic to ensure the DDR memory has been connected to the SoC correctly. In some cases, a DRAM calibration routine may need to be executed.

About the details use and introduction on this script you can refer to

Freescale i.MX6 DRAM Port Application Guide-DDR3

After configure the DRAM, you need to use the DRAM Stress Test to perform calibrations the performance and then regulate some parameters.

2\DRAM Stress Test

DDR_Stress_Tester is a software application for fine tuning DDR parameters and verifying DDR performance on i.MX6 boards. It performs write leveling, DQS gating, read/write delay calibration on the target board to match the layout of the board and archive the best DDR performance.

In addition, the stress test can help the user to verify the DDR performance on their boards.

The DDR stress test tool serves two purposes.

First, it can perform calibrations for DDR3 to match the MMDC PHY delay settings with PCB for optimal DRAM performance. The process is fully automatic, and therefore the customers can get there DDR3 working in much shorter time.

In addition, the tool can run a memory stress test to verify the DDR3 functionality as well as the reliability. The stress test can help verifying the hardware connections, MMDC registers parameters, and DDR3 mode registers setting. The most important purpose of the test is that it allows the customers to verify that the DDR3 operations are stable on their board.

The newest version  of DRAM Stress Test tool you can see in our community:

i.MX6/7 DDR Stress Test Tool V2.51

And the old version you can see in the follow link:

i.MX6 DDR Stress Test Tool V1.0.3

About how to use this tool you can read the use guide. Besides , you also can refer to the

Freescale i.MX6 DRAM Port Application Guide-DDR3

By the way, if customers use the different DRAM from our reference design when the use the mfgtool to download the images, they need to build manufacturing images for mfgtool.

Take the Linux 3.14.52 BSP as an example: $ bitbake fsl-image-mfgtool-initramfs

Hope this can help you.

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