The configuration of DDR is very important. NXP provides a tool for configuring DDR for users of i.MX series products. Here are the details steps for it. Hope can do help for someone.
1\ The DDR part startup and initialization sequence of MX8MM:
The MX 8M series DDR tools include：
- DDR Register Programming Aid
--->Configurate custom DDR initialization
- MSCALE DDR Tool（DDR Stress Test Tool）
--->Test DDR initialization And DDR interface
---> Generate custom DDR initialization code for the u-boot SPL
DDR RPA（RPA） is an Excel spreadsheet tool used to develop DDR initialization for specific DDR configurations (DDR device type, density, etc.) of users. RPA generates DDR initialization (in a separate Excel worksheet tab). Detailed explanations and introductions will be provided here.
DDR stress testing tool is a software tool based Windows that initializes PHY and generates DDRC configuration Uboot source code to verify whether DDR initialization can be used for u-boot and OS startup. DDR stress testing script, this format is specifically used for DDR stress detection. First, copy the content from this worksheet tab, and then paste it into a text file, naming the document with the ". ds" file extension. Select this file when performing DDR stress testing.
2\i.MX8M series DDR tool work flow
Above is the DDR Tool flow for the i.MX8MM:
DDR RPA Tool: Configure DDR parameters to generate DDR Stress Test script ". ds".
DDR Sress Test Tool: Test DDR initialization and DDR interface, generate DDR initialization code for the u-boot SPL DDR driver.
For the newest DDR RPA version as below：
In the above link, you can download the corresponding DDR configuration tools for i.MX8MM using different DDRs.
3\How to use this script to configure DDR parameters
(1)Obtain the required DRAM data sheet from the DRAM supplier firstly.
The DDR parameter configuration content will be completed in the "Register Configuration" worksheet tab.
(2)"Register Configuration"，Update the device information table to include DRAM information and system usage.
DDR RPA tool: Register Configuration---->Device Information table
It should be filled out based on the datasheet and relevant hardware circuit design of the selected DDR chip. Specific users can refer to the manual for selecting DDR chips and their own hardware design.
Take the i.MX 8M Mini LPDDR4 EVK board as example, it selects the Micron MT53D512M32D2DS-053 WT:D, we can go the Micron website to download the DDR’s datasheet and we can see bellow:
Density per channel (Gb)= Device density (Per Channel Per CS)=8Gb
Number of ROW Addresses=R[15:0]=16
Number of Channels=2 (2 Channels i.MX8MM DDR is 32bit)
Number of COLUMN Addresses=C[9:0]=10
Total DRAM density(Gb) Automatic calculation：Density per channel (Gb) * Number of Channels *
Number of Chip Selects used =8Gb * 2 * 1=16Gb=2GB
Bus Width=M32=32bit: i.MX8MM DDR support 32bit
Cycle Freq (MHz)=1500MHZ: The DDR controller clock of the i.MX8MM is set to 1500MHZ.
The information filled in is shown in the table below:
(3)Browse through various shaded cells in the spreadsheet to update using data from the DRAM table (pay special attention to the "Legend" table to determine the meaning of different shaded cells; in many cases, these cells may not need to be updated).
On the parameter filling page, we can also see the following table, with different colors indicating the need to modify and maintain the original parameters and the affected parameter information. On the register configuration tab, basically only the orange part of the color represents the bit segments that usually need to be updated, and the rest do not need to be modified or configured.
(4)Go to the BoardDataBusConfig tab, fill in the i.MX8MM data bus mapping to the memory device correctly.
DDR RPA tool: BoardDataBusConfig ---->Configurate data bus bit
Users should pay special attention to ensuring that this worksheet is configured correctly, otherwise the LPDDR4 system may not function properly. The memory controller of i.MX8MM allows for BYTE internal swapping. For layout convenience, BYTE internal swapping is usually performed, so the BoardDataBusConfig column needs to be configured according to the actual schematic design.
We can see the tab in the BoardDataBusConfig, user fill the i.MX8MM data bit connection to associated LPDDR4, the filling in of data bits here should be consistent with the order of our hardware design wiring, which means that if there are swapped data bits, the corresponding relationship must be filled in. Take the LPDDR4 connection to the i.MX8MM as example, the highest 8 bits on the channel B of the LPDDR4
connect to the side of DRAM_DQ00~DRAM_DQ07 of CPU, and the lowest 8 bits on the channel B of the LPDDR4 DRAM_DQ08~DRAM_DQ15 of CPU side，the lowest 8 bits on the channel A of the LPDDR4 connect to the DRAM_DQ16~DRAM_DQ23 of CPU side，the highest 8 bits on the channel A of the LPDDR4 connect to the DRAM_DQ24~DRAM_DQ31 of the CPU side.
The i.MX8MM memory controller allows for BYTE internal swapping. For layout convenience, BYTE internal swapping is usually performed, and this needs to be filled in according to the actual wiring in the data bus.
(5)Generate the “.ds” file
DDR RPA tool: DDR stress test file ----> “.ds”
Copy the content of the DDR stress test file into a text file and name it a. ds file. For subsequent DDR stress testing purposes.
4\Do the DDR Stress test and Generate the DDR Code
The following is the workflow of the DDR tool for the MX8MM series:
Preparation
Board: i.MX 8M Mini LPDDR4 EVK
Software download: mscale_ddr_tool_v3.31_setup.exe(Install it)
PC:Window10 PC file .ds file
Hardware requirements for the board: (Please note that these interfaces are necessary when using our stress testing tools)
- Serial download mode
- USB OTG port
- Debug UART port
4.1 Hardware connection
SW1101set 1010xxxxxx go to Serial Download mode, connect the USB-OTG and UART to PC, USB OTG is used for serial download of binary files: UART is used to communicate with users. Note: It is recommended to connect the USB OTG directly to the host PC, rather than through the USB Hub.
When power on the board，we can see HID-compliant vendor-defined device and USB Input Device:
UART port are COM3 and COM4:
4.2 Open MSCALEDDR_Tool. exe in administrator mode for DDR parameter calibration and pressure testing：
- Select serial port
Select Search in Debug UART and you can read that the other two serial ports COM3 and COM4 have been tried. Click on the Connect button. It should be noted that we have two serial ports, one for the A core and the other for the M core. Here, COM4 must be selected to load the script normally. COM4 is used for the A core.
- Select Target
Select the MX8M-mini，speed of CPU chosse1200MHZ, DDR LPDDR4 size 2GB.
- Select .ds file, Load DDR Script:
Copy the generate mx8mm_micron_lpddr4_2gb_2d_1500m_200m_50m_32bit_1cs_RPAv22.ds to the path of the DDR TOOL, then press the Download button. After the download is successful, there will be a print message indicating the successful download and the startup information of the board. We can see the CPU parameters and DDR configuration.
- Pres Calibration:
This step mainly involves executing the DDR initialization and calibration process. If there is a failure, it is necessary to analyze the DDR problem based on the printed information. If there is no problem, the following interface will appear.
(5) If there are no problems after calibration, perform a pressure test. Only perform this operation when the calibration is passed. Run the test on all frequency set points. If the DDR pressure test passes, you can see that the test has passed successfully. If there is an error, you should search for the problem with the DDR based on the error message.
(6) Generate u-boot timing
After the stress test is successfully completed, clicking the Gen Code button will generate a file lpddr4_timing. c, and then the lpddr4_timing. C file can be copied to the u boot directory.
5\ Modifying and configuring DDR frequencies that are not supported by default
The above test is for the frequency point 1500MHZ that is supported by default in our tool. RPA provides default DRAM PLL settings (DRAM frequency) based on the default settings supported in u-boot. If the customer is not using the default supported frequency, in addition to updating the new frequency in RPA, the new DRAM PLL settings should also be manually updated in the u boot SPL.
(1) Firstly, in the RPA script, "Clock Cycle Freq (MHz)" is set to the frequency we need
(2) Then search for 'memory set 0x30360054' in the RPA DDR stress test file worksheet tab, with a default setting of 1500MHZ.
We can see the DRAM PLL register and bit settings：
For special frequencies, we have a calculation formula here:
DDR_freq = [(24MHz x pll_main_div)/(pll_pre_div x 2^pll_post_div)] x 2
1500 = [(24 x 250) / (8 x 2^1)] x 2
Bellow are some special examples of the required configurations for various frequencies:
Finishing configuration, create a. ds test DDR script in the RPA script to specify the frequency of this configuration.
（3）After creating a DDR script for the DDR stress testing tool, run the calibration and perform the DDR pressure test. Generating the lpddr4_timing.c, modify the required DDR rate parameters Manually.
（4）Modify the DRAM PLL，DRAM_freq = DRAM_PLL x 2 in SPL，u-boot SPL DDR driver can will not automatically change DRAM PLL based on generated code. Therefore, users will need to manually modify the dram_pll_init for the required DDR PLL parameter.
