i.MX6SX DDR3 Register Programming Aid

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i.MX6SX DDR3 Register Programming Aid

i.MX6SX DDR3 Register Programming Aid

This is a detailed programming aid for the registers associated with MMDC initialization. The last sheet formats the register settings for use with ARM RealView ICE. It can also be used with the windows executable for the DDR Stress Test. This programming aid was used for internal Freescale validation boards.


On sheet 2 it says :

"i.MX6SL MMDC DDR3 Configuration Spreadsheet "

I hope/presume this should read i.MX6SX" ?

Hi Mark,

I'm trying to use the above spreadsheet to setup the DCD for our PCB with an iMX6SX CPU and 2xDDR3 MICRON MT41K128M16JT-125:K. The design is based on mx6sxsabresd board.

DDR3 Calibration passed correctly after running about 12h. Returned values are the following:


Register nameRegister addressRegister value (HEX)
MPDGCTRL0 PHY00x021b083c0x41480144
MPDGCTRL1 PHY00x021b08400x01380130
MPRDDLCTL PHY00x021b08480x42403C40
MPWRDLCTL PHY00x021b08500x36343834
MPWLDECTRL0 PHY00x021b080c0x00220023
MPWLDECTRL1 PHY00x021b08100x001F0023

The DDR3 parameters has been set as below:


Memory type:DDR3
Memory part number:MT41K128M16JT-125
Density per chip select (Gb):2
Number of Chip Selects per channel used1
Total DRAM density (Gb)2
Number of ROW Addresses14
Number of COLUMN Addresses10
Number of BANKS8
Bus Width (input 16, 32, or 64 bits)32
Clock Cycle Freq (MHz)400
Clock Cycle Time (ns)2.5

Using the DCD register setting in the RealView.inc tab the board doesn't boot at all, even the serial console doesn't work.

Any idea?

Thanks in advance,

Roberto Fichera.

With a different DCD I was able to boot u-boot but the kernel still hang with lots of rubbish after cache controller: see below:

U-Boot 2014.04-imx_v2014.04_3.14.28_1.0.0_ga+g88123ea (Jul 02 2015 - 19:04:50)

CPU:   Freescale i.MX6SX rev1.2 at 792 MHz

CPU:   Temperature 34 C, calibration data: 0x5ba52269

Reset cause: POR

Board: Domus iMX6SX (ID:e301dab51902b1d4)

I2C:   ready

DRAM:  512 MiB

force_idle_bus: sda=0 scl=0 sda.gp=0x3 scl.gp=0x2

MAX7322 Not found


*** Warning - bad CRC, using default environment

In:    serial

Out:   serial

Err:   serial

Found PFUZE100! deviceid 0x11, revid 0x21

mmc0 is current device

Net:   Phy not found

PHY reset timed out


Warning: failed to set MAC address

Normal Boot

Hit any key to stop autoboot:  0


=> setenv mmcroot /dev/mmcblk3p2 rootwait rw earlyprintk

=> saveenv

Saving Environment to MMC...

Writing to MMC(0)... done

=> boot

mmc0 is current device

mmc0 is current device

reading boot.scr

** Unable to read file boot.scr **

reading zImage

5934672 bytes read in 277 ms (20.4 MiB/s)

Booting from mmc ...

reading domus-reva.dtb

48167 bytes read in 19 ms (2.4 MiB/s)

Kernel image @ 0x80800000 [ 0x000000 - 0x5a8e50 ]

## Flattened Device Tree blob at 83000000

   Booting using the fdt blob at 0x83000000

   Using Device Tree in place at 83000000, end 8300ec26

switch to ldo_bypass mode!

Starting kernel ...

Uncompressing Linux... done, booting the kernel.

Booting Linux on physical CPU 0x0

Linux version 3.14.28-1.0.0_ga+g91cf351 (roberto@dragon.tekno-soft.it) (gcc version 4.9.2 (GCC) ) #1 SMP PREEMPT Fri Jul 3 12:43:06 CEST 2015

CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d

CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

Machine model: Voneus i.MX6 SoloX Domus ARM2 Board

bootconsole [earlycon0] enabled

cma: CMA: reserved 320 MiB at 8c000000

Memory policy: Data cache writealloc

PERCPU: Embedded 8 pages/cpu @8bb3a000 s8896 r8192 d15680 u32768

Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048

Kernel command line: console=ttymxc0,115200 root=/dev/mmcblk3p2 rootwait rw earlyprintk

PID hash table entries: 2048 (order: 1, 8192 bytes)

Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)

Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)

Memory: 176704K/524288K available (7213K kernel code, 394K rwdata, 6196K rodata, 328K init, 428K bss, 347584K reserved, 0K highmem)

Virtual kernel memory layout:

    vector  : 0xffff0000 - 0xffff1000   (   4 kB)

    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)

    vmalloc : 0xa0800000 - 0xff000000   (1512 MB)

    lowmem  : 0x80000000 - 0xa0000000   ( 512 MB)

    pkmap   : 0x7fe00000 - 0x80000000   (   2 MB)

    modules : 0x7f000000 - 0x7fe00000   (  14 MB)

      .text : 0x80008000 - 0x80d20678   (13410 kB)

      .init : 0x80d21000 - 0x80d732c0   ( 329 kB)

      .data : 0x80d74000 - 0x80dd6ac0   ( 395 kB)

       .bss : 0x80dd6acc - 0x80e41d9c   ( 429 kB)

SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1

Preemptible hierarchical RCU implementation.

        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.

RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1

NR_IRQS:16 nr_irqs:16 16

L310 cache controller enabled

l2x0: 16 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x32030000, Cache size: 256 kB

Here is my current DCD:


* Copyright (C) 2014 Freescale Semiconductor, Inc.


* SPDX-License-Identifier: GPL-2.0+


* Refer docs/README.imxmage for more details about how-to configure

* and create imximage boot image


* The syntax is taken as close as possible with the kwbimage


#define __ASSEMBLY__

#include <config.h>

#include "asm/arch/mx6-ddr.h"

#include "asm/arch/iomux.h"

#include "asm/arch/crm_regs.h"

/* image version */



* Boot Device : one of

* spi/sd/nand/onenand, qspi/nor










PLUGIN board/voneus/domus-imx6sx/plugin.bin 0x00907000



CSF 0x2000


/* Enable all clocks */

DATA 4 CCM_CCGR0  0xffffffff

DATA 4 CCM_CCGR1  0xffffffff

DATA 4 CCM_CCGR2  0xffffffff

DATA 4 CCM_CCGR3  0xffffffff

DATA 4 CCM_CCGR4  0xffffffff

DATA 4 CCM_CCGR5  0xffffffff

DATA 4 CCM_CCGR6  0xffffffff

// DATA 4 0x020C4084 0xffffffff     what is this????

/* IOMUX */


DATA 4 MX6_IOM_GRP_DDR_TYPE 0x000c0000 /* DDR3 */

DATA 4 MX6_IOM_GRP_DDRPKE   0x00000000

/* CLOCK */

DATA 4 MX6_IOM_DRAM_SDCLK_0 0x00000030 /* 43 Ohm */


DATA 4 MX6_IOM_DRAM_CAS     0x00000020 /* 60 Ohm */

DATA 4 MX6_IOM_DRAM_RAS     0x00000020 /* 60 Ohm */

DATA 4 MX6_IOM_GRP_ADDDS    0x00000020 /* 60 Ohm */


DATA 4 MX6_IOM_DRAM_RESET   0x00000020

DATA 4 MX6_IOM_DRAM_SDBA2   0x00000000

DATA 4 MX6_IOM_DRAM_SDODT0  0x00000020

DATA 4 MX6_IOM_DRAM_SDODT1  0x00000020

DATA 4 MX6_IOM_GRP_CTLDS    0x00000020


DATA 4 MX6_IOM_DDRMODE_CTL  0x00020000

DATA 4 MX6_IOM_DRAM_SDQS0   0x00000028

DATA 4 MX6_IOM_DRAM_SDQS1   0x00000028

DATA 4 MX6_IOM_DRAM_SDQS2   0x00000028

DATA 4 MX6_IOM_DRAM_SDQS3   0x00000028

/* DATA */

DATA 4 MX6_IOM_GRP_DDRMODE  0x00020000

DATA 4 MX6_IOM_GRP_B0DS     0x00000028

DATA 4 MX6_IOM_GRP_B1DS     0x00000028

DATA 4 MX6_IOM_GRP_B2DS     0x00000028

DATA 4 MX6_IOM_GRP_B3DS     0x00000028

DATA 4 MX6_IOM_DRAM_DQM0    0x00000028

DATA 4 MX6_IOM_DRAM_DQM1    0x00000028

DATA 4 MX6_IOM_DRAM_DQM2    0x00000028

DATA 4 MX6_IOM_DRAM_DQM3    0x00000028

/* Calibrations */

/* ZQ */

DATA 4 MX6_MMDC_P0_MPZQHWCTRL   0xa1390003

/* write leveling */

DATA 4 MX6_MMDC_P0_MPWLDECTRL0  0x00220023


/* DQS Read Gate */

DATA 4 MX6_MMDC_P0_MPDGCTRL0    0x41480144

DATA 4 MX6_MMDC_P0_MPDGCTRL1    0x01380130

/* Read/Write Delay */


DATA 4 MX6_MMDC_P0_MPWRDLCTL    0x34363638

/* read data bit delay */

DATA 4 MX6_MMDC_P0_MPRDDQBY0DL  0x33333333

DATA 4 MX6_MMDC_P0_MPRDDQBY1DL  0x33333333

DATA 4 MX6_MMDC_P0_MPRDDQBY2DL  0x33333333

DATA 4 MX6_MMDC_P0_MPRDDQBY3DL  0x33333333

/* Complete calibration by forced measurment */

DATA 4 MX6_MMDC_P0_MPMUR0       0x00000800

/* MMDC init */

/* in DDR3, 32-bit mode, only MMDC0 is initiated */

DATA 4 MX6_MMDC_P0_MDPDC        0x0002002d

DATA 4 MX6_MMDC_P0_MDOTC        0x00333030

DATA 4 MX6_MMDC_P0_MDCFG0       0x676b52f3

DATA 4 MX6_MMDC_P0_MDCFG1       0xb66d8b63

DATA 4 MX6_MMDC_P0_MDCFG2       0x01ff00db

DATA 4 MX6_MMDC_P0_MDMISC       0x00011740

DATA 4 MX6_MMDC_P0_MDSCR        0x00008000

DATA 4 MX6_MMDC_P0_MDRWD        0x000026d2

DATA 4 MX6_MMDC_P0_MDOR         0x006b1023

DATA 4 MX6_MMDC_P0_MDASP        0x0000007f

DATA 4 MX6_MMDC_P0_MDCTL        0x83190000

/* Initialize MT41K128M16JT-125 */

/* MR2 */

DATA 4 MX6_MMDC_P0_MDSCR        0x04008032

/* MR3 */

DATA 4 MX6_MMDC_P0_MDSCR        0x00008033

/* MR1 */

DATA 4 MX6_MMDC_P0_MDSCR        0x00048031

/* MR0 */

DATA 4 MX6_MMDC_P0_MDSCR        0x05208030

/* DDR device ZQ calibration */

DATA 4 MX6_MMDC_P0_MDSCR        0x04008040

/* final DDR setup, before operation start */

DATA 4 MX6_MMDC_P0_MDREF        0x00000800

DATA 4 MX6_MMDC_P0_MPODTCTRL    0x00011117

DATA 4 MX6_MMDC_P0_MDSCR        0x00000000


Register MMDC_MAARCR is not normally programmed by the initialization script. Freescale recommends leaving it with default values.

This is an advisory to customers who decide to change some of the fields in this register.

A bug has been found with the ARCR_GUARD field. It should always be left programmed to the default 0x0 value. If programmed to a different value, the behavior is unpredictable.

My kernel freeze at this same line.

How did you solve your problem?


Hi Florian,

yes! Indeed. I've posted my DCD in another thread. Have a look to it.

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Last update:
‎06-24-2015 10:18 PM
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