i.MX 91 - LPDDR4 Memory Compatibility Guide

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The purpose of this document is to provide extended guidance for the selection of compatible LPDDR4 memory devices that are supported by the i.MX 91 series of processors. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs.

Memory devices with binary densities (e.g., 1 GB, 2 GB, 4 GB) are preferred because they simplify memory management by aligning with system addressing schemes and reducing software complexity.

LPDDR4 - Maximum Supported Densities

SoC	Max Data bus width	Maximum density	Assumed memory organization	Notes
i.MX 91 (i.MX 91xx)	16-bit	16 Gb / (2 GB)	single rank, single channel device with 17-row addresses (R0 - R16)	1, 2, 3

LPDDR4 - List of Validated Memories

The validation process is an ongoing effort - regular updates of the table are expected.

SoC	Density	Memory Vendor	Validated Memory Part#	Notes
i.MX 91	16 Gb / (2 GB)	Micron	MT53E1G16D1FW-046 AAT:A MT53E1G16D1ZW-046 AAT:C	5
	2 Gb / (256 MB)	Winbond	W66BP6NBHAHJ	4
	8 Gb / (1 GB)	Nanya	NT6AN512M16AV-J1I
	4 Gb / (512 MB)	Nanya	NT6AN256M16AV-J1I	4
	8 Gb / (1 GB)	ISSI	IS43LQ16512B-046BLI	4
	12 Gb / (1.5 GB)	Micron	MT53E768M16D1ZW-046	4
	16 Gb / (2 GB)	Intelligent Memory	IMAG16L4KBBG	4
	2 Gb / (256 MB)	Nanya	NT6AN128M16AV-J1	4
	4 Gb / (512 MB)	UniIC	SCB11N4G160BF-04ZI	4
	4 Gb / (512 MB)	ISSI	IS43LQ16256B-053BLI	4
	4 Gb / (512 MB)	Winbond	W66CP6RBHAHJ	4

Note: This device supports operation with LPDDR4 memories only. LPDDR4x operation is not supported. 
Dual‑mode memories that support both LPDDR4 and LPDDR4x are allowed as long as the device can operate in LPDDR4 mode, 
including using LPDDR4 I/O voltage levels and initialization sequences.

NOTE: LPDDR4 devices from certain memory vendors may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low-speed operation is planned in the use case, please consult with the memory vendor about the configuration aspects and possible customization of the memory device so correct functionality is ensured.

Note 1:

The numbers are based purely on the IP documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, SoC reference manual and on the JEDEC standards JESD209-4B (LPDDR4). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.

Note 2:

Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification).

Note 3:

The SoC also supports dual rank single channel devices therefore, 16Gb/2GB density can be also achieved by using a dual rank single channel device with 16-row addresses (R0 - R15).

Note 4:

The memory part number did not undergo full JEDEC verification however, it passed all functional testing items.

Note 5:

The memory part number is not recommended for new designs and superseded by a new part number