Connects - Training Material

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Learn how to move from physical to virtual network functions (VNFs) on ARM QorIQ platforms using KVM virtual machines and Docker containers with native DPAA2 and virtual virtio devices. Leverage packet processing, crypto acceleration and advanced offloads from DPDK/ODP and Linux native guest applications. Connect VNFs through virtual switching either using optimized user space implementations or offloading datapath into DPAA2 Advanced IO Processor. Make use of the switching functions provided by DPAA2 integrated Edge Virtual Bridge and L2 Switch. Leverage OPNFV integration and take advantage of distributed VNFs via Service Function Chaining.

This presentation provides an overview of the new toolchain to support the S32 platform of MCUs and application processors, this includes an IDE with new project generation, extensive collateral for ease of use and getting started as well as the next-generation Debugger tools, a new Flash tool specifically design for the S32 platform, the S32 configuration tool plus numerous software products integarted into the toolchain for ease of customer use.

NXP’s latest and most powerful Microprocessor requires the latest and fastest memories to keep it running efficiently. During this session, we will discuss the new memories supported on the new i.MX 8 processor family. For DRAM, this will include DDR4 and Low Power DDR4. For non-volatile memory this will include Octal SPI NOR (XccelaTM Flash) which offers up to 400MB/s as well as the latest eMMC 5.X devices that also support high speeds. These devices are offered with Commercial, Industrial or Automotive temperature and quality ratings. I will include a section on packaging technologies that can provide designers with innovative ways to reduce size. These include Package on Package and Multi-Chip Packages. This session will provide designers with the tools necessary to create state-of-the-art i.MX 8 systems. Micron will be giving away 2-1/2” 120GB SSDs to the first 50 attendees of this session.

Join this session to understand the breakthrough security features integrated in the recently launched LPC5500 MCU Family. Along with Arm® TrustZone technology the LPC5500 SRAM PUF based key management makes security easy to use and easy to deploy. This session will start off by introducing the scope of securing a smart connected device. It will explain the need for addressing device life cycle in a scalable way that is easy to use and easy to deploy. Then it will detail the protected key management achievable when using LPC5500 with MCUXpresso Software & Tools.

In this class, participants will learn how to leverage model-based design technology (MATLAB/Simulink) to quickly develop motor control algorithms for BLDC, ACIM, and PMSM motors using NXP S32K MCUs on the S32K144 automotive reference platform. Learn the basics of the motor control toolbox to generate C-code from simulation models. The toolbox will be utilized demonstrating peripheral driver blocks, optimized automotive math/motor control blocks, software and processor in the loop techniques for algorithm verification, as well as other utilities for MCU profiling and algorithm development.

Learn how NXP provides support for ODP and DPDK without sacrificing performance. Learn how we're leveraging specific acceleration advantages of the NXP data plane architectures, such as packet IO, classification, scheduling, crypto, etc. This session will provide a comparative analysis and evolution of both of these open-source, platform independent and vendor-neutral standard APIs for optimized packet processing and traditional networking services in user space. It will help you choose the right API for your project, based on design requirements. We will also cover how the ODP and DPDK can provide the necessary infrastructure for virtualized environments.

Many people involved in the electronics industry need a basic knowledge of semiconductor components in order to understand issues like manufacturing cycle time, semiconductor fab consolidation and failure analysis results. This session is geared towards a non-technical audience and gives a high-level overview of semiconductor devices and how they are made. The lecture begins with a brief overview of how semiconductor devices work. The bulk of the presentation describes the generic manufacturing flow for semiconductor devices with an emphasis on the complexity of the equipment/facilities used and the process time required.

In the last 10 years, Green Hills has observed carmaker and Tier 1 customers expand from the traditional segments of powertrain, airbags and braking ECUs into graphics-rich dashboards, open source operating sytems and the secure Connected Car. A leading requirement is ECU consolidation while keeping ASIL safety intact. This requires the run-time architecture to safety and securely run guest operating systems Linux or Android on the same single core (or across multiple cores as SMP) alongside safety or security-critical applications like instrument clusters, gateways, V2X and ADAS. Here, we'll take a closer look at the customer’s pain points and goals, and we’ll summarize various industry solutions, including the INTEGRITY Multivisor secure hypervisor.

The number of ECUs in a car is increasing dramatically on a year by year basis. Modern cars are starting to introduce the concept of centralizing multiple domains (Infotainment, ADAS, etc.) in a single ECU and separate them using technologies like virtualization, multicore or multiple SOCs. Although separated, these entities need to communicate and implementing a software communication solution which is scalable, portable, open and easy to program is key to offering a complete software enablement to our customers. This session will present NXP software solution for communication within a domain and between domains controllers in an ECU.

This course will provide an in-depth system analysis of High Voltage (HV) Electric. We review how the MCU, GDIC and IGBTs function individually and as a system. We will discuss EV and HEV power systems and components for achieving a highly efficient and safe HV motor drive. Using system block diagrams and oscilloscope screen shots of NXP’s new HV IGBT GDIC, the GD3100, and Fuji GEN 7 IGBT modules as we will consider how to achieve smaller, more efficient and lower cost HV inverter designs. We will review SPI interface programmability that enables any IGBT to be tuned for maximum efficiency, thermal design considerations, layout considerations, power budget assessment, power up sequencing, managing short circuit faults, temperature monitoring and advanced features achieve system ASIL level D and ISO26262 certification.

Ethernet adoption in new OEM platforms is accelerating, as a result of increased media, communication, and ADAS streams between different end points in vehicles. The required Quality of Service and synchronization is typically achieved through the implementation of Audio Video Bridging (AVB) specifications, or derivatives of AVB. NXP has a unique position in the market given our capability to offer a full solution for AVB in the car, from end points (MPUs as well as MCUs), PHYs, switches, plus the needed software stacks. In addition, the software stacks are full featured, including critical but often initially forgotten components such as Media Clock Recovery. Get an introduction to the basis of the AVB technology, and how NXP can help you deploy AVB in your products.

Connects - Training Material

Connects - Training Material

Training Sessions Material

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