i.MX RT has a flexible external SPI Flash interface, which supports all existing SPI protocols. However, Serial Flash products may vary in READ performance due to the number of I/O, command protocols and the maximum frequency. Serial Flash Read performance has a direct impact on the system bootup time as well as code execution efficiency. In an advanced system design where system code is shadowed from Flash to DRAM, the initial boot time depends on the data transfer time from Flash to DRAM. In a cost-efficient system design, DRAM is reduced or eliminated since the processor will be able to fetch execution instructions directly from the Flash to the internal cache. During code fetching, a fixed length of data (typically 32- or 64-Byte) is read out from the flash. Shortening the overall 32-Byte or 64-Byte Read time will greatly reduce processor’s wait cycle, leading to improvement on XiP efficiency.