When to improve kernel booting using hibernation [1], I found kernel initialized each component [2] took too much time. One solution is to remove unnecessary module to save time. Another approach is to delay those modules until user space up. Then it won’t lost some features just because hopes to gain benefit on booting speed. This is very useful since hibernation’s trigger point is at the late_initcall [3]. Kernel doesn't need do much module initialize since hibernate will restore those module status later. The detailed implementation is in the attached patch. [1]: hibernation is a technique to store system memory content to storage. Then the device can be shutdown and read the content back after power on. [2]: component means subsystem or driver. [3]: Consult kernel/power/hibernate.c, software_resume

Background Configure Trace32 Attach to SCFW with Lauterbach Snooping Perf Examples Example 1 : Snoop a function call (or a variable) Example 2: MonitorFrame Per Second Example 3: Monitor Frame Per Second and rendering size Background None of my automotive have trace pins on their board. Trace is consequently not possible. Anyway you can do "Snooping" with your Lauterbach JTAG probe. Snooping just send data as fast as possible. In the following example I will Snoop the i.MX8X' SCFW, notice I do not have the sources (except board.c) but I have the elf file (thus I have debug info with functions names for instance). Notice Snooping is available on all MCU/MPU with JTAG.   In my case I used it for the first time in 2015 on Vybrid, our first heterogeneous dual core (Cortex-A5 & Cortex-M4) with no XRDC... My customer has sent the final product with a JTAG connector and flashed SW product to me. I had a laconic comment: "software is done all around the world in UK, India and the US, when we flash all the software the Vybrid Reset for some version, we don't have the sources for this specific software we have flashed in this product. Good Luck". In this case snooping on both core at the same time was the only solution for me... At the end I have discovered (thanks to the last PC addresses before the crash) the cortex-A5 was deconfiguring a pin of the QSPI flash interface on which the M4 was eXecuting In Place (XiP). Configure Trace32 When your Trace32 is open, CPU>>System Settings... menu and configure the JtagClock as fast as possible (here 40MHz) to have fast data streaming: go in Trace>>Configuration menu Select "SNOOPer" Select to stream the Pointer Counter thus select the mode "PC" Pass to State to "Arm" You can increase also the SIZE of the buffer Launch your code: Attach to SCFW with Lauterbach In Trace32, CPU>>System Settings, chose IMX8QXP-SCU: And then do an "Attach": Then yu should see your SCU core running: Snooping And break your code, your "used" field " should be filled: Open Trace>>List>>Default Click on "Chart" On the trace list you can see the sampling rate: around 48µs in our case. It means you may (almost) not see functions lasting less than 48µs (depends when it is sampled), or you'll see it sometimes. But for performance analysis it can be useful to see which function is too slow (rather then instrument the code), but as I mentioned in my case function has to last more than 48µs! Perf You can also get Performance analysis. But keep in mind if your function is faster than 48µs in my case, the result will not be accurate! Go in Perf>>Perf Configuration (it can also be done un real time with Perf>>Perf List Dynamic)... and select "Snoop": Then put the State in "Arm" and click on "List" to open the "List Window" Launch your code and stop it. In the "List" window you'll see all the function ranked according to their usage occurrence (my SCFW is almost always in sleep!) Examples Example 1 : Snoop a function call (or a variable) With Snooping you cannot trace a function calls. To do that I add a global variable in the function. You'll have a little overhead due to that. I will use an i.MXRT1170 with the SDK 2.6.1. I have built the Tiger example (vglite). April 4th 2020: i.MXRT1170 is not public, meaning not officially supported by Lauterbach. Please follow the instruction in my SharePoint folder (if the link disappears, it may signify i.MXRT1170 is supported) to add support of the i.MXRT1170. https://nxp1-my.sharepoint.com/:f:/g/personal/vincent_aubineau_nxp_com/Ej8ID8mXaNZPnVgTWgYgqHQBzR0XcE0K4sl1WusR3UMBnw?e=…  I want to know the framerate. To do that I have to monitor the redraw() calls. What I do, is I put the "n" variable as global. Trace>>Configuration ... Chose "memory" and "changes" (to log only when the variable is changing): Then then click on select... and "i" Search for "n" variable and select it: Launch your software and then do a break. Click on "List": You have the list of your function call (as you can see it is not always the same), in the "ti. call" you have the duration between 2 call (keep in mind the function must not be called at high frequency: If you click on "draw", you can display the variable values (click on  to scale it): Example 2: Monitor Frame Per Second I can also monitor the fps if I pass "time" variable global: And you can have a reprensentation of you fps (notive I have unchecked "Changes" to have an easy to intrepret curve Example 3: Monitor Frame Per Second and rendering size Results often depends of several variables. If you display 2 variables on 1 display window, if the 2 variable does not have the same range, it is not easy to observe. The best solution I have found in this case is to have 2 "Draw" Windows. Add the 2 variables in the "SElect" field ("time" and "ScaleCount", beware, it is case sensitive). Launch your code, and stop it after a while. Then right click on the "time" and "ScaleCount" variable in your code to display 2 "Draw" window: Thus you have 2 "Draw" windows, and you see FPS depends on rendering size... logical!  

Hi All, The new Android JB4.3_1.1.0-GA release is now available on www.freescale.com ·         Files available           Name Description IMX6_JB43_110_ANDROID_DOCS i.MX   6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Android   jb4.3_1.1.0 BSP Documentation. Includes Release Notes, User's Guide, QSG and   FAQ Sheet. IMX6_JB43_110_ANDROID_SOURCE_BSP i.MX   6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Android   jb4.3_1.1.0 BSP, Documentation and Source Code for BSP and Codecs. IMX6_JB43_110_ANDROID_DEMO_BSP i.MX   6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Android   jb4.3_1.1.0  BSP Binary Demo Files IMX6_JB43_110_AACP_CODEC_CODA AAC   Plus Codec for i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX   6Sololite Android jb4.3_1.1.0 ·         Target HW boards o   i.MX6DL  SABRE SD board o   i.MX6Q  SABRE SD board o   i.MX6DQ SABRE AI board o   i.MX6DL SABRE AI board o   i.MX6SL EVK board ·         Release Description i.MX Android jb4.3_1.1.0 release includes all necessary codes, documents and tools to assist users in building and running Android 4.3 on the i.MX 6Quad, i.MX 6DualLite and i.MX6SoloLite hardware board from the scratch. The prebuilt images are also included for a quick trial on Freescale i.MX 6Quad and i.MX 6DualLite SABRE-SD Board and Platform, i.MX 6Quad and i.MX 6DualLite SABRE-AI Board and Platforms and i.MX6SoloLite EVK Board and Platforms. This release includes all Freescale porting and enhancements based on Android open source code. Most of deliveries in this release are provided in source code with the exception of some proprietary modules/libraries from third parties. ·         What's in this release         Android Source Code Patch All   Freescale i.MX specific patches (apply to Google Android repo)   to enable Android on i.MX based boards. For example Hardware   Abstraction Layer implementation, hardware codec acceleration,   etc. Packed in   android_jb4.3_1.1.0-ga_source.tar.gz Documents The   following documents are included in android_jb4.3_1.1.0-ga_docs.tar.gz: ●   i.MX Android jb4.3_1.1.0-ga Quick Start: A   manual explains how to run android on i.MX board by using prebuilt images. ●   i.MX Android jb4.3_1.1.0-ga User Guide: A   detailed manual for this release package. ●   i.MX Android jb4.3_1.1.0-ga FAQ: A document lists   “Frequently Asked Questions”. ●   i.MX Android Codec Release Notes: A   document to describes the Freescale Codec Package ●   i.MX Android Wi-FI Display Sink API Introduction A   document to describes how to use i.MX Android Wi-Fi Display Sink API ●   i.MX6 G2D API User Guide document to introduce how to use i.MX6 G2D API for   2D BLT usage ●   i.MX Android jb4.3_1.1.0-ga Release Note A   document to introduce the key updates and known issues in this release. Tools Tools   in android_jb4.3_1.1.0-ga_tools.tar.gz ●  MFGTool. Manufacturing tools for i.MX platform ●  USB tethering windows .inf driver configure file.tool/tetherxp.inf Prebuilt Images You   can test Android on i.MX with prebuilt image on i.MX board before building   any code. ● android_jb4.3_1.1.0-ga_image_6qsabresd.tar.gz: Prebuilt   images for the SABRE-SD board. ●  android_jb4.3_1.1.0-ga_image_6qsabreauto.tar.gz: Prebuilt   images for the SABRE-AI board. ●  android_jb4.3_1.1.0-ga_image_6slevk.tar.gz: Prebuilt images for the 6SL   SABRE-AI board. All   prebuilt images are in another package. See "i.MX Android jb4.3_1.1.0-ga   Quick Start" and "i.MX Android jb4.3_1.1.0-ga User Guide" to   understand which image should be used in which case. ·         Known issues For known issues and limitations please consult the release notes

When I am planing to develop some features in Uboot, I found it has lots limitation without interrupt. For example, to have camera preview in Uboot. Polling in Uboot results non sync when camera preview and hard to keep code simple and clean. I decided to take some time survey interrupt and it is time to share it.   This patch (shown as attachment) is to enable the interrupt. It also has the sample code to set GPIO interrupt as well. The test below showed Uboot can get the interrupt when pressing Volume up key. Special thanks for Anson Huang for patient discussing with me on this.   irqinfo is the command to enable Volume up interrupt. The log do_irq is print when Uboot got the interrupt.   Original Attachment has been moved to: 0001-Enable-interrupt-on-i.MX6Q-SabreSD.patch.zip

Issue: During DDR3 Burst Write, the DQS strobe signal must be driven low for a minimum of 0.3 x cycle period on the last data clock cycle before it is released. This ensures sufficient time for the write to be strobed correctly. When measuring this timing parameter, it has often been found to be too short. This may be contributing to write errors on customer boards, depending on the signal layout used by the board. Root Cause: The internal DQS strobe enable signal is controlled by the MMDC, which is tied to the SDCLK clock signal. But the DQS strobe signal can be delayed in the MMDC to match different SDCLK trace lengths by using Write Leveling parameters to ensure the the DQS strobe edge reaches the DDR3 device at the same time the SDCLK edges reaches the device. If the write level delay is too long, the MMDC can crop the end of the DQS strobe signal too short, causing a violation of the Write Post Amble Delay timing specification and potentially leading to  write errors. How much delay in the Write Leveling parameter would cause this problem? The Reference Manual states that a delay around half a cycle may cause problems, but testing on some boards indicates that delays even as short as 1/4 a cycle could cause violations of the Write Post Amble Delay. Solution: The MMDC was designed with the ability to add extra time to the strobe enable period during write procedures. This parameter is referred to as Write Additional Latency. It is found in the MMDCx_MDMISC register and the field is labeled as WALAT. Incrementing the value of this register field by one adds a full clock cycle delay to the Write Post Amble period, and ensures enough time at the end of a burst write to guarantee a correct write. There is no maximum value to Write Post Amble Delay. Setting WALAT = 1 (or larger if WL parameters are larger) will cause a small hit in overall performance, but will add to the reliability of write operations, particularly on boards that require larger WL parameter settings.

     

Introduction. In some cases, such as development stages, testing, validate flash process from zero, etc. It is needed to erase the eMMC storage device, here is described the process and the required equipment: Required equipment. i.MX93 FRDM board (this is the selected board for this post, it works for others). Debug USB-C cable. Data USB-C cable. Micro SD (16GB recommended). Personal computer. How to erase the eMMC? This method will use another boot source (Micro SD) to erase the eMMC so, it is needed to flash the Micro SD with at least the bootloader (U-boot), you can use a prebuilt image for the EVK board, it can be downloaded from the following link. But, in the case of i.MX93 FRDM board, there is no pre-built image available and needs to be build: The FRDM-IMX93 BSP release is based on i.MX SW 2024 Q3 release with Yocto Project 5.0 (Scarthgap). To build FRDM-IMX93 image from source code, please first check i.MX Yocto Project User's Guide to get familiar with Yocto project and Yocto build. Then please follow below steps to build image for FRDM-IMX93. 1. Download i.MX SW 2024 Q3 BSP Release: $ repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-scarthgap -m imx-6.6.36-2.1.0.xml $ repo sync 2. Integrate FRDM-MX93 layer into Yocto code base: $ cd ${MY_YOCTO}/sources $ git clone https://github.com/nxp-imx-support/meta-imx-frdm.git 3. Yocto Project Setup: $ MACHINE=imx93frdm DISTRO=fsl-imx-xwayland source sources/meta-imx-frdm/tools/imx-frdm-setup.sh -b frdm-imx93 4. Build images: $ bitbake imx-image-full The flashing process can be consulted here. Once the board is flashed, we need to change the boot switches to boot from Micro SD and turn-on the board. To debug this process, we will use Tera Term terminal with the board connected from the Micro USB debug cable to the PC and select the next configuration: Please verify that you are selecting the corresponding COM for Cortex-A debug. After boot we need to press a key, and the board will enter to U-boot. So, then we need to select the partition of the eMMC with the next command: u-boot=> mmc dev <storage device> <partition> In the case of the eMMC, the storage device corresponds to the device "0" and if the device has an image flashed into the eMMC e.g. Linux, the device will have three partitions from 0 to 2. The next command will select the eMMC and the boot partition area: u-boot=> mmc dev 0 0 switch to partitions #0, OK mmc0(part 0) is current device Depending on the device, image, etc. This partition size can vary so, we need to know how many blocks it has. We can use the next command that will let us know the max address value that is assigned to this partition by getting an error on the address that is out of the range. u-boot=> mmc read ${loadaddr} 0x7fffffff 1 MMC read: dev # 0, block # 2147483647, count 1 ... MMC: block number 0x80000000 exceeds max(0x1d5a000) 0 blocks read: ERROR Now, with this information, we are able to erase the entire partition with the next command: u-boot=> mmc erase 0 0x1d5a000 MMC erase: dev # 0, block # 0, count 30777344 ... 30777344 blocks erased: OK As mentioned before, the device has multiple partitions so, this process needs to be done in each partition Boot area Partition. User Area 1 Partition. User Area 2 Partition. But the process is the same, let's change the partition to User Area 1: u-boot=> mmc dev 0 1 switch to partitions #1, OK mmc0(part 1) is current device  Confirm the size of the partition: u-boot=> mmc read ${loadaddr} 0x7fffffff 1 MMC read: dev # 0, block # 2147483647, count 1 ... MMC: block number 0x80000000 exceeds max(0x2000) 0 blocks read: ERROR And erase it: u-boot=> mmc erase 0 0x2000 MMC erase: dev # 0, block # 0, count 8192 ... 8192 blocks erased: OK And let's finish with User Area 2 Partition: u-boot=> mmc dev 0 2 switch to partitions #2, OK mmc0(part 2) is current device u-boot=> mmc read ${loadaddr} 0x7fffffff 1 MMC read: dev # 0, block # 2147483647, count 1 ... MMC: block number 0x80000000 exceeds max(0x2000) 0 blocks read: ERROR u-boot=> mmc erase 0 0x2000 MMC erase: dev # 0, block # 0, count 8192 ... 8192 blocks erased: OK With this done, the eMMC is completely erased and you can confirm it by turning off the board, change the boot switched to eMMC, remove the SD card and turn-on the board.  Since there is not a bootable image into the boot source, the board will jump to serial download mode and you can verify connecting the USB data cable to the board and run the next command in UUU: Conclusion. Erasing the eMMC of the board is optional step in your development stage but also helpful for testing or system recovery (e.g. test manufacture mode). By using a Micro SD you can access to the eMMC and do all the modifications in the partitions that you want without issues. With this you can go to a clean storage state into the boot device and test a new image from scratch or test recovery methods in your design.

On this tutorial we will review the implementation of Flutter on the i.MX8MP using the Linux Desktop Image. Please find more information about Flutter using the following link: Flutter: Option to create GUIs for Embedded System... - NXP Community Requirements: Evaluation Kit for the i.MX 8M Plus Applications Processor. (i.MX 8M Plus Evaluation Kit | NXP Semiconductors) NXP Desktop Image for i.MX 8M Plus (GitHub - nxp-imx/meta-nxp-desktop at lf-6.1.1-1.0.0-langdale) Note: This tutorial is based on the NXP Desktop Image with Yocto version 6.1.1 – Langdale. Steps: 1. First, run commands to update packages. $ sudo apt update $ sudo apt upgrade 2. Install Flutter for Linux using the following command. $ sudo snap install flutter --classic 3. Run the command to verify the correct installation. $ flutter doctor With this command you will find information about the installation. The important part for our purpose is the parameter "Linux toolchain - develop for Linux desktop". 4. Run the command “flutter create .” to create a flutter project, this framework will create different folders and files used to develop the application.  $ cd Documents $ mkdir flutter_hello $ cd flutter_hello $ flutter create .​ 5. Finally, you can run the “hello world” application using: $ flutter run Verify the program behavior incrementing the number displayed on the window.  

Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response.   These are the detailed programming aids for the registers associated with DRAM initialization (DDR3 and LPDDR2) of the MX6DQP (also known as Rev 2 or Dual/Quad Plus), and covers the Sabre_SD boards and DDR3 based Auto Infotainment board. The last work sheet tab in the tool formats the register settings for use with the ARM RealView debugger (.inc) and the DDR Stress Test. It can be manually converted, by the user, to the DS5 .ds format or to a DCD file format used by uboot or other. The programming aids were developed based on NXP development boards and can be customized by the user for their board design. This tool serves as an aid to assist with programming the DDR interface of the MX6DQP and is based on the DDR initialization scripts developed by the R&D team and no guarantees are made by this tool. The following are some general notes regarding this tool: • Refer to the "How To Use" tab in the tool as a starting point to use this tool. • This tool may be updated on an as-needed basis for bug fixes or future improvements.  There is no schedule for aforementioned maintenance. • The MX6DQP adds a new third party IP called the NoC. The programming for these registers are automatically updated in the tool given a set of user input MMDC parameters and should not be modified manually.

This link contains the scripts, U-boot commands, and patch code shown on the application note AN5409 titled 'i.MX6 Dual/6 Quad Power Consumption Measurement'.

Quaestion: What does exactly the RNG_TRIM after burning the SRK hash table? There is no such thing on the former i.MX HAB procedure. What would a random generator stuff bring here? Additionnally, there is the possibility to lock the SRK shadow register via an OTP bit. Is it recommeneded to lock it? if not, is it really possible to change the SRK hash value by modofying the shadow register value before performing the SRK hash key check in a HAB boot process? One last question: the PKI requires the user to enter a certificate lifetime. Does that really mean that openssl will refuse generating new signatures once the certificates lifetime is expired? Answer: 1. The intent of the of the RNG_TRIM fuses is for Freescale to essentially extendthe amount of time the RNG4 in CAAM has to generate entropy.  The longer this period the more likely it is that RNG4 will generate entropy that will pass its internal statistical tests.  The reason for the fuses is HAB (in the Closed configuration only) instantiates the RNG by default and needs some external indication on how to progran the RNG4 in CAAM to ensure the internal HW statistical tests will pass.  This was to allow the RNG to be useable by application code after execution has left the ROM.  However this requires that the RNG_TRIM fuse value be fully characterized across numerous conditions temperature, voltage etc.  This effort is still on going.  For customers performing secure boot (in Closed configuration) we recommend they follow Section 6.3 of http://cache.freescale.com/files/32bit/doc/app_note/AN4581.pdf.  In this case the RNG4 can be instantiated by CAAM driver code which can be easily changed if required. 2. Yes, once the SRK hash is provisioned to the SRK_HASH field it is recommended to blow the corresponding SRK_LOCK fuse.  If the SRK_LOCK fuse is not blown then additional fuses in the SRK_HASH field can be blown.  This will cause devices in the closed configuration to fail to boot.  i.e. "bricking" the device. 3. Please see https://community.freescale.com/message/334186#334186 for the answer to your question on the certificate validity period.

From Android 12, NXP use GKI(Generl kernel image) instead of NXP's kernel code.  This follow up Android ASOP standard. This article described that when customer use Android 12 and later version, they need to pay attention on GKI development, which is different with previous version.

Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response. This is a detailed programming aid for the registers associated with MMDC initialization. The last sheet formats the register settings for use with ARM RealView ICE. It can also be used with the windows executable for the DDR Stress Test. This programming aid was used for internal NXP validation boards.

Overview i.MX6Dual/Quad and i.MX6DualLite supports 32-bit and 64-bit DDR3. Freescale i.MX6 SabreSD board deploys 64bit DDR3 and 64bit DDR3 script is delivered into Linux/Android Software release. This document introduces how to create i.MX6 32bit DDR script based on 64bit DDR script when deploying 32bit DDR on customized board. Changes Set the DSE field in the following iomux registers to 0 - disable unused IO pad to save power: IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 IOMUXC_SW_PAD_CTL_GRP_B4DS IOMUXC_SW_PAD_CTL_GRP_B5DS IOMUXC_SW_PAD_CTL_GRP_B6DS IOMUXC_SW_PAD_CTL_GRP_B7DS IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 Update MMDC registers to reflect 32bit DDR changes: MMDC0_MDASP: Update CS0_END if CS size is changed. MMDC0_MDCTL: set DSIZ to 32 bit MMDC1_MPODTCTRL: Set it as 0 and disable the odt of higher byte Follow "i.MX 6 Series DDR Calibration" Application note to calibrate DDR parameters. Reference One example about 32bit DDR script is located under uboot-imx git ( File: board/freescale/mx6q_sabresd/flash_header.S). Open it and you can see the following script: #if defined CONFIG_MX6DL_DDR3 #if defined CONFIG_DDR_32BIT ... #endif You can refer to it and create your 32bit DDR script.

1 How to build out userdata.img and cache.img The default fsl android  bsp don't support userdata.img and cache.img. You need add the below patch to build  out these images. The hardware for below patch is imx7D. You can adjust your patch according your hardware. diff --git a/imx7/BoardConfigCommon.mk b/imx7/BoardConfigCommon.mk index 14e4881..c207727 100644 --- a/imx7/BoardConfigCommon.mk +++ b/imx7/BoardConfigCommon.mk @@ -61,7 +61,11 @@ BOARD_BOOTIMAGE_PARTITION_SIZE :=  16777216 BOARD_RECOVERYIMAGE_PARTITION_SIZE := 16777216 BOARD_SYSTEMIMAGE_PARTITION_SIZE := 377487360 +BOARD_USERDATAIMAGE_PARTITION_SIZE := 576716800 +TARGET_USERIMAGES_USE_EXT4 := true +BOARD_CACHEIMAGE_PARTITION_SIZE := 69206016 +BOARD_CACHEIMAGE_FILE_SYSTEM_TYPE := ext4 BOARD_FLASH_BLOCK_SIZE := 4096 TARGET_RECOVERY_UI_LIB := librecovery_ui_imx - +TARGET_USERIMAGES_SPARSE_EXT_DISABLED := true 2  How to add  pre-install apk. I add a content pre-app in device/fsl/imx7. helloworld.apk is the added pre-install apk. diff --git a/imx7/pre-app/AnTutuV2.4.apk b/imx7/pre-app/helloworld.apk new file mode 100755 index 0000000..a96003a Binary files /dev/null and b/imx7/pre-app/AnTutuV2.4.apk differ diff --git a/imx7/sabresd_7d.mk b/imx7/sabresd_7d.mk index d7c5c76..11be86c 100644 --- a/imx7/sabresd_7d.mk +++ b/imx7/sabresd_7d.mk @@ -27,7 +27,8 @@ PRODUCT_COPY_FILES += \         device/fsl/common/input/20b8000_kpp.idc:system/usr/idc/20b8000_kpp.idc \         device/fsl/common/input/20b8000_kpp.kl:system/usr/keylayout/20b8000_kpp.kl \         device/fsl/sabresd_7d/audio_policy.conf:system/etc/audio_policy.conf \ -       device/fsl/sabresd_7d/audio_effects.conf:system/vendor/etc/audio_effects.conf +       device/fsl/sabresd_7d/audio_effects.conf:system/vendor/etc/audio_effects.conf \ +       device/fsl/imx7/pre-app/*:data/. 3 What are userdata.img and cache.img for? userdata.img: we need to integrate some customized APKs which should be preinstalled but should be able removed/updated by end user after product delivery. Which means they cannot be installed as system APPs in /system/app folder but User APPs in /data/app folder. At this point, we need compile userimage by ourself. Cache.img: /cache include the content when apk start running. You may storage some special content which app need. I have not find any advantage to pre-build cache.img. Note:      a. The  userdata.img and cache.img's format is sparse ext4 image. You need convert it through simg2img.           The  tool simg2img located at lp5.1_sabresd_7d_4_20/out/host/linux-x86/bin/simg2img           You can use below command to get raw ext4 userdata.img which can be burned into emmc/sd.           out/host/linux-x86/bin/simg2img userdata.img userdata_raw.img     b. BOARD_USERDATAIMAGE_PARTITION_SIZE BOARD_CACHEIMAGE_PARTITION_SIZE define the size of data and cache partition Reference: https://community.freescale.com/docs/DOC-105215

Ftrace is powerful tracing utility embedded in Linux kernel. It provides a very good method for kernel developer to get insights of the kernel behavior. While official kernel doc for ftrace is somehow long and complex, this document provides a quicker and simpler way to get start with ftrace.

This is a simple document for recording some known-how and tips for building up the Windows 10 IoT development environment for i.MX platform. It can only be used as a complement for official document in BSP package (Guide/Release Note/etc.). Applicable for: Windows 10 IoT, i.MX BSP v1.4.1 (date to Nov/2023) Please refer to the PDF attached.

This doc will show: i.MX8DXL EVK board without connect  hardware LCD display, using FreeRDP to share screen to remote PC which is in same network,  PC take this shared screen could  run any command on i.MX8DXL EVK board.   HW: i.MX8DXL EVK board,  PC  SW: i.MX8DXL Linux 5.15.32 BSP release, and code change in this doc   1> i.MX8DXL Linux kernel side, just use imx8dxl-evk-lcdif.dts, but did not connect any LCD display,  so Linux kernel could create related drm device, and weston could be start. But on 8DXL EVK board, ENET1_RGMII_TXD3 and ADMA_LCDIF_D03 pin conflict,  so need code change as 5.15.32-imx8dxl-evk-lcdif.dts.diff.   2> yocto/bld/conf/local.conf, add below line, as freerdp depend on ffmpeg. LICENSE_FLAGS_ACCEPTED+="commercial"   3> For i.MX8DXL,  weston use software pixman render, to use NEON optimization,  pixman need switch to  latest 0.42.0,  enter folder (yocto/bld/tmp/work/armv8a-poky-linux/pixman/1_0.40.0-r0/pixman-0.40.0),  git clone (https://github.com/freedesktop/pixman.git) and checkout to latest 0.42.0:  Also chaneg related build flag at bb file as pixman_0.40.0.bb.diff.     4> Default  freerdp need switch to 2.8.0, enter folder (yocto/bld/tmp/work/armv8a-poky-linux/freerdp/1_2.4.1-r0/git),  git clone (https://github.com/FreeRDP/FreeRDP.git), check out to 2.8.0; And to use neon accelerate freerdp related function, such as color space conversion, image codec encoding ,  need apply patch  freerdp-codechange-neon.diff. And related bb file compile flag change as freerdp_2.4.1.bb.diff     5> bitbake -c compile ffmpeg bitbake -c install ffmpeg   bitbake -c compile pixman  bitbake -c install pixman    bitbake -c compile  freerdp bitbake -c install  freerdp   Copy  generated new libs to default released i.MX8DXL rootfs, make sure ffmeg , pixman, freerdp related libs are  from your build, for example: libfreerdp-client2.so.2 -> libfreerdp-client2.so.2.8.0 libfreerdp2.so.2 -> libfreerdp2.so.2.8.0 libwinpr-tools2.so.2 -> libwinpr-tools2.so.2.8.0 libwinpr2.so.2 -> libwinpr2.so.2.8.0   6> i.MX8DXL Linux rootfs:  file /etc/xdg/weston/weston.ini,  change start-on-startup to true: [screen-share] command=/usr/bin/weston --backend=rdp-backend.so --shell=fullscreen-shell.so --no-clients-resize --rdp-tls-cert=/etc/freerdp/keys/serve start-on-startup=true   7> i.MX8DXL Linux OS, run below cmd: winpr-makecert -path $PWD copy generated files to /etc/freerdp/keys/server.crt and /etc/freerdp/keys/server.key   8> reboot i.MX8DXL EVK board,  make sure  EVK board and PC in the same network; check i.MX8DXL Linux OS , there are two process name as "weston", one process is weston rdp backend to share screen to PC.   9> PC side, get wfreerdp.exe from  https://github.com/FreeRDP/FreeRDP/wiki/Prebuilds PC side run cmd as: wfreerdp.exe /v:ipaddress_of_8DXLEVK     Reference: 1>https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX#design-resources 2>https://github.com/FreeRDP 3>https://github.com/freedesktop/pixman 4>https://github.com/DLTcollab/sse2neon  

Q: Q&A: Where to find IBIS Models on the web? A: In the first figure (FSL driving 100 ohm), the processor is DC coupled to a transmission line and terminated at the far end with a 100-ohm resistor. The results look pretty normal for this. In the other figure, the processor is dc coupled to a transmission line, then ac coupled to another transmission line segment (0.1u) with 50-ohm resistors to ground, and then drives the inputs of an HCSL clock buffer. The results are pretty un remarkable. The top red signal in the trace is one of the IMX6 clock outputs, the first green signal is the other clock output, and the last green signal (from top to bottom that is) is the differential signal seen by the clock buffer. The customer is concerned about the asymmetrical drive of the processor. It looks like LVDS clock outputs do not like to be AC coupled. This simulation resembles the way the clock is handled in the Smart Device schematics where the clock is AC coupled to the reference clock inputs on the PCIE connector. The ibis files were downloaded from the web (21x21_imx6q, consumer variant). So a few updates: I had the customer download the latest duallite IBIS models. Previously they were apparently using the quad/dual models. They are going to update HyperLynx and are going to run a simulation and let me know if they still see the same issue. He said he's using "linesim". Meanwhile he noticed a different problem with the duallite/solo IBIS models. Although the datasheet says LVDDR3 (1.35V) is supported, there is no model for DDR3_L either as input or output. The same model existed in the quad/dual models. Do you know why this option is not in the duallite IBIS models? Thanks! A ctm of mine would like to get the IBIS model with LVDDR3 support on the i.MX6 DL. For mx6-duallite IBIS models for DDR3L memory (1.35V). It'd be great if the models matched the quad version. Please find the new updated IBIS file in website. http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6DL&nodeId=018rH3ZrDRB24A&fpsp=1&tab=Design_Tools_Tab