For more information verify the U-Boot User Manual[1].   First all configure your board IP, your host IP and the gateway IP:   => setenv ipaddr 10.29.244.91   => setenv serverip 10.29.244.27   => setenv gatewayip 10.29.244.27 You don't need to set the gatewayip when using cross'cable! Save this configuration to flash: => saveenv   Download the file to board RAM: => tftp 0x80000000 zImage   Where:   400000 is the memory position where the file will be placed;   zImage is the file that will be downloaded from TFTP server.  

Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response. i.MX 6/7 Family DDR Stress Test  The i.MX6/7 DDR Stress Test Tool is a PC-based software to fine-tune DDR parameters and verify the DDR performance on a non-OS, single-task environment(it is a light-weight test tool to test DDR performance). It performs write leveling, DQS gating and read/write delay calibration features. The tool described on this page cover the following i.MX 6/7 series SoCs: i.MX 6DQP (Dual/Quad Plus) i.MX 6DQ (Dual/Quad) i.MX 6DL/S (Dual Lite/Solo) i.MX 6SoloX i.MX 6SL i.MX 6SLL i.MX 6UL i.MX 6ULL/ULZ i.MX 7D/S i.MX 7ULP Note that the DDR Stress test tool supports the all of the above i.MX SoCs, however, some of the supported i.MX SoCs named in the tool support multiple i.MX SoCs as follows: MX6DQ – when selected, this supports both i.MX 6DQ and i.MX 6DQP (Plus) MX6DL – when selected, this supports both i.MX 6DL and i.MX 6S (i.MX 6DLS family) MX6ULL – when selected, this supports both i.MX 6ULL and i.MX6 ULZ MX7D – when selected, this supports both i.MX 7D and i.MX 7S The purpose of the i.MX 6/7 series DDR Tools is to enable users to generate and test a custom DRAM initialization based on their device configuration (density, number of chip selects, etc.) and board layout (data bus bit swizzling, etc.). This process equips the user to then proceed with the bring-up of a boot loader and an OS. Once the OS is brought up, it is recommended to run an OS-based memory test (like Linux memtester) to further verify and test the DDR memory interface. The i.MX 6/7 series DDR Tools consist of: DDR Register Programming Aid (RPA): i.MX 6/7 Series DDR Tool Release DDR Stress test: Described below There are three options to run the DDR Stress test. Each of these options are provided in the attached zip files. The following is a high-level overview of each option along with the naming convention of the associated zip file: Option 1 GUI based: Run the GUI executable and connect your board to the host PC via USB Archive file: ddr_stress_tester_vX.xx.zip The tool will first need to run a DDR initialization script for the specified i.MX SoC (refer to Load Init Script in the GUI tool).  Example initialization scripts based on NXP's development boards can be found in this zip file under the script folder.  Note, these scripts may need to be modified for your custom board and memory.   Option 2 DDR Stress Tester: JTAG Interface A hardware debugger connected to the board via the JTAG interface is used to download an elf file into the i.MX SoC OCRAM (internal RAM) and then begin execution. Results are shown on the UART serial port (115200-8-n-1). Archive file: ddr_stress_tester_jtag_vX.xx.zip As with the GUI tool, the JTAG/debugger option will first need to run a DDR initialization script for the specified i.MX SoC. Refer to the GUI tool description above for the location of the example scripts (which are found in the ddr_stress_tester_vX.xx.zip file). Note that the scripts are available either in the RealView ICE format (.inc file) or the DS-5 DSTERAM format (.ds). For other debuggers, the user will have to modify the script's command syntax for their specific debugger. This is also true if converting from a RealView Ice (.inc) format to a DS-5 DSTREAM (.ds) format and vice versa. The DDR Stress Tester executable (starting with V2.20) has an auto UART detection feature. If a different UART port for the serial console has been chosen than used on the NXP development tool (EVK, SABRE) specific commands can be added to the DDR initialization script that allows you to configure for the specific UART and then load and run the elf executable. Refer to the FAQ section of this community post and the txt file found in the JTAG archive file for instructions.   Option 3 U-Boot: The boot loader u-boot is running and commands in u-boot are used to download the bin file into SoC OCRAM and begin execution. Results are shown on the UART serial port (115200-8-n-1) Archive file: ddr_stress_tester_uboot_vX.xx.zip When downloading the DDR Stress Test Tool by u-boot, please copy the ddr-test-uboot-jtag-mxxxx.bin to SD card and load it to IRAM using the 'fatload' u-boot command (see notes below when using newer versions of u-boot). For i.MX6, please load the binary to 0x00907000. For i.MX7D, please load the binary to 0x00910000.  It is imperative to first disable the I and D cache in u-boot as shown below as the DDR Stress Test re-configures and re-enables the cache and MMU page table. While this option allows the user to load and run the DDR stress test from u-boot, NXP highly recommends executing the GUI based version for system testing and debugging. The u-boot version is considered a “last resort” for systems in production which may not have USB or JTAG connectivity. The reasons behind this stance are: In the GUI version, the system starts “clean” and uninitialized, whereas u-boot initializes many SoC features outside the knowledge of the DDR stress test and may conflict with the stress test operation When running the u-boot version, the test will overwrite the contents of u-boot residing in DDR, hence the test will overwrite any data in DDR. Once the stress test is loaded and executed, u-boot itself will no longer be accessible. To return to the functionality of u-boot, a system re-boot is required. Newer versions on u-boot do not allow a direct loading of the DDR stress test code from the SD card (boot media) directly to the SoC internal OCRAM (aka IRAM). Hence, the procedure is updated to first load the DDR stress test code into DDR and then copy into OCRAM, as shown in the procedure below: u-boot> dcache off;icache off;fatload mmc 2:1 0x12000000 ddr-test-uboot-jtag-mx6dq.bin;cp.b 0x12000000 0x00907000 0x20000;go 0x00907000 As u-boot initializes many peripherals that may conflict with the operation of the DDR stress test, it is necessary to clock gate these peripherals prior to running the DDR stress test. Hence, it is highly recommended to augment the procedure above as follows: u-boot> dcache off;icache off;fatload mmc 2:1 0x12000000 ddr-test-uboot-jtag-mx6dq.bin;cp.b 0x12000000 0x00907000 0x20000; u-boot> mw 0x020c4068 0x00C0000F; u-boot> mw 0x020c406c 0x00000000; u-boot> mw 0x020c4074 0x3F300000; u-boot> mw 0x020c4078 0x0000F300; u-boot> mw 0x020c407c 0x0F000003; u-boot> mw 0x020c4080 0x000003FC; u-boot> go 0x00907000 Note, in the above procedure, it is recommended to write to each clock gate register in separate commands (refer to commands starting with “mw”). The SoC requires a finite amount of time to gate each clock hence performing this sequence with a new command line write ensures the SoC has time to gate the intended clocks.   Stress Test Revision Features Comments 3.00 Add i.MX 7ULP support in the GUI version Known issues: USB connection is unstable when under USB HUB or some PC environments 2.92 Minor correction with write leveling calibration code error check to avoid a corner case of flagging an error when none have occurred.    2.91 Resolved issue with write leveling calibration code where a race condition in the code may result in the calibration routine not being able to find any delay values.   Only applies to MX6 series SoCs that support DDR3.  2.90 Reserve write delay line register (MMDC_MPWRDLCTL) configuration as DDR script does when do write calibration. In previous releases, MMDC_MPWRDLCTL would be changed to 0x40404040 by default.      * Further details available in the release notes  _________________________________________________________________________________________________________________________________________    FAQ   Q. I see an error message that states "ERROR: DCD addr is out of valid range.", why is this and how do I resolve?   A. Sometimes, when using the register programming aid, there are registers writes that are not supported in the DCD range.  Try looking for the following items and comment them out from the DDR initialization script: wait = on setmem /16 0x020bc000 = 0x30 // disable watchdog (note the address for this may be different between i.MX6x devices)  Q. How do I select the "DDR Density" pull-down menu and what is the purpose of this?   A. The DDR Density pull-down menu gives the user the option of testing a DDR density smaller than what they actually have on their board.  The advantage of doing this is to speed up test time to allow the user to perform a "quick test" of their system.  IMPORTANT: it is imperative that the user not set this value higher than the supported density on their board, doing so will cause the stress test to fail and/or lock up. The DDR Density has a different meaning depending on the memory type being tested (DDR3 or LPDDR2): For DDR3, this is the density per CHIP SELECT.  So if your board has two chip selects, and each chip select has 512MB, you would simply select 512MB or lower.  The default setting will simply set this to the detected density per chip select. For LPDDR2, this is the density per CHANNEL.  This is only relevant for MX6 devices that support 2 channel LPDDR2 memories (MX6DQ, MX6DL).  For other MX6 devices that support only one LPDDR2 channel, then this is the total density (for the maximum setting) for that channel. Note that for LPDDR2, the number of chip selects (per channel) is irrelevant when selecting the density to test as the stress test combines both chip-selects into one combined density per channel.  For example, lets say you have a 2GB LPDDR2 device, which 2 channels and 2 chip-selects per channel.  That means you have 512MB per chip select, per channel.  Or, it also means you have 1GB per channel when combining both chip selects per channel.  In this case, you would choose (a maximum setting of) 1GB in the DDR Density drop down menu.  However, this is also the same setting as the default setting (which you are welcome to still choose 1GB to convince yourself that 1GB per channel is indeed being tested). Now let's assume you have only one channel (LPDDR2) and one chip select, with a density of 128MB; in this case, the maximum DDR Density you can select is 128MB. Let's assume you have one channel and two chip selects, each chip select is 128MB;  in this case, the maximum DDR Density you can select is 256MB (a combination of both chip selects).   Note, for the MX7D, an actual density needs to be entered. For the MX6x series, simply leaving this field as Default will cause the DDR stress test to ascertain the supported density from the DDR init script. As the MX7D DDR controller is different, this feature is not supported, hence it is required for the user to enter an actual density (for more details regarding MX7D usage of density and number of chip-selects, see the next FAQ on the DDR CS setting).   Q.  What is the purpose of the "DDR CS" pull-down option?   A.  The answer depends on which processor you are testing:   For the i.MX 6x series: This pull down menu gives you the option of testing one chip select (CS0) or ALL (both) chip selects *IF* you have a two-chip select configuration.  If you have a two-chip select configuration, then this allows you to test only one chip select for faster test time; else you can choose to test both chip selects.  Note that if you have a one-chip select configuration and you choose "ALL", the stress test will return an error.   For the iMX 7D: Because the MX7D DDR controller is different, the DDR stress test will need the user to supply the entire supported density found on their board. The chip select field should be left as is (0) as the test will naturally test one chip select to the next. For example, let’s assume you are using two chip selects, with each chip select being 512MB. In this case, you would enter 1GB for the DDR Density field ensuring that both chip selects will be tested. The user is allowed to enter a density less than the density found on their board (for quicker testing), but keeping in mind both chip selects may not be tested in this case.   Q. I run DDR calibration using the DDR Stress Test Tool to obtain the calibration results.  Are these calibration parameters are written to the uboot flash_header.S automatically or manually?   A. The calibration values obtained from the DDR Stress Test Tool will need to be manually updated in the flash_header.S file or any other DDR initialization script.   Q. When running the DDR stress test on MX7D and I try to perform calibration, I get an error stating that calibration is not supported, is this expected?   A. Yes, calibration is not supported or needed when using MX7.  The reason is, MX7 uses a different memory controller than the MX6 series.  The MX6 series memory controller has built-in support for calibration where the MX7 memory controller does not.   Q. When running the GUI version of the DDR stress test, on MX7 and I leave DDR Density as default, I get an error in the tool stating I must supply a density.  Why is this?   A. This is due to the fact that MX7 uses a different memory controller than the MX6 series.  In the MX6 series, it was possible to calculate the memory density from the memory controller register settings.  The MX7 memory controller is different and does not lend itself to easily calculate the supported density based on the register settings.  Instead, the user should verify the density on their board and selected this value in the DDR Density pull-down menu.    Q. I noticed that when I run write-leveling calibration I sometimes see a note that due to the write-leveling calibration value being greater than 1/8 clock cycle that WALAT must be set to 1.  What does this mean?   A. In the MMDC chapter of the reference manual for the specific i.MX 6 device, the need to set WALAT is described in the MDMISC register as follows: "The purpose of WALAT is to add time delay at the end of a burst write operation to ensure that the JEDEC time specification for Write Post Amble Delay (tWPST) is met (DQS strobe is held low at the end of a write burst for > 30% a clock cycle before it is released). If the value of any of the WL_DL_ABS_OFFSETn register fields are greater than ‘1F’, WALAT should be set to ‘1’ (cycle additional delay). WALAT should be further increased for any full-cycle delays added by the WL_CYC_DELn register fields." Therefore, if the write-leveling calibration routine detects any write-leveling delay value greater than 0x1F, it will note to the user that WALAT must be set and the user should update their DDR3 init script to ensure WALAT is set.  Sometimes, a user may find that the write-leveling delay value may fluctuate from one run to the next, which is quite normal.  If it is found that this delay is "borderline" meaning sometimes it is greater than 0x1F and sometimes it might be slightly less, then it is ok to go ahead and set WALAT permanently in your init script as there is no harm in doing so and will ensure you will stay within JEDEC's tWPST.   Q. I sometimes see that after running write-leveling calibration that delay values being reported back are zero'd out (0x00), and then at times I see a non-zero value being reported, why is this? A. It is quite normal to see slight variations in the delay value between write-leveling calibration runs.  The write-leveling calibration routine assumes a majority of users have designed their board such that the DDR3 memories are placed close to the i.MX 6 SoC. There’s a mechanism in NXP’s DDR Stress test write leveling calibration code that checks the returned write leveling value. If the write-leveling calibration routine detects that the returned delay value is greater than ¾ of a clock cycle, it will "zero out" the delay value. It does this because it assumes that such a large delay result is due to the fact that the DQS signal is already delayed relative to the SDCLK, and to align DQS with SDCLK requires the calibration routine to delay DQS even further to align it to the next SDCLK edge, something we ideally would like to avoid.  JEDEC specs that the DQS edge must be within 25% of a SDCLK cycle with respect to the SDCLK edge, so having DQS initially slightly delayed from SDCLK is actually ok, hence why the calibration routine “zero’s” this out when the returned value exceeds ¾ of a clock cycle.  In cases like this, the DQS edge and SDCLK edge are so close together that in some calibration runs, the DQS edge may slightly precede SDCLK (resulting in a very small write-leveling delay value) and other runs, it may be slightly delayed relative to the SDCLK (resulting in a very large write-leveling delay value that will try to align DQS to the next SDCLK edge, hence needs to be zero’d out).   Q. When using the JTAG version of the DDR stress test, how can I select a different UART port for my serial port?   A. Under the folder ddr_stress_tester_jtag_v2.52, there's a text file that describes how to add a different UART port by adding a few additional commands to your DDR init script.  The following is an outline of these commands: 1. Ungate UART module clocks (most NXP scripts ungate all of the peripheral clocks at the beginning of the script, so this part is already done) 2. Configure the IOMUX options for the pins you wish the UART to use (normally an IOMUX option for UART_TX and UART_RX, and a daisy chain option for the UART_RX input) 3. Enable the desired UART module via the register UCR1, bit UART_EN 4. Disable other UART modules (UCR1[UART_EN] = 0).  Normally disabling UART1 should be sufficient, but it doesn't hurt to disable all of the other un-used UART options for the purpose of the stress test.   Here's an example in the .ds file vernacular of a set up as follows: MX6DQ, UART4 on KEY_COL0 and KEY_ROW0 (assume clock is ungated to all peripherals): mem set 0x020E01F8 32 0x00000004   #// config_pad_mode(KEY_COL0, ALT4) mem set 0x020E01FC 32 0x00000004   #// config_pad_mode(KEY_ROW0, ALT4); mem set 0x020E0938 32 0x00000001   #// Pad KEY_ROW0 is involved in Daisy Chain. mem set 0x02020080 32 0x00000000   #//disable UART1 in UART1_UCR1 (Note, you can disable other UART modules as well) mem set 0x021F0080 32 0x00000001   #//enable UART4 in UART4_UCR1   Here's another example in the .inc file vernacular of a set up as follows: MX6SX, UART5 on SD4_DATA4 abd SD4_DATA5 (assume clock is ungated to all peripherals): setmem /32 0x020E0294 = 0x2 //IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5, ALT2; UART5_TX_DATA setmem /32 0x020E0290 = 0x2 //IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4, ALT2; UART5_RX_DATA setmem /32 0x020E0850 = 0x00000000 // IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, daisy chain for UART5_RX input to use SD4_DATA4 setmem /32 0x021F4080 = 0x00000001 // Enable UART_EN in UCR1 of UART5 // Disable UART_EN in UCR1 of UART1, UART2, UART3, and UART4 setmem /32 0x02020080 = 0x00000000 // UART1 setmem /32 0x021F0080 = 0x00000000 // UART2 setmem /32 0x021EC080 = 0x00000000 // UART3 setmem /32 0x021E8080 = 0x00000000 // UART4     Related Resources Links: iMX 8M Mini Register Programming Aid DRAM PLL setting  i.MX 8/8X Series DDR Tool Release  i.MX 8M Family DDR Tool Release 

Wondering how to manage and install the various rpms generated under tmp/deploy/rpm? smart is the application you need on the target to replace apt-get Please set your local.conf with the following: # It is also recommended you use build history, which adds some sanity checks to package versions, in conjunction with the server that # is running the PR Service. To enable build history, add the following to each building system's # It is recommended to activate "buildhistory" for testing the PR service INHERIT += "buildhistory" BUILDHISTORY_COMMIT = "1" PRSERV_HOST = "localhost:0"  # This will set up your host computer as Package Revision Server // PACKAGE_FEED_URIS = "http://10.170.96.7/imx7rpm" #please place any server ip addr, this one is mine. add also the following to enable the package management (smart): EXTRA_IMAGE_FEATURES += "package-management" Setup your own http server, and link the server repository with your tmp/deploy/rpm repo (your are free to use your preferred http server). Since Morty (yocto 2.4), smart has been deprecated, and now the package management is done with dnf (from Debian). Please check dnf document to get more to know about dnf. The dependencies are still poorly controlled. After compiling a pkg the easiest remain: dnf install package.rpm example: root@imx8mmevk:~# dnf install libfuse2-2.9.7-r0.aarch64.rpm Failed to synchronize cache for repo 'oe-remote-repo-imx8m-imx8mqevk-arm', disabling. Dependencies resolved. ===============================================================================================================  Package                  Arch                    Version                   Repository                    Size =============================================================================================================== Installing:  libfuse2                 aarch64                 2.9.7-r0                  @commandline                  56 k Transaction Summary =============================================================================================================== Install  1 Package Total size: 56 k Installed size: 212 k Is this ok [y/N]: y Downloading Packages: Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction   Preparing        :                                                                                       1/1   Installing       : libfuse2-2.9.7-r0.aarch64                                                             1/1   Running scriptlet: libfuse2-2.9.7-r0.aarch64                                                             1/1 /sbin/ldconfig: /usr/lib/libOpenVG.so is not a symbolic link   Verifying        : libfuse2-2.9.7-r0.aarch64                                                             1/1 Installed:   libfuse2.aarch64 2.9.7-r0 Complete!

1.  Software change for Certification Test Compared to standard Linux/Android release, you may need to do below software changes to implement the certification tests, it is applicable from imx_3.10.31_1.1.0 Linux BSP GA release, for the release before that, user may need to apply the related patches before doing below things, and some examples may be different for former releases, the user needs to change accordingly. See the detailed information in this document “How to do USB Compliance Test for 3.10.y kernel”. And there is also a link describes the patch for USB Certification Test: Patch to make i.MX6DQ USB to support test modes for certification test 2. I.MX6 series USB Certification Guide http://cache.freescale.com/files/microcontrollers/doc/user_guide/IMXUSBCGUG.pdf Include the descriptions of all the Certification Test requirements, equipment, procedures for I.MX6 series. For example, Host/Device High Speed Eye Diagram Test(眼图测试).   3. Description of USBCertification related Registers AN4589 Configuring USB on i.MX 6 Series Processors http://cache.freescale.com/files/32bit/doc/app_note/AN4589.pdf   4. I.MX6Q/I.MX6DL/I.MX6SL/ I.MX6SX Certification Reports, see attachments   5. Checklist and TPL, see attachments. Original Attachment has been moved to: I.MX6SX-Checklist-and-TPL.zip

The i.MX27 multimedia applications processors balance high performance with low power consumption through an intelligent combination of dedicated hardware video accelerators and a fast ARM926EJ-S™ core. Both the i.MX27 and the i.MX27L processors provide an array of connectivity options and robust security. The rich feature set of the i.MX 27 processors make them an excellent choice for video- and voiceover- IP (V2IP) cordless and mobile phones, intelligent remote controls, point-of-sale terminals, control devices, low to mid end PNDs and many other wireless applications. i.MX Family Comparison Product Information on Freescale.com i.MX27 Multimedia Applications Processor i.MX27L Multimedia Applications Processor Evaluation/Development Boards and Systems IMX27PDK:  i.MX27 Development Kit Bootloader Compiling U-Boot for iMX27ADS Installing U-Boot on iMX27ADS Embedded Software and Tools Android OS for i.MX Applications Processors Partners / 3rd-Party Development Tools STK5:  Starter-Kit V for TX Modules with Freescale i.MX Processors (Karo Electronics) Additional Resources i.MX27 ADS Adding USB Host2 i.MX27 D1 Capture Kernel 2.6.22 Compiling U-Boot for i.MX27ADS IMX27-ADS i.MX27 ADS Board Flashing I.MX27 ADS Board Video i.MX27 ADS Board TV Out i.MX 27 ADS Adding USB Host2 i.MX 27 ADS Board Video GST Encode i.MX 27 ADS Board Video GST Play i.MX 27 ADS Compiling Linux Kernel Mainline i.MX 27 mDDR Issue i.MX 27 PDK I.MX27 PDK Board Flashing IMX27-Lite-Kit i.MX 27 Video GST Caps Installing U-Boot on i.MX27ADS

For the board imx8M Quad EVK running the Linux 4.14.78-1.0.0_ga version BSP, the resolutions 3840x2160,1920x1080, 1280x720, 720x480 are support in our default BSP. For the other resolutions how to make it work? This patch used to do support for a non-default resolution on i.MX 8MQ EVK. Basically, the customer needs to change the clocks accordingly to the display requirements,  it to be used as a base to the display support.

The following document contains a list of document, questions and discussions that are relevant in the community based on amount of views. If you are having a problem, doubt or getting started in i.MX processors, you should check the following links to see if your doubt is in there. Yocto Project Freescale Yocto Project main page‌ Yocto Training - HOME‌ i.MX Yocto Project: Frequently Asked Questions‌ Useful bitbake commands‌ Yocto Project Package Management - smart  How to add a new layer and a new recipe in Yocto  Setting up the Eclipse IDE for Yocto Application Development Guide to the .sdcard format  Yocto NFS & TFTP boot  YOCTO project clean  Yocto with a package manager (ex: apt-get)  Yocto Setting the Default Ethernet address and disable DHCP on boot.  i.MX x Building QT for i.MX6  i.MX6/7 DDR Stress Test Tool V3.00  i.MX6DQSDL DDR3 Script Aid  Installing Ubuntu Rootfs on NXP i.MX6 boards  iMX6DQ MAX9286 MIPI CSI2 720P camera surround view solution for Linux BSP i.MX Design&Tool Lists  Simple GPIO Example - quandry  i.MX6 GStreamer-imx Plugins - Tutorial & Example Pipelines  Streaming USB Webcam over Network  Step-by-step: How to setup TI Wilink (WL18xx) with iMX6 Linux 3.10.53  Linux / Kernel Copying Files Between Windows and Linux using PuTTY  Building Linux Kernel  Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)  load kernel from SD card in U-boot  Changing the Kernel configuration for i.MX6 SABRE  Android  The Android Booting process  What is inside the init.rc and what is it used for.  Others How to use qtmultimedia(QML) with Gstreamer 1.0

Chinese version of the paper had been published in July of China Integrated Circuit magazine. Please find Chinese version through following link. 飞思卡尔i.MX6平台DRAM接口高阶应用指导-DDR3篇

When the customer want to use the PCIE module on the i.MX6SX SDB board, they can use the oscillator to do the pretset, there are the test report.

Issue: On i.MX 6Solo designs using LPDD2 memory, the correct settings for two important registries may be confusing to determine. Solution: 1) MMDCx_MDMISC register, LPDDR2_2CH Field: For the i.MX 6Solo processor, this field should always be set to '0'. Reason: Two channel mode is not possible on this processor. Only channel MMDC0 is connected to external pins. 2) IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET register, DDR_SEL Field: For the i.MX 6Solo processor, this field should always be set to "00". Reason: A DRAM Warm Reset requires a response from MMDC1, which is not connected externally on the 6Solo processor, so a Warm Reset never complets. These two issues will be clarified in a subsequent revision of the MCIMX6SDL Reference Manual.

Overview i.MX6Dual/Quad and i.MX6DualLite supports 32-bit and 64-bit DDR3. Freescale i.MX6 SabreSD board deploys 64bit DDR3 and 64bit DDR3 script is delivered into Linux/Android Software release. This document introduces how to create i.MX6 32bit DDR script based on 64bit DDR script when deploying 32bit DDR on customized board. Changes Set the DSE field in the following iomux registers to 0 - disable unused IO pad to save power: IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 IOMUXC_SW_PAD_CTL_GRP_B4DS IOMUXC_SW_PAD_CTL_GRP_B5DS IOMUXC_SW_PAD_CTL_GRP_B6DS IOMUXC_SW_PAD_CTL_GRP_B7DS IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 Update MMDC registers to reflect 32bit DDR changes: MMDC0_MDASP: Update CS0_END if CS size is changed. MMDC0_MDCTL: set DSIZ to 32 bit MMDC1_MPODTCTRL: Set it as 0 and disable the odt of higher byte Follow "i.MX 6 Series DDR Calibration" Application note to calibrate DDR parameters. Reference One example about 32bit DDR script is located under uboot-imx git ( File: board/freescale/mx6q_sabresd/flash_header.S). Open it and you can see the following script: #if defined CONFIG_MX6DL_DDR3 #if defined CONFIG_DDR_32BIT ... #endif You can refer to it and create your 32bit DDR script.

There developed the controller uses i.MX53 + Linux. Has developed a solution for building distributed information and control systems. Prototmpy been in operation for over a year. Examples: - Control Electromagnetic stirring (mixer) http://ontecom.com/en/catalog/ems / Rusal, Krasnoyarsk. - Moniroring and management of pumping stations. - Monitoring and control of climate control systems. You can create a smart home systems and iot. There is experience with PLC (Power Line Communication) Qualcomm/Atheros. In my spare time I develop a budget solution for PLC (Power Line Communication) control / monitoring components smart home. Based on the standard IEC 61131-3 developed software - distributed information management system. The solution is cross-platform. In a single system may be computers of different architectures and various operating systems. Such signals are synchronized controller ARM / Linux, and x86 server (Win, Linux, VMS, ...) Uses wxWidgets. Articles on this subject is, but in Russian.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-344896 

Sometimes we need to use proxy to access network with Ethernet. Here are the steps for how to set proxy in Gingerbread and ICS. Gingerbread 1. Enable http proxy >  sqlite3 /data/data/com.android.providers.settings/databases/settings.db "INSERT INTO secure VALUES (99, 'http_proxy', 'wwwgate0.freescale.net:1080');" With this setting, you can access network for web browsing. If you want to play some http streaming content, you need to set a property for the player, > setprop rw.HTTP_PROXY http://wwwgate0-az.freescale.net:1080 2. Disable http proxy >  sqlite3 /data/data/com.android.providers.settings/databases/settings.db "delete from secure where name='http_proxy'" >  setprop rw.HTTP_PROXY "" ICS 1. Enable http proxy >  setprop net.proxy wwwgate0-az.freescale.net:1080 With this setting, you can access network for web browsing. If you want to play some http streaming content, you need to set a proxy property for the player, >  setprop rw.HTTP_PROXY http://wwwgate0-az.freescale.net:1080 2. Disable http proxy >  setprop net.proxy "" >  setprop rw.HTTP_PROXY ""

iWave's i.MX6 UltraLite (i.MX6UL) based SODIMM CPU module integrates power efficient high performance ARM Cortex A7 CPU core operating up to 528MHz speed. iMX6 UL SOM is ultra-compact in size and integrated with on-board PMIC, Flash, DDR3 and dual Ethernet PHY. The SOM is ideally suitable for the cost & power optimized general embedded and industrial applications.                                                                                                                                                                                                                                                                                                    i.MX6UL SODIMM Development Kit    i.MX6UL SODIMM SOM                                                                                                                                                                                                                                                                                                 Benefits: Ultra-compact form factor module with size of 67.6mm x 29mm Long term support: 7+ years Technical & Quick customization support Compatible with ARM Cortex A9 i.MX6 Q/D/S SODIMM SOM Highlights: Power efficient ARM Cortex-A7 @ 528MHz Advanced hardware enabled security PMIC with DVFS support Industrial temperature support available  Features: CPU: Freescale’s i.MX6UL1/2/3 @ 528MHz ARM Cortex A7 PMIC: Freescale PF3000 Memory: 256MB DDR3 RAM(Expandable) 256MB NAND Flash (Expandable) MicroSD Slot (Optional) 1 eMMC Flash (Optional) 1 QSPI Flash (Optional) 1 Communication: 10/100 Ethernet PHY – 2 Ports SODIMM Edge Interfaces: Debug UART Data UART – 2 Ports CAN – 2 Ports SD(4-Bit) – 1 Port 10/100 Ethernet – Up to 2 Ports 2 USB OTG – 2 Ports 24bpp RGB display port 8-Bit Parallel Camera Port I2S Audio or JTAG I2C x 1 Port PWM GPIOs OS Support: Linux 3.14.28 Power Supply: 3.3V @ 1A through SODIMM edge Note 1: At a time either NAND Flash or eMMC & QSPI flash or uSD & QSPI flash can be used in the SOM. By default NAND Flash is supported. Note 2: If 2 nd Ethernet (ENET2) not used, it can be used as additional 3 UARTs or Key pad 4x4 or RMII interface. Target Applications: Industrial HMI & Access Control Energy management & IOT gateway Industrial control & automation White goods & Smart appliances Medical & Healthcare equipments Mobile POS & Secure e-commerces To send us an enquiry on this product, please click here Enquiry Form To get more details on this product, please write us on [email protected]

The instructions is based on building wayland-weston on Ubuntu prebuilt image. The same can be applied to other build systems as well. PREREQUISITIES The following is the software environment required: - Ubuntu Oneiric (11.10) distribution. (Download Pre-built Ubuntu demo image from www.freescale.com/imx6) - Wayland/Weston : Wayland dependencies are listed in http://wayland.freedesktop.org/building.html. - 0001-DRM-condition.patch and 0002-Enable-weston-for-Vivante-GPU.patches for Weston. WAYLAND VERSION This release is based on Wayland 1.1.0 version. BUILDING The steps are based on wayland building from http://wayland.freedesktop.org/building.html. Download wayland-1.1.0.tar.xz from http://wayland.freedesktop.org/releases.html    3. Setting up the environment. This need to be performed on the target $export WLD=/usr $export LD_LIBRARY_PATH=$WLD/lib $export PKG_CONFIG_PATH=$WLD/lib/pkgconfig/:$WLD/share/pkgconfig/ $export ACLOCAL="aclocal -I $WLD/share/aclocal"        Also, create the 'share/aclocal' directory.                $mkdir -p $WLD/share/aclocal       Let us consider, extracting the package to /opt $cd /opt $tar xvvf wayland-1.1.0.tar.xz $cd wayland-1.1.0 $ ./configure --prefix=$WLD --disable-documentation $ make $ make install   4. Setting up GPU-VIV graphics drivers The GPU-VIV graphics drivers are available as part of BSP release. Get the gpu-viv-wl-bin-mx6q-{VER}.tar.gz for 4.0.0 release gpu-viv-wl-bin-mx6q-3.0.35-4.0.0.tar.gz from the BSP-Source/pkgs Extract to the target $ROOTFS The prebuilt root file system (rootfs) may come with prebuilt GPU driver. By default, it may set to EGL framebuffer. To enable Wayland/Weston support, make EGL and GAL point to correct binaries as shown below: $ ls –l $(ROOTFS)/usr/lib/libEGL.so* libEGL.so -> libEGL-wl.so libEGL.so.1 -> libEGL-wl.so $ ls –l $(ROOTFS)/usr/lib/libGAL.so                            libGAL.so -> libGAL-wl.so   5. Build the libxkbcommon as in http://wayland.freedesktop.org/building.html 6. We will need Cairo stack as Weston clients depend on Cairo for rendering. Please build Cairo as described in http://wayland.freedesktop.org/building.html, but note that, for now, we do not enable gl backend for Cairo, so the '--enable-gl --enable-xcb' flags must not be used when building. 7. Building Weston     Now add the following environment settings in the terminal window. (Note the "`"- backtick - character). export WLD=/usr export LD_LIBRARY_PATH=$WLD/lib export PKG_CONFIG_PATH=$WLD/lib/pkgconfig/:$WLD/share/pkgconfig/ export ACLOCAL="aclocal -I $WLD/share/aclocal" export LD_LIBRARY_PATH="/usr/lib" export LDFLAGS="-lwayland-server -lwayland-client -lwayland-server -lwayland-cursor -lpixman-1" export COMPOSITOR_LIBS="-lGLESv2 -lEGL -lGAL -lwayland-server -lxkbcommon -lpixman-1" export COMPOSITOR_CFLAGS="-I $WLD/include -I $WLD/include/pixman-1 -L$SDK_DIR/drivers -DLINUX=1 -DEGL_API_FB -DEGL_API_WL" export CLIENT_CFLAGS="-I $WLD/include -I $WLD/include/cairo -I $WLD/include/pixman-1" export CLIENT_LIBS="-lGLESv2 -lEGL -lwayland-client -lwayland-cursor -lxkbcommon" export SIMPLE_EGL_CLIENT_CFLAGS="-DLINUX=1 -DEGL_API_FB -DEGL_API_WL -I $WLD/include" export SIMPLE_EGL_CLIENT_LIBS="-lGLESv2 -lEGL -lwayland-client -lwayland-cursor" export IMAGE_LIBS="-lwayland-cursor" export WESTON_INFO_LIBS="-lwayland-client" Apply the two patches 0001-DRM-condition.patch and 0002-Enable-weston-for-Vivante-GPU.patch. Build the Weston. $cd /opt $tar xvvf weston-1.1.1.tar.xz $ cd weston-1.1.1     $ ./configure --prefix=$WLD \         --disable-setuid-install \         --disable-x11-compositor --disable-drm-compositor \         --disable-rpi-compositor --disable-wayland-compositor \         --disable-weston-launch --disable-libunwind \         --disable-xwayland-test \ WESTON_NATIVE_BACKEND="fbdev-backend.so" $ make $ make install RUNNING Also, Weston must be run as root. copy weston.ini and weston-desktop-shell.ini to /root/.config/ . In terminal window, export LD_LIBRARY_PATH="/usr/lib" export XDG_RUNTIME_DIR=/tmp Execute 'src/weston'. You should see a blue screen fading in. In a different terminal, enter 'clients/simple-shm &'. You should see a scrolling color pattern. You can then enter 'clients/simple-egl &' to see a 3D client  action.

  The VAR-SOM-SOLO small form factor System-on-Module carries an advanced feature-set and broad connectivity options, making it an ideal solution for customers and products in the embedded market.   Staying on-trend with the market’s shift towards a cost-effective highly integrated off-the-shelf solution, the VAR-SOM-SOLO from Variscite levels the playing ground for a broad spectrum of embedded products. Bringing all the benefits of the widely successful VAR-SOM-MX6, the VAR-SOM-SOLO from Variscite carries much smaller dimensions and a slim lined price-point.  Features include Freescale’s i.MX6 1GHz Cortex-A9, SLC NAND, eMMC, dual band Wi-Fi/BT with MIMO, USB, Gigabit Ethernet, A/V interfaces and industrial operating temperatures. The VAR-SOM-SOLO utilizes a standard SO-DIMM 200pins interface to the carrier board, fully pin-to-pin compatible with the VAR-SOM-MX6.   Ohad Yaniv, Variscite’s CEO, explains the strategy behind the new System-on-Module: “In today’s market, we believe the compact VAR-SOM-SOLO presents a true synergy between an impressive feature set and an affordable price-point. We feel the newly introduced SoM reflects a constantly evolving embedded application concept that requires advanced multimedia features, in a compact and cost efficient solution.”   Key features include:   - Freescale i.MX6 1000MHz single Cortex-A9   - Up to 1GB DDR3, 512MB SLC NAND and 64GB eMMC   - Certified Wi-Fi 802.11 a/b/g/n 2.4/5GHz with optional 2x2 MIMO   - Bluetooth 4.0/BLE   - Full 1080p video encode/decode capability   - Vivante GPU 2D/3D graphics accelerator   - Display: 2x LVDS, HDMI1.4, MIPI DSI   - 10/100/1000 Mbps Ethernet   - USB 2.0: Host, OTG   - PCIe   - Audio In/Out   - Camera inputs: MIPI CSI, parallel   - Dual CAN, UART, I2C, SPI   - Industrial temperature -40 to 85°C   - Dimensions: 33mm x 68mm x 4mm   - OS: Linux Yocto & Ubuntu, Android, WEC 7 & 2013   Availability and Pricing: The VAR-SOM-SOLO is available now. Pricing starts at 42USD. Contact [email protected] or +972 9 9562910 for more information.   About Variscite: Variscite is a leading System on Modules (SoM) and Single-Board-Computer (SBC) design and manufacture company. A trusted provider of development and production services for a variety of embedded platforms, Variscite transforms clients’ visions into successful products.   Learn more about Variscite, visit www.variscite.com    

[中文翻译版] 见附件   原文链接： Add a new shared memory region on Android Auto P9.0.0_GA2.1.0 BSP 

Introduction This guide provides a step by step explanation of what is involved in adding a new WiFi driver and making a new WiFi card work well in a custom Android build. (This guide was written for Android 4.1 but should be applicable to previous Android releases and hopefully future releases.) Contents Understand how Android WiFi works Port WiFi driver. Compile a proper wpa_supplicant in your BoardConfig.mk Modify your wifi.c in HAL. Launch wpa_supplicant and dhcpcd services in init.rc. Several debug tips. Understand How Android WiFi Works As the following figure, Android wireless architecture can be divided into three parts: Java Framework(WifiManager, WifiMonitor etc..), HAL(wifi.c,wpa_supplicant,netd) kernel space modules(wireless stack, wifi drivers) Java Framework communicate with wpa_supplicant using native interface (wifi.c). Wpa_supplicant and netd uses wireless extension or nl80211 to control WiFi drivers. Port WiFi driver Usually WiFi driver is provided as a kernel module. There are mainly two types of Android WiFi architecture:nl80211 and wext. With the implementation of nl80211/cfg80211 many wireless drivers in main line kernel  support nl80211 interface instead of wireless extension. For different vendors’ WiFi drivers, writing one Android.mk to add its compile into Android is what you should do. Here take atheros’s AR6kl as an example: ath6kl_module_file :=drivers/net/wireless/ath/ath6kl/ath6kl_sdio.ko $(ATH_ANDROID_SRC_BASE)/$(ath6kl_module_file):$(mod_cleanup) $(TARGET_PREBUILT_KERNEL) $(ACP)         $(MAKE) -C $(ATH_ANDROID_SRC_BASE) O=$(ATH_LINUXPATH) ARCH=arm CROSS_COMPILE=$(ARM_EABI_TOOLCHAIN)/arm-eabi- KLIB=$(ATH_\ LINUXPATH) KLIB_BUILD=$(ATH_LINUXPATH)         $(ACP) -fpt $(ATH_ANDROID_SRC_BASE)/compat/compat.ko $(TARGET_OUT)/lib/modules/         $(ACP) -fpt $(ATH_ANDROID_SRC_BASE)/net/wireless/cfg80211.ko $(TARGET_OUT)/lib/modules/ include $(CLEAR_VARS) LOCAL_MODULE := ath6kl_sdio.ko LOCAL_MODULE_TAGS := optional LOCAL_MODULE_CLASS := ETC LOCAL_MODULE_PATH := $(TARGET_OUT)/lib/modules LOCAL_SRC_FILES := $(ath6kl_module_file) include $(BUILD_PREBUILT) Compile a proper wpa_supplicant in your BoardConfig.mk In Android’s external directory, there are two wpa_supplicant_* projects. For wext-based wifi driver, wpa_supplicant_6 can be used. For nl80211-based WiFi driver, wpa_supplicnat_8 can only be used. But if WiFi vendors supply their own customized wpa_supplicant, it will be much easier to debug the communication between wpa_supplicant and WiFi drivers. No matter which supplicant  you choose, just control their compile in your BoardConfig.mk. Take atheros’s ath6kl as an example: ifeq ($(BOARD_WLAN_VENDOR),ATHEROS) BOARD_WLAN_DEVICE                        := ar6003 BOARD_HAS_ATH_WLAN                      := true WPA_SUPPLICANT_VERSION                  := VER_0_8_ATHEROS WIFI_DRIVER_MODULE_PATH                  := "/system/lib/modules/ath6kl_sdio.ko" WIFI_DRIVER_MODULE_NAME                  := "ath6kl_sdio" WIFI_DRIVER_MODULE_ARG                  := "suspend_mode=3 wow_mode=2 ar6k_clock=26000000 ath6kl_p2p=1" WIFI_DRIVER_P2P_MODULE_ARG              := "suspend_mode=3 wow_mode=2 ar6k_clock=26000000 ath6kl_p2p=1 debug_mask=0x2413" WIFI_SDIO_IF_DRIVER_MODULE_PATH          := "/system/lib/modules/cfg80211.ko" WIFI_SDIO_IF_DRIVER_MODULE_NAME          := "cfg80211" WIFI_SDIO_IF_DRIVER_MODULE_ARG          := "" WIFI_COMPAT_MODULE_PATH                  := "/system/lib/modules/compat.ko" WIFI_COMPAT_MODULE_NAME                  := "compat" WIFI_COMPAT_MODULE_ARG                  := "" endif then you need to provide a proper wpa_supplicant.conf  for your device. wpa_supplicant.conf  is very important because the control socket for android is specified in this file(ctrl_interface=). This file should be copied to /system/etc/wifi. Minimum required config options in wpa_supplicant.conf : There are two different ways in which wpa_supplicant can be configured, one is to use a "private" socket in android namespace, created by socket_local_client_connect() function in wpa_ctrl.c and another is by using a standard UNIX socket. Android private socket ctrl_interface=wlan0 update_config=1 - Unix standard socket ctrl_interface=DIR=/data/system/wpa_supplicant GROUP=wifi update_config=1 Modify your wifi.c in HAL Here what you should do is modifying some codes like wifi_load_driver and wifi_unload_driver. For Broadcom or CSR’s wifi driver, you can directly use the original wifi.c. But for atheros’s ath6kl driver, there are total three  .ko modules to install. So some micro variables and codes need to be changed to adapt it. Launch wpa_supplicant and dhcpcd services in init.rc If you have configured to use android private socket, you should do like this: service wpa_supplicant /system/bin/wpa_supplicant -Dwext -iwlan0 -c / data/misc/wifi /wpa_supplicant.conf socket wpa_wlan0 dgram 660 wifi wifi disabled oneshot or if you have configured to use unix standard socket, you should do like this: service wpa_supplicant /system/bin/wpa_supplicant -Dwext -iwlan0  -c/data/misc/wifi/wpa_supplicant.conf disabled oneshot If WiFi driver is not “wext” but “nl80211”, you should change it to –Dnl80211. For dhcpcd, you should lunch it like the following: service dhcpcd_wlan0 /system/bin/dhcpcd -ABKL     class late_start     disabled oneshot The parameters “-ABKL” can largely enhance wifi connection speed.  About what “ABKL” stand for, you can refer to dhcpcd’s GNU manual. Several debug tips Incorrect permissions will result in wpa_supplicant not being able to create/open the control socket andlibhardware_legacy/wifi/wifi.c won't connect. Since Google modified wpa_supplicant to run as wifi user/group the directory structure and file ownership should belong to wifi user/group (see os_program_init() function in wpa_supplicant/os_unix.c ). Otherwise errors like: E/WifiHW  (  😞 Unable to open connection to supplicant on "/data/system/wpa_supplicant/wlan0": No such file or directory will appear. Also wpa_supplicant.conf should belong to wifi user/group because wpa_supplicant will want to modify this file. How to Enable debug for wpa_supplicant.               By default wpa_supplicant is set to MSG_INFO that doesn't tell much.                    To enable more messages:                 modify common.c and set wpa_debug_level = MSG_DEBUG                 modify common.h and change #define wpa_printf from if ((level) >= MSG_INFO) to if ((level) >= MSG_DEBUG)         3. WiFi driver’s softmac.               For most vendors’ WiFi driver, the mac address is fixed. We should add one softmac rule to let WiFi driver’s mac is unique for each board.