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Enable HDMI CEC function Board: i.MX8MQ Board BSP version: imx-android-11.0.0_2.2.0  Following the Android user guide download and built the Android-11.0.0_2.2.0 BSP  The build directory shared here:  http://10.168.2.226/android/build_folder/device/nxp/imx8m/evk_8mq/hdmicec/. or use the files in attachment. The steps are: Copy the above link code to their android env under device/nxp/imx8m/evk_8mq/hdmicec/.  In device/nxp/imx8m/evk_8mq/evk_8mq.mk, adding below code: +PRODUCT_PACKAGES += \ hdmi_cec.nxp\ hdmicec_test" (2) Compile that. (3) Copy to board  adb root adb remount adb push hdmi_cec.nxp.so /vendor/lib64 adb push hdmi_test /vendor/bin evk_8mq:/vendor/bin # ./hdmicec_test [  349.297183] msg[0]=0x40 [  349.299641] msg[1]=0x4
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Symptoms   When configure a gpio pin for a driver in the dts/dtsi file like below example,   e.g.   a-switch {            compatible = "a-switch-driver";            pinctrl-names = "default";            pinctrl-0 = <&pinctrl_switch>;            gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;            status = "okay"; };   pinctrl_switch: switch_gpio {     fsl,pins = < IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01    0x21 >; };   then you may get the error when request the gpio in the driver during the kernel boot up.   Error message like this: a-switch: failed to request gpio a-switch: probe of a-switch failed with error -22   Linux version: L5.4.x   Diagnosis   Because the gpio_mxc_init function run before the function imx_scu_driver_init. The pm_domains for gpio is not ready before running mxc_gpio_probe, so gpio request will be failed.     Solution   There are two ways to resolve this issue 1. Build the driver as a module. i.e. select the driver in kernel’s menuconfig as “M”. Then , run “insmod” to load the driver after the kernel boot up.   OR   2. Apply below patch, let gpio driver init after scu driver. diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 1dfe513f8fcf..52b5799040b3 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -892,7 +892,7 @@ static int __init gpio_mxc_init(void) return platform_driver_register(&mxc_gpio_driver); } -subsys_initcall(gpio_mxc_init); +device_initcall(gpio_mxc_init);  
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1 - Introduction: The Ultra Secured Digital Host Controller (uSDHC) provides the interface between the host processor and the SD/SDIO/MMC cards. Most recent versions provides the ability to automatically select a quantized delay (in fractions of the clock period) regardless of on-chip variations such as process, voltage, and temperature (PVT). The auto tuning is performed during runtime at hardware level, no software enablement is needed to drive this feature. 2 - Failure description: SDIO cards can implement an optional feature that uses DATA[1] to signal the card's interrupt to the i.MX device, this feature can be enabled by the SDIO card device and does not depends on i.MX uSDHC driver configuration. NXP Linux BSP is enabling the auto tuning for high SDIO frequencies (SDR104 and SDR50). Out of reset uSDHC_VEND_SPEC2 register is configured to use DATA[3:0] for calibration, this setup can conflict with the SDIO interrupt as DATA[1] signal can be asserted asynchronously. SDIO failures can be observed when running SDIO applications that requires high usage of the SDIO interface (e.g Download of large files), SDIO controller cannot return an accurate DLL causing failures such as "CMD53 read error". Failure can be observed on i.MX8MM EVK and i.MX8MN EVK boards, both devices are running 88w8987 Wi-Fi chipset at 208Mhz (SDR104). Users can observe an SDIO crash followed by error message below at Linux Kernel level. [ 401.945627] cmd53 read error=-84 [ 401.974677] moal_read_data_sync: read registers failed 3 - Impacted devices: The following devices are impacted by this limitation. - i.MX6 Family:   i.MX6SL, i.MX6SLL, i.MX6SX, i.MX6UL, i.MX6ULZ and i.MX6ULL. - All i.MX7 and i.MX7ULP family:   i.MX7D, i.MX7S and i.MX7ULP. - All i.MX8M Family:   i.MX8MQuad, i.MX8M Mini, i.MX8M Nano, i.MX8M Nano UL and i.MX8M Plus. - All i.MX8/8X Family:   i.MX8DQXP, i.MX8DX and i.MX8QM. NXP Linux BSP is enabling the auto tuning for SDR104 and SDR50 modes. Other operation modes are not impacted by this limitation. Users can poll uSDHCx_CLK_TUNE_CTRL_STATUS register when running SDIO applications to confirm. TAP_SEL_PRE field is updated automatically during run time and constant variations can point to an incorrect delay cell calculated by the uSDHC controller.   All NXP Wi-Fi chipsets are enabling SDIO interrupt during firmware load, failures can be observed with any Wi-Fi vendor enabling SDIO asynchronous interrupt. 4 - Software changes: Recommendation is to enable auto tuning for DATA[0] and CMD signals only, DATA[1] should not be used for auto calibration to avoid a possible conflict with SDIO interrupt. This setup can only be used if SDIO interface length are well matched. Software patches can be found at codeaurora.org. Fix is already included in L5.10.52-2.1.0 BSP, users can add fsl,sdio-interrupt-enabled property to uSDHC device tree node to enable SW workaround. https://github.com/nxp-imx/linux-imx/commit/3b3d6dec05277f7786d813592a31ea4a1ce60a74 https://github.com/nxp-imx/linux-imx/commit/b9b5a43df1d709809b2b654ad8f8181b00a4ee55 https://github.com/nxp-imx/linux-imx/commit/95a846af9f82dc6ea60064d9d12d5d2378e23941      
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The i.MX 8QuadXPlus Multisensory Enablement Kit (MEK) is a NXP development platform based on Cortex A-35 + Cortex-M4 cores. Built with high-level integration to support graphics, video, image processing, audio, and voice functions, the i.MX 8X processor family is ideal for safety-certifiable and efficient performance requirements. This tutorial shows how to enable the Cortex-M4 using the MCUXpresso SDK package and loading the binary from the network. NOTE: It is also possible to load the Cortex-M4 image from the SCFW using the imx-mkimage utility. But now we are going to focus on MCUXpresso. Setting up the machine   Install cmake on the host machine: $ sudo apt-get install cmake Download the armgcc toolchain and export the location as ARMGCC_DIR: $ export ARMGCC_DIR=<your_path_to_arm_gcc>/gcc-arm-none-eabi-9-2020q2/ NOTE: The ARMGCC_DIR variable needs to be exported on the terminal used for compilation. To setup the TFTP server on the host machine: Configuring your Host PC for TFTPPermalink   The first step is to install all the prerequisite packages for TFTP: $ sudo apt-get install xinetd tftpd tftp Create a TFTP folder in your desired location with root owner and the “rwx” permission for all users: $ sudo mkdir /tftpboot $ sudo chmod –R 777 /tftpboot $ sudo chown –R root /tftpboot Create a configuration file for the TFTP with the following content. (The server_args parameter must match with the folder created above) $ cat /etc/xinetd.d/tftp service tftp { protocol = udp port = 69 socket_type = dgram wait = yes user = root server = /usr/sbin/in.tftpd server_args = -s /tftpboot disable = no } Restart the xinetd service: $ sudo /etc/init.d/xinetd restart You can place any file at the TFTP folder and load it through U-Boot, you can also create symbolic links from your building directory avoiding to copy and paste your zImage and dtb files every time. Configuring your Host PC for NFSPermalink   Install all the needed packages for NFS: $ sudo apt-get install nfs-kernel-server Create a folder for placing your rootfs: $ mkdir /tftpboot/rfs Add the following line in the end of your /etc/exports file: /tftpboot/rfs *(rw,no_root_squash,no_subtree_check) Restart the NFS service: $ sudo service nfs-kernel-server restart Place your rootfs or create a symbolic link for the NFS folder.    Downloading the SDK Download the MCUXpresso following these steps: Click on “Select Development Board”; Select MEK-MIMX8QX under “Select a Device, Board, or Kit” and click on “Build MCUXpresso SDK” on the right; Select “Host OS” as Linux and “Toolchain/IDE” as GCC ARM Embedded; Add “FreeRTOS” and all the wanted Middleware and hit “Request Build”; Wait for the SDK to build and download the package. Building the image All demos and code examples available on the SDK package are located in the directory <<SDK_dir>>/boards/mekmimx8qx/. This tutorial shows how to build and flash the hello_world demo but similar procedures can be applied for any example (demo, driver, multicore, etc) on the SDK. To build the demo, enter the armgcc folder under the demo directory and make sure that the ARMGCC_DIR variable is set correctly. $ cd ~/SDK_2.3.0_MEK-MIMX8QX/boards/mekmimx8qx/demo_apps/hello_world/armgcc $ export ARMGCC_DIR=<your_path_to_arm_gcc>/gcc-arm-none-eabi-9-2020q2/ Run the build_release.sh script to build the code. $ ./build_release.sh NOTE: If needed, give the script execution permission by running chmod +x build_release.sh. This generates the M4 binary (hello_world.bin) under the release folder. Copy this image to the /tftpboot/ directory on the host PC. NOTE: This procedure shows how to build the M4 image that runs on TCM. To run the image from DDR, use the build_ddr_release.sh script to build the binary under the ddr_release folder. Flashing the image Open two serial consoles, one for /dev/ttyUSB0 for Cortex-A35 to boot Linux, and one for /dev/ttyUSB1 for Cortex-M4 to boot the SDK image. On the A35 console, with a SD Card with U-Boot, stop the booting process and enter the following commands to load the M4 binary to TCM: => dhcp => setenv serverip <ip_from_host_pc> => tftp 0x88000000 hello_world.bin => dcache flush => bootaux 0x88000000 Then the M4 core will load the image to the /dev/ttyUSB1 console.    
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SW Environment Setup: 1. Prepare L5.10.35 Yocto and build Image  The prebuilt image also is available and useable. 2. Flash image to the SD card  Refer to the Yocto User Guide. 3. Compile flash.bin without M4 and flash it to sdcard (flash.bin as attachment)  make SOC=iMX8QM flash sudo dd if=flash.bin of=/dev/sde bs=1k seek=32 conv=fsync HW Environment Setup: Prepare the imx8qm MEK CPU board and base board and DB9 male cable, connect to CAN0 and CAN1 female connector on base board. (Pin to Pin connection) User Case: 1. Power on board and configure specify dtb file in uboot  setenv fdt_file imx8qm_mek.dtb 2. Boot up and config bitrate for can0 and can1 in kernel root@imx8qmmek:~# ip link set can0 up type can bitrate 500000 root@imx8qmmek:~# ip link set can1 up type can bitrate 500000 3. Check CAN0 and CAN1 devices root@imx8qmmek:~# ifconfig can0: flags=193<UP,RUNNING,NOARP> mtu 16 unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 (UNSPEC) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 device interrupt 85 can1: flags=193<UP,RUNNING,NOARP> mtu 16 unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 (UNSPEC) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 device interrupt 86 3. Run candump for CAN1 root@imx8qmmek:~# candump can1 & [1] 1215 [ 65.624580] can: controller area network core [ 65.630225] NET: Registered protocol family 29 [ 65.641158] can: raw protocol 4. Run cansend for CAN0 root@imx8qmmek:~# cansend can0 5A1#11.2233.44556677.88 can1 5A1 [8] 11 22 33 44 55 66 77 88   The above red is output result from CAN1.
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Here are some debug methods for kernel performance requirements or related issues. It includes all the common methods such as oops/panic issues, memory issues, and so on. Please check it in the attachments for details. OS and System analysis Oops/Panic case addr2line objdump gdb Pstore Kdump Memory debugging SLAB KASAN Kmemleak Performance Perf Ftrace eBPF/bcc
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Use case: iMX8QXP system can be a video input source to another system.   Hardware Pins: LCDIF_D00 ~ LCDIF_D07 LCDIF_CLK LCDIF_VSYNC LCDIF_HSYNC LCDIF_EN   Reference patch: It is based on L5.4.70_2.3.0 GA BSP.  File: L5.4.70_2.3.0-iMX8QXP-LCDIF-add-YUV422-8-bits-output.patch Customer can change the timing parameters in file "panel-lcdif-yuv422.c" as needed, the default timing is a 1280x720 P30 mode: static const struct display_timing yuv422_lcd_timing = {     .pixelclock = { 74250000, 74250000, 74250000 },     .hactive = { 1280, 1280, 1280 },     .hfront_porch = { 220, 220, 220 },     .hback_porch = { 110, 110, 110 },     .hsync_len = { 40, 40, 40 },     .vactive = { 720, 720, 720 },     .vfront_porch = { 20, 20, 20 },     .vback_porch = { 5, 5, 5 },     .vsync_len = { 5, 5, 5 },     .flags = DISPLAY_FLAGS_DE_HIGH, };   Test application: drm_test_yuv.zip: it can set framebuffer to UYVY mode, in this case, no CSC is needed, the data in framebuffer memory will be same as output on display data interface. drm_test_rgb.zip: it can set framebuffer to RGBA mode, in this case, RGB to YUV CSC is needed, application can draw RGB data into framebuffer as normal, the LCDIF will convert it to YUV422 format on the fly, then output the YUV data to display interface.    
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This article will describe one suggestion for one issue that UART continuously generate RX interrupts and receive 0xFF even when Rx line is continuously high in some cases on imx6 series. Below I will explain with imx6DL. Some settings are just to make it easier to reproduce. BSP version: L5.4.70-2.3.0 Board HW: MCIMX6DL-SDB When issue happen Config imx6DL UART3 as the serial port to 1200 baud, 8-N-1 format. Keep the RX Line high. Make the RX line low and keep it for a short time (360 usec-370 usec).   At this condition, you will find that the UART will continuously generate RX interrupts and show receiving 0xFF even you make the RX line return to be high. Why issue happen The low time is not in the correct range and out of our spec. In the imx6DL AEC document, there is one chapter named UART Receiver like blow   If using 1200 band, that means one valid bit time is 833 usec. And there is a definition that “tolerate 1/(16 x Fbaud_rate) tolerance in each bit”. That’s means in the case of 1200 baud. A range of valid bit is 781 to 885 usec. But is reproducing, the Low level time is 360 usec. This time out of range will make UART state machine to be confused. How to fix Actually, the best way is following our spec. If there is such an unknown situation in the customer’s environment, then the following method could be regarded as a suggestion to fix the issue meet by the customer. The interrupt handler will check USR1[AWAKE]. 2    If AWAKE is asserted, clear it and proceed as usual (assume we have valid data), else, check if USR1[AGTIM] is asserted. 3    if AGTIM is asserted, clear it and proceed as usual, else perform software reset (assume we have invalid data). Checking AGTIM is for one race condition when the RX fifo has some characters (less than RXTL) but no more data is coming in. When following this procedure, the UART will perform a software reset when a block interrupt occurs. Notes: From customer report, error could be cleared if a valid start-bit is detected on the RX line. This needs to be verified by the customer themselves. Test code has been included in attachment.   Besst Regards
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Introduction This document intends to describe how to implement workaround for ERR050145 (ISI: Memory overwrite occurring outside of allocated buffer space corrupting system memory) based on Linux BSP. ERR050145 is applicable for i.MX8QM B0, i.MX8QXP B0 series products.   Software Platform Reference patches stated into this document are developed and validated on L4.14.98_GA2.0.0 release.   Software Workaround As workaround stated, the xRDC can be programmed to grant write access to the ISI only within its allocated frame buffer space, which can prevent the corruption. So under Linux, we can consider to implement workaround like so: Create children partition for ISI and allocate buffers. Then Linux can access these buffers as normal, but ISI can't access other memory out of these buffers, it is limited by xRDC hardware. Considering the xRDC hardware can only support up to 16 memory regions, we may need to consider different workaround implementations for different camera use case scenarios.   For single camera use case, the required camera buffer number is usually less than 16. So “0001-iMX8QM-iMX8QX-ERR050145-ISI-overwrite-workaround.patch” is enough. No modification is needed for camera application in this case.   For multiple camera use case, all patches (0001~0003) are needed. If the camera application used VB2_MEMORY_MMAP memory mode, then no code modification is needed in application. The V4l2 ISI driver can handle everything (Allocate physical continued memory for each camera, and map them as one xRDC memory region for overwrite protect). If the camera application used VB2_MEMORY_USERPTR and VB2_MEMORY_DMABUF memory mode, then it needs allocate camera buffers with physical continued memory for each camera, then the driver will merge them as one xRDC memory region in SCFW.   How to prove workaround take effective? After applying the patches, the ISI will report AXI_WR_ERR due to it failed to write data out of the allocated buffers when the errata happens. To reduce the ISI interrupt, we can also change the ISI interrupt setting as followed: void mxc_isi_enable_irq(struct mxc_isi_dev *mxc_isi) {     u32 val;     val = CHNL_IER_FRM_RCVD_EN_MASK |         CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK |         CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK |         CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK;     writel(val, mxc_isi->regs + CHNL_IER); }   Add reference patch for L5.4.70_2.3.0 and L5.10.72_2.2.0.
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The A53 Debug Console Changing consists in several major updates like: RDC settings, Pinmux, Clocks and Ecosystem Updates.
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Some case need configure the GPIO as power off button. One solution is to use “gpio-keys” to send the “KEY_POWER” event to the system. Co-work with systemd, system gets power off.  
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Purpose This is early communication to notify i.MX 8M Dual/8M QuadLite/8M Quad customers of a potential incorrect PCIe power supply configuration on certain NXP BSP Linux and Android versions. Description The PCIE_VPH power supply is selectable in software  between 1.8V and 3.3V. When the PCIE_VPH supply is configured to operate at 3.3V, the 1.8V internal regulator (disabled by default) must be enabled to prevent overstress conditions on the PCIe PHY. If the 1.8V internal regulator is left disabled when the PCIE_VPH supply is configured to operate at 3.3V, it could potentially impact the product lifetime of the device.   Impact •i.MX 8M Dual/8M QuadLite/8M Quad (other i.MX processors are not impacted) •Only Impacts Linux/Android kernel versions earlier than L5.4.70_2.3.2 or Linux 5.10.9_1.0.0 releases MITIGATION •When the PCIE_VPH supply is configured to operate at 3.3V users need to enable the internal regulator by setting the IOMUXC_GPR_GPR14 and IOMUXC_GPR_GPR16 registers - PCIE1_VREG_BYPASS and PCIE2_VREG_BYPASS bit to 0. •There are 3 software patches for each release. Software patch details in the Code Aurora Forum (CAF): •For L5.4.70_2.3.2 patch release, the git log references are: •MLK-25349-3 PCI: imx: clear vreg bypass when pcie vph voltage is 3v3 •MLK-25349-2 arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy •MLK-25349-1 dt-bindings: imx6q-pcie: add one regulator used to power up pcie phy • •The L5.4.70_2.3.2, LF_5.10 Q2 and later BSP releases correctly configure and enable the internal regulator by setting the IOMUXC_GPR_GPR14 and IOMUXC_GPR_GPR16 registers The Patch MLK-25349 which correctly enables the internal regulator is already included in the L5.4.70_2.3.2 patch release and release versions after it. MITIGATION •The following branches of Linux/Android BSP releases contain the MLK-25349 patch. The patch is attached below for each respective release.   •Other branches which are not listed should try to apply the nearest Patch version patch. If a user encounters any conflicts in applying, they should back porting from below nearest patch release version below. imx_4.9.51_ga, imx_4.9.y_android_imx8m_ga_v2                           - Patch attached  imx_4.9.88_ga, imx_4.9.y_android_2.0.0_ga                                   - Patch attached  imx_4.14.y and imx_4.14.98_2.3.0, imx_4.14.98_2.3.0_android     - Patch attached  imx_4.19.y and imx_4.19.35_1.1.0, imx_4.19.35_1.1.0_android     - Patch attached  imx_5.4.y, imx_5.4.3_2.0.0, imx_5.4.3_2.0.0_android                     - Patch attached Documentation Change Description – 1 of 3 for Datasheet Updated Datasheets and Reference Manual will be published to nxp.com. Updated Hardware Design guide and Schematics have already been published on nxp.com.  Updated the descriptions of PCIE_VPH in the Datasheet Table 8, "Operating ranges"     Documentation Change Description – 2 of 3 for Reference Manual (RM) Updated the description of field 12 "PCIE1_VREG_BYPASS" in 8.2.4.15 GPR14 General Purpose Register (IOMUXC_GPR_GPR14)           Documentation Change Description – 3 of 3 for RM Updated the description of field 12 "PCIE2_VREG_BYPASS" in 8.2.4.17 GPR16 General Purpose Register (IOMUXC_GPR_GPR16)   REFERENCES •i.MX 8M Dual / 8M QuadLite / 8M Quad Product Lifetime Usage  •i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Industrial Products •i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products •i.MX 8MDQLQ Hardware Developer’s Guide  •i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual  
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Software environment: L5.4.47_2.2.0 Hardware i.MX8QXPC0 EVK board In the uuu script we can see the bootloader imx-boot-imx8qxpc0mek-sd.bin-flash is necessary. The default BSP build generate in the yocto project is with the spl, some customers are confused about the how to build the imx-boot-imx8qxpc0mek-sd.bin-flash. Here I give the manually compile way and generate it in yocto. In the yocto generate it is more convenient than the manually compile way. Hope this can do help for you.
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1.  Introduction 1.1.        Purpose This application note introduces a procedure of how to port AVB/TSN stack and run referring feature demos on i.MX8DXL board. This can help users who want to run AVB/TSN demos to quickly understand and customized their own codes. Since many of the standards are only for TSN switch/bridges and i.MX8DXL is design to be a TSN/AVB endpoint, the demos did not implement a full stack or full standards. They only demonstrated the basic end-to-end point (talker to listener) A/V streaming without bridge or switch. The software used for example in this documentation are based on the opensource such as gstreamer and alsa utils.   1.2.        Overview 1.2.1.     AVB/TSN AVB (Audio Video Bridging) is a common name for the set of technical standards which provide improved synchronization, low-latency, and reliability for switched ethernet network. AVB was initially developed by the IEEE Audio Video Bridging task group of the IEEE 802.1 standards committee. In November 2012, AVB group was renamed to TSN (Time-Sensitive Networking) task group to reflect the expanded scope of its work, which is to provide the specifications that will allow time-synchronized low latency streaming services through IEEE 802 networks. The referring standards shows as follows:     TSN protocol additions QoS components supported in HW TSN MAC + SW driver Managed Object components expose i/f to allow support of standardized network config protocols (local & remote) Transport API to allow other transport layer to use TSN QoS Stack extensions to map traffic priority to application task scheduling Real Time, gPTP based, Best Effort 1.2.2.     Demo introduction   The two streams are defined as below to grantee time sensitive (sub-microsecond synchronization), low latency and bandwidth on the ethernet: Stream A: SR class A, AVTP Audio Format, PCM 16-bit sample, 48 kHz, stereo, 12 frames per AVTPDU. Stream B: SR class B, AVTP Compressed Video Format, H.264 profile High, 1920x1080, 30 fps. The two TSN streams would be allocated into different TC (traffic control) class for egress. Different TC class would be mapped to different hardware queues with specific DMA channel which supported by ENET_OoS IP. The demos were built by follow blocks:   Linux Traffic Control: streams egress control Linux ptp: clock sync in network Libavtp: Time Sensitive Applications AV Transport protocol Gstreamer: avtp plugin uses the libavtp to transmit and receive AVTP audio/video (audio pcm, video h264).   1.2.3.     Traffic control Multiply queue qdiscs + CBS: The CBS class is actually handled by hardware IP to select which queue for transmitting.   CBS parameters come straight from the IEEE 802.1Q-2018 specification. They are the following: idleSlope: rate credits are accumulated when queue isn’t transmitting; sendSlope: rate credits are spent when queue is transmitting; hiCredit: maximum amount of credits the queue is allowed to have; loCredit: minimum amount of credits the queue is allowed to have;     2.  Build demo 2.1.        Build yocto $ DISTRO=fsl-imx-xwayland MACHINE=imx8dxlevk source imx-setup-release.sh -b ./xwayland $ bitbake imx-image-full Prepare a SD card and burn it with the built out images. 2.2.        Rebuild kernel Rebuild the kernel after applying the 0001-qenet-add-queue-avoid-panic.patch, and overwrite the Image and imx8dxl-evk.dtb on the boot partition of the SD card. 2.3.        Install the toolchain $ bitbake -f fsl-image-validation-imx -c populate_sdk $ sh tmp/deploy/sdk/fsl-imx-xwayland-glibc-x86_64-fsl-image-validation-imx-aarch64-imx8dxlevk-toolchain-5.4-zeus.sh The toolchain would be installed into /opt/fsl-imx-xwayland/5.4-zeus   2.4.        Create a install folder $ mkdir <your install folder> Create a folder to install all of the shared libraries, binaries and configure files which built out manually in this doc. After built done, you should copy all of the contents in this folder to target board root.   2.5.        Build libavtp $ source /opt/fsl-imx-xwayland/5.4-zeus/environment-setup-aarch64-poky-linux $ git clone https://github.com/Avnu/libavtp.git $ cd libavtp $ meson build --prefix=<your install folder>/usr $ ninja -C build Copy the built out .so and .pc into the toolchain rootfs: $ sudo cp build/libavtp.so* /opt/fsl-imx-xwayland/5.4-zeus/sysroots/aarch64-poky-linux/usr/lib $ sudo cp build/meson-private/*.pc /opt/fsl-imx-xwayland/5.4-zeus/sysroots/aarch64-poky-linux/usr/lib/pkgconfig/ Copy the .so into the install folder: $ cp build/libavtp.so* <install folder>/usr/lib/ To make sure you have avtp package installed correctly:     $ pkg-config --list-all | grep avtp   2.6.        Build ALSA aaf plugin $ cd <yocto build>/tmp/work/aarch64-poky-linux/alsa-plugins/1.1.9-r0/alsa-plugins-1.1.9 $ ./configure --build=x86_64-linux --host=aarch64-poky-linux --target=aarch64-poky-linux --prefix=<install folder>/usr --disable-silent-rules --disable-dependency-tracking --with-libtool-sysroot=<yocto build>/xwayland/tmp/work/aarch64-poky-linux/alsa-plugins/1.1.9-r0/recipe-sysroot --disable-static --enable-aaf --disable-jack --disable-libav --disable-maemo-plugin --disable-maemo-resource-manager --enable-pulseaudio --enable-samplerate --with-speex=lib $ make $ make install   2.7.        Build Gstreamer AVTP plugins (1.17.x) 2.7.1.     Build Gstreamer core $ git clone https://gitlab.freedesktop.org/gstreamer/gstreamer.git $ patch -p1 < gstreamer-1.0-pass-build.patch $ meson build --prefix=<install folder>/usr $ ninja -C build $ sudo ninja -C build install After Gstreamer is installed into <your install folder>, please fix the “prefix” path in the .pc files by, and copy to the toolchain folders: $ cd <your install folder> $ grep -lR <your install folder> ./lib/pkgconfig/ | xargs sed -i 's/<your install folder>/\/usr/g' $ cp -rf ./usr/* /opt/fsl-imx-xwayland/5.4-zeus/sysroots/aarch64-poky-linux/usr/ 2.7.2.     Build gst-plugins-base $ git clone https://gitlab.freedesktop.org/gstreamer/gst-plugins-base.git $ cd gst-plugins-base $ patch -p1 < gst-plugins-base-pass-build.patch $ meson build --prefix=<your install folder>/usr $ ninja -C build $ sudo ninja -C build install   2.7.3.     Build gst-plugins-bad $ git clone https://gitlab.freedesktop.org/gstreamer/gst-plugins-bad.git $ cd gst-plugins-bad $ meson build --prefix=<your install folder>/usr $ ninja -C build $ sudo ninja -C build install   After gst-plugins-base and gst-plugins-bad installed into <your install folder>, please fix the “prefix” path in the .pc files and copy them into the toolchain folders: $ cd <your install folder> $ grep -lR <your install folder> ./lib/pkgconfig/ | xargs sed -i 's/<your install folder>/\/usr/g' $ cp -rf ./usr/* /opt/fsl-imx-xwayland/5.4-zeus/sysroots/aarch64-poky-linux/usr/   2.8.        Build H.264 SW plugins 2.8.1.     Build x264 As the yocto actually has the x264 recipes, but not included in our bblayers, we need to copy the x264 source into our bblayers path under <yocto>/source to build: $ cp -rf ./poky/meta/recipes-multimedia/x264 ./meta-openembedded/meta-multimedia/recipes-multimedia/ $ vi ./meta-openembedded/meta-multimedia/recipes-multimedia/x264_git.bb Remove the LICENSE_FLAGS line $ bitbake -f x264 -c do_install $ sudo cp -rf tmp/work/aarch64-poky-linux/x264/r2917+gitAUTOINC+72db437770-r0/image/usr/* /opt/fsl-imx-xwayland/5.4-zeus/sysroots/aarch64-poky-linux/usr/ 2.8.2.     Build gst-plugins-ugly $ git clone https://gitlab.freedesktop.org/gstreamer/gst-plugins-ugly.git $ cd gst-plugins-ugly $ meson build --prefix=<your install folder>/usr $ ninja -C build $ sudo ninja -C build install   2.8.3.     Build libav $ cp -rf poky/meta/recipes-multimedia/gstreamer/gstreamer1.0-libav meta-openembedded/meta-multimedia/recipes-multimedia/gstreamer-1.0/ Remove the LICENSE_FLAGS line $ vim ./poky/meta/recipes-multimedia/gstreamer/gstreamer1.0-libav_1.16.2.bb $ bitbake -f gstreamer1.0-libav -c do_install $ cp /opt/samba/nxf39444/imx-yocto-bsp-i.mx8dxl/xwayland/tmp/work/aarch64-poky-linux/gstreamer1.0-libav/1.16.2-r0/image/usr/lib/gstreamer-1.0/libgstlibav.so <your install folder>/usr/lib/gstreamer-1.0   2.8.4.     Install binaries Final step is to copy all of your built out files from <your install folder> into your board / root, and boot up the board. $ export GST_PLUGIN_PATH=/usr/lib/gstreamer-1.0/ $ gst-inspect-1.0 To check if the above Gstreamer plugins we built out can be found by gst-instpect.   3.  System Setup 3.1.        VLAN The ENTE_QoS is assigned to eth0 instance. So create eth0.5 for vlan id 5: $ ip link add link eth0 name eth0.5 type vlan id 5 egress-qos-map 2:2 3:3 $ ip link set eth0.5 up   3.2.        Qdiscs The TSN control plane is implemented through the TC (Traffic Control) system. The transmission algorithms specified in the FQTSS (Forwarding and Queuing for Time-Sensitive Streams) chapter of IEEE 802.1Q-2018 are supported via TC Qdiscs (Queuing Discipline). 3.2.1.     MQPRIO qdisc $ tc qdisc add dev eth0 parent root handle 100 mqprio num_tc 3 map 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 1@1 1@2 hw 1 3.2.2.     CBS qdisc Q1 CBS for audio, Q2 CBS for video: $ tc qdisc replace dev eth0 parent 100:3 handle 888 cbs idleslope 3648 sendslope -996352 hicredit 12 locredit -113 offload 1 $ tc qdisc replace dev eth0 parent 100:2 handle 777 cbs idleslope 98688 sendslope -901312 hicredit 153 locredit -1389 offload 1 3.2.3.     TimeSync Run the ptp4l and phc2sys in background, and use check_clocks to check the ptp sync works. $ ptp4l -i eth0 -f ./gPTP.cfg --step_threshold=1 & $ pmc -u -b 0 -t 1 "SET GRANDMASTER_SETTINGS_NP clockClass 248 clockAccuracy 0xfe offsetScaledLogVariance 0xffff currentUtcOffset 37 leap61 0 leap59 0 currentUtcOffsetValid 1 ptpTimescale 1 timeTraceable 1 frequencyTraceable 0 timeSource 0xa0" $ ./check_clocks -d eth0 4.  Run demo 4.1.        ALSA AAF audio To run the alsa AAF demo, please add aaf0 and converter0 plugin device into /etc/asound.conf: pcm.aaf0 {    type aaf    ifname eth0.5    addr 01:AA:AA:AA:AA:AA    prio 2    streamid AA:BB:CC:DD:EE:FF:000B    mtt 50000    time_uncertainty 1000    frames_per_pdu 12    ptime_tolerance 100 } pcm.converter0 {    type linear    slave {                  pcm "hw:0,0"                  format S16_LE    } } The “aaf0” plugin device defines the ethernet interface which AAF runs on, the socket priority which mapping to Traffic Class in kernel TC, the stream-id for the aaf streaming. The “converter0” plugin device is used for convert the S16_BE format to S16_LE for the wm8960 PCM audio.   Select one device as AVB talker, and run: $ speaker-test -p 25000 -F S16_BE -c 2 -r 48000 -D aaf0   Select one device as AVB listener, and run: $ arecord -F 25000 -t raw -f S16_BE -c 2 -r 48000 -D aaf0 | aplay -F 25000 -t raw -f S16_BE -c 2 -r 48000 -D converter0   You can hear the sound on the listener device.   You can also check which qdisc queue is used for AAF by: $ tc -s qdisc   4.2.        Gstreamer AAF audio Select one device as AVB talker, and run: $ gst-launch-1.0 clockselect. \( clock-id=realtime audiotestsrc samplesperbuffer=12 is-live=true ! audio/x-raw,format=S16BE,channels=2,rate=48000 ! avtpaafpay mtt=50000000 tu=1000000 streamid=0xAABBCCDDEEFF000B processing-deadline=0 ! avtpsink ifname=eth0.5 address=06:98:c0:22:df:35 priority=3 processing-deadline=0 \)   Select one device as AVB listener, and run: $ gst-launch-1.0 clockselect. \( clock-id=realtime avtpsrc ifname=eth0.5 ! avtpaafdepay streamid=0xAABBCCDDEEFF000B ! queue max-size-bytes=0 max-size-buffers=0 max-size-time=0 ! audioconvert ! audioresample !  alsasink device="hw:0,0" \)   5.  Packet sniffer Use tcpdump on board to dump the L2 ethernet packet: $ tcpdump -i eth0 ether proto 0x22f0 -w dump.pcap The AVTP ether protocol code is 0x22f0 embedded inside the ether frame, or you can use "vlan 5" VLAN id for tcpdump parameters to dump. Then open this dump.pcap in the windows/Linux PC by the wireshark tool, it will automatically show the protocol inside the package, it can also parser the IEEE1722 (AVTP) CVF/AFF package header as below:   To measure the package latency from transmit port (talker) to receive port (listener), you can use the tcpdump on both end-points. And compare the Epoch Time the packet dumped: "Epoch Time: 1596252905.688243000 seconds". The delta of the epoch time of the same packet is around 100us~500us. This latency actually includes the AF_PACKET clone cost in kernel netfilter, also the tcpdump application schedule latency.   6.  Revision history summarizes the changes done to this document since the initial release. Table2. Revision history Revision number Date Substantive changes 1 5/2021 Initial release    
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This doc share one OpenGL ES sample code, it is running on i.MX8 MEK board with QNX SDP7.1. HW: i.MX8 MEK board, HDMI display SW: QNX SDP7.1, i.MX8 MEK board BSP, and this sample code   This sample code will draw 3D object model, and with some animation. Reference: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8-family-arm-cortex-a53-cortex-a72-virtualization-vision-3d-graphics-4k-video:i.MX8 https://github.com/NXPmicro/gtec-demo-framework https://github.com/syoyo/tinyobjloader-c https://github.com/nothings/stb https://3dhaupt.com/futuristic-car-game-ready-download/ https://wallpapersafari.com/w/Y5JZNh https://www.pngwing.com/en/free-png-ysaus https://www.shadertoy.com/view/Ms2SWW#
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  Question: How can we generate an ARM DS5 DStream format DDR initialization script using the DRAM Register Programming Aid?  Answer: Some RPAs include a  "DStream .ds file" tab for the ARM DS5 debugger specific commands. The i.MX6UL/ULL/ULZ DRAM Register Programming Aids for example already has this supported. However, the user can easily create  the .ds format from the existing .inc format. The basic steps to convert .inc files to .ds format are as follows: 1)  Replace the one instance of setmem /16 with mem set 2)  In that same line, replace 0x020bc000 = with 0x020bc000 16 3)  Use a Replace All command to change setmem /32 with mem set 4)  Use a Replace All command to change = with 32 5)  Use a Replace All command to change // with # 6)  Save as a .ds file.   Question: When using a 528MHz DRAM Controller interface with a DDR memory of a faster speed bin, which speed bin timing options should one use? Answer: For example, let’s assume our MX6DQ design is using a DDR3 memory from a DDR3-1600 speed bin.  However, the maximum speed of the MMDC interface for the MX6DQ using DDR3 is 528MHz.  Should we use the 1600 speed bin (800MHz clock speed) or the 1066 speed bin (533MHz clock speed)?  In short, the user should use the timings rated for the maximum speed (frequency) with which you are running, in this case DDR3-1066 (533MHz).  In some cases, like when using the MX6DL, the maximum DDR frequency is 400MHz.  In this case, you would want to try and use 800 timings found in the AC timing parameters table.  However, most DDR3 devices have speed bin tables that may go only as low as 1066, in which case you would use the closest speed bin to your operational frequency (i.e. the 1066 speed bin table).     Question: Some timing parameters may specify a min and max number, which should I use? Answer: In most cases, you will want to choose the minimum timings.  Some DRAM controllers may have a tRAS_MAX timing parameter, in which case you would obviously use the maximum tRAS parameter given in the DRAM data sheet. Also, for timing parameters tAONPD and tAOFPD, we also want to use the maximum values given in the DDR3 data sheet. These represent the maximum amount of time the DDR3 device takes to turn on or off the RTT (termination), therefore, we should wait at least this amount of time before issuing any commands or accesses.   Question: Some timing parameters state things like “Greater of 3CK or 7.5ns”; which should I use? Answer: This depends on your clock speed.  Say you are running at 533MHz.  At 533MHz, 7.5ns equates to 4CKs.  In this case, 7.5ns at 533MHz is GREATER than 3CK, so we would use the 7.5ns number, or 4CKs. At 400MHz, 7.5ns equates to 3CKs.  In this case, we’d simply use 3CKs.   Question: I have a design that will throttle the DDR frequency (dynamic frequency scaling).  At full speed, I plan to run at 533MHz, and then I plan to throttle down to say 400MHz whenever possible.  Do I need to re-calculate my 400 MHz timing parameters that were initially set for 533MHz? Answer: It is not necessary to re-calculate timing parameters for 400MHz, and you can re-use the ones for 533MHz.  The timings at 533 MHz are much tighter than 400 MHz, and the key here is to NOT violate timings.  Also, it may be a bit of a hassle maintaining two sets of timing parameters, especially if later in the design, you swap DDR vendors that might require you to re-calculate some timing parameters.  It’s easier to do it once and to come up with a combined worse-case timing parameters for 533MHz, which you know will work at 400MHz.  But, if you don’t mind maintaining two sets of timing parameters, and really want to optimize timings down to the last pico-second for 400MHz, then knock yourself out.   Question: Can I use these Register programming aids for both Fly by and T- Topology ? Answer Yes The DDR register programming aid is agnostic to the DDR layout. The same spreadsheet works for both topologies. We recommend running write leveling calibration for both topologies and the values returned by the Write Leveling routine from the Freescale DDR stress test should be incorporated back to the customer specific initialization script. The DDR stress test also has a feature whereby it evaluates the write leveling values returned from calibration and increments WALAT to 1 if the values exceed a defined limit. The DDR stress test informs the user when the Write Additional latency (WALAT) exceeds the limit and should be increased by 1, and reminds the user to add it back in the customer specific initialization script if required.   WALAT - 0 00000000 WALAT: Write Additional latency. Recommend to clear these bits. Proper board design should ensure that the DDR3 devices are placed close enough to the MMDC to ensure the skew between CLK and DQS is less than 1 cycle.     Question: Can I use the DEFAULT Register programming aid values for MDOR when using an Internal OSC instead of the recommended 32.768 KHZ XTAL ? Answer No, NXP recommends reprogramming these values based on the worse case frequency (Max clock) of the internal OSC of the device to guarantee JEDEC timings are met. Please refer to Internal Oscillator Accuracy considerations for the i.MX 6 Series for more details  
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Steps to replace the Wi-Fi/Bluetooth firmware on the i.MX 8M series on Linux    Applicable to versions L5.4.47, L5.4.70, L5.10.9   1. Download the newest firmware. you can download the attachment in this thread and unzip it. 2. Copy it to the EVK board. 3. Copy the firmware to /lib/firmware/nxp   root@imx8mmevk: cp pcieuart8997_combo_v4.bin sdiouart8987_combo_v0.bin  /lib/firmware/nxp If the Linux version is L5.4.3,Then the step3 is to copy firmware to lib/firmware/mrvl/ root@imx8mmevk: cp pcieuart8997_combo_v4.bin sdiouart8987_combo_v0.bin  /lib/firmware/mrvl    
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