[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343521 

Computer On Module • Processor Freescale i.MX287, 454 MHz • RAM 128MB DDR2-400 SDRAM • ROM 128MB NAND Flash • Power supply Single 3.1V to 5.5V • Size 40mmX35mm • Temp.-Range -40°C..85°C Key Features • Two 10/100Mbps Ethernet ports with IEEE1588 support • Two High-Speed USB 2.0 ports • One colour LCD controller • Two CAN interfaces • 4 wire Touchscreen interface • Several peripheral interfaces: UART, SD-CARD, I2C, PWM, Serial Audio, SPI • Power management optimized for long battery life • 3.3V I/O OS Support • Windows Embedded CE 6.0 • Linux 2.6.35 Application：Building control, factory automation, printers and security panels, HMI, industrial control media gateways / accessories, portable medical devices, energy-saving Energy Gateway / Meter For more information, please see Attachment We can provide a complete solution

Background : Some customer wants to know the DRAM's MR register value. But, For now, we do not have any documentation or binary to complete this. So, this article aim to show how to read this register.   Hardware environment : i.MX8ULP EVK board Software environment : uboot-imx : lf_v2024.04   1. The related registers information are as following:   DENALI CTL 165 [READ MODEREG[24:8]] Read the specified memory mode register from specified chip when start bit set. Bits (7:0) define the memory mode register and bits (15:8) define the chip select. Set bit (16) to 1 to trigger.   DENALI CTL 166 [PERIPHERAL MRR - DATA[31:0]] Data and chip returned from memory mode register read requested by the READ MODEREG parameter. Bits (7:0) indicate the read data and bits (15:8) indicate the chip. READ-ONLY   2. Test result :         Type the below command: mrr <chip_select MR_register>  Like the below picture, when type the mrr 0 c, it means the chip select is 1 and the MR register is MR12, then the value of MR12 register can be output , is 0x1c.     Note : When read the MR register, must make sure the register has read right. Because most of MR register only have write right. you can check about it on JDEC spec document.   If you want to get the test binary file, please contact to me, i will send it to you.

Dear,   We want to start application program from bootloader, we have below questions: We we use I.MX6UL bootrom start BootLoader， we need use mkimage.sh, compile and generator bin file, then we convert to executable file. If we need use Bootloader run application program,whether application image also need convert by mkimage.sh?  The file which convert by mkimage.sh is compressed file. we do not know its format, how about its start address, how to realize the the address jump, do you have example? Thanks.  

Hello Android users Otto has posted on the Element14 community some clear tutorial (accessible following the link below) to build Android from source. RIoTboard: Building Android from Source | element14 I recommend you to start following those steps to properly setup the Android tools. Happy Source Programming Greg

Attached slides introduce the i.MX95 Power management with following topics: SoC Power Architecture Power Management with BSP Power on/off & Reboot Suspend Implementation Low Power Run

There are two ways to enable support for the imx95-19x19-evk board:   1.  Directly replace the flash.bin from the Yocto release. 1). depoly LSDK2512 on imx95-15x15-evk board which is supported in Debian LSDK2512     A:    $ flex-installer -i pf -d /dev/sdX -F     B： $ flex-installer -i auto -m imx95evk -d /dev/sdX   2). Download prebuild flash.bin for imx95-19x19-evk board from Yocto release:     A: download： https://www.nxp.com/webapp/sps/download/license.jsp? colCode=L6.12.20-2.0.0_MX95&appType=file1&DOWNLOAD_ID=null     B： Extract the downloaded file to obtain the flash.bin file: imx-boot-imx95-19x19-lpddr5-evk-sd.bin-flash_all   3). Overwrite flash.bin     $ sudo umount /dev/sdX; sudo dd if=imx-boot-imx95-19x19-lpddr5-evk-sd.bin-flash_all of=/dev/sdX bs=1024 seek=32   4). Insert the prepared SD card into the board and power it on. After entering the U-Boot prompt， set the boot command:     => setenv bootcmd "setenv bootargs 'root=/dev/mmcblk1p3 rw rootwait console=ttyLP0,115200 earlycon';ext2load mmc 1:1 0x90400000 Image;ext2load mmc 1:1 0x93000000 imx95-19x19-evk.dtb;booti 0x90400000 - 0x93000000"; saveenv     => reset   The Debian system will start automatically.   2. Build the BSP image using FlexBuild: 1).  clone the Flexbuild source code and apply the patch as attached. 2). build the bsp and boot images:       $ bld bsp -m imx95evk       $ bld boot -m imx95evk or download the pre-built image at: http://sun.ap.freescale.net/images/debian/lsdk2512/firmware_imx95evk_19x19_sdboot.img 3). install the image:       $ ./flex-installer -f firmware_imx95evk_sdboot.img -d /dev/sdX -m imx95evk -b boot_IMX_arm64_lts_6.12.20.tar.zst -r rootfs_lsdk2512_debian_imx95evk.tar.zst 4).  Insert the prepared SD card into the board and power it on. After entering the U-Boot prompt, run the following command to boot board:       u-boot=> bootflow scan -lb

This document explains how to enable and test Bluetooth 6LoWPAN (IPv6 over Low-power Wireless Personal Area Networks) in the i.MX Linux BSP.   Environment   i.MX Linux BSP 6.6.52-2.2.0 (based on Yocto scrathgap) i.MX 93 EVK (2 units) An Embedded Artists 2EL M.2 module with the Murata LBES5PL2EL module (containing NXP IW612) is inserted into the i.MX 93 EVK's M.2 slot and connected to the onboard Wi-Fi/BT antenna. One i.MX 93 EVK will serve as the Peripheral device, while the other will act as the Central device. It should also work with i.MX 8 and 9 series evaluation kit equipped with Bluetooth LE modules.   Configurations   Although the Linux kernel includes a Bluetooth 6LoWPAN driver, it is disabled in the i.MX Linux BSP. Therefore, we will modify the kernel configuration to enable it. Add 2 settings below in kernel configuration file (imx_v8_defconfig) to build the required drivers as modules: CONFIG_6LOWPAN=m CONFIG_BT_6LOWPAN=m These settings can be found in the following section of the Linux kernel menuconfig. CONFIG_6LOWPAN: Depends on: NET [=y] && IPV6 [=y] Location: -> Networking support (NET [=y]) -> Networking options -> 6LoWPAN Support (6LOWPAN [=m]) CONFIG_6LOWPAN  CONFIG_BT_6LOWPAN: Depends on: NET [=y] && BT_LE [=y] && 6LOWPAN [=y] Location: -> Networking support (NET [=y]) -> Bluetooth subsystem support (BT [=y]) -> Bluetooth Low Energy (LE) features (BT_LE [=y]) -> Bluetooth 6LoWPAN support (BT_6LOWPAN [=m]) Rebuild the image containing the Linux kernel and make sure that the required drivers are present in the following paths. /lib/modules/6.6.52-ge0f9e2afd4cf-dirty/kernel/net/6lowpan/6lowpan.ko /lib/modules/6.6.52-ge0f9e2afd4cf-dirty/kernel/net/bluetooth/bluetooth_6lowpan.ko   Operations for Peripheral device   Boot the Peripheral device EVK and log in as the root user. NXP i.MX Release Distro 6.6-scarthgap imx93-11x11-lpddr4x-evk ttyLP0 imx93-11x11-lpddr4x-evk login: root Load the NXP Bluetooth UART driver to enable Bluetooth. # modprobe btnxpuart Start the Bluetooth hci0 interface with the hciconfig command. # hciconfig hci0 up Type hciconfig command to check the BD Address of the Bluetooth hci0 interface and confirm that its status is "UP RUNNING". # hciconfig -a hci0: Type: Primary Bus: UART BD Address: D0:17:69:12:34:56 ACL MTU: 1021:7 SCO MTU: 120:6 UP RUNNING RX bytes:862 acl:0 sco:0 events:59 errors:0 TX bytes:1085 acl:0 sco:0 commands:58 errors:0 Features: 0xbf 0xfe 0x8f 0xfe 0xdb 0xff 0x7b 0x87 Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3 Link policy: RSWITCH SNIFF Link mode: PERIPHERAL ACCEPT Name: 'imx93-11x11-lpddr4x-evk' Class: 0x200000 Service Classes: Audio Device Class: Miscellaneous, HCI Version: 5.4 (0xd) Revision: 0x8300 LMP Version: 5.4 (0xd) Subversion: 0x1015 Manufacturer: NXP Semiconductors (formerly Philips Semiconductors) (37) Load the Bluetooth 6LoWPAN driver. # modprobe bluetooth_6lowpan Enable Bluetooth 6LoWPAN. # echo 1 > /sys/kernel/debug/bluetooth/6lowpan_enable Start Bluetooth advertising and waits for a connection request from the Central device. # bluetoothctl advertise on   Operations for Central device   Boot the Central device EVK and log in as the root user. NXP i.MX Release Distro 6.6-scarthgap imx93-11x11-lpddr4x-evk ttyLP0 imx93-11x11-lpddr4x-evk login: root Load the NXP Bluetooth UART driver to enable Bluetooth. # modprobe btnxpuart Start the Bluetooth hci0 interface with the hciconfig command. # hciconfig hci0 up Type hciconfig command to check the BD Address of the Bluetooth hci0 interface and confirm that its status is "UP RUNNING". # hciconfig -a hci0: Type: Primary Bus: UART BD Address: D0:17:69:AB:CD:EF ACL MTU: 1021:7 SCO MTU: 120:6 UP RUNNING RX bytes:862 acl:0 sco:0 events:59 errors:0 TX bytes:1085 acl:0 sco:0 commands:58 errors:0 Features: 0xbf 0xfe 0x8f 0xfe 0xdb 0xff 0x7b 0x87 Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3 Link policy: RSWITCH SNIFF Link mode: PERIPHERAL ACCEPT Name: 'imx93-11x11-lpddr4x-evk' Class: 0x200000 Service Classes: Audio Device Class: Miscellaneous, HCI Version: 5.4 (0xd) Revision: 0x8300 LMP Version: 5.4 (0xd) Subversion: 0x1015 Manufacturer: NXP Semiconductors (formerly Philips Semiconductors) (37) Load the Bluetooth 6LoWPAN driver. # modprobe bluetooth_6lowpan Enable Bluetooth 6LoWPAN. # echo 1 > /sys/kernel/debug/bluetooth/6lowpan_enable Send a connection request to the Peripheral device. (In this example, the BD address of the Peripheral device is D0:17:69:12:34:56.) # echo "connect D0:17:69:12:34:56 1" > /sys/kernel/debug/bluetooth/6lowpan_control After waiting for a few tens of seconds, the bt0 network interface will appear. (At the same time, the bt0 network interface will appear on the Peripheral device that accepted the connection.) # ifconfig bt0 bt0: flags=4161<UP,RUNNING,MULTICAST> mtu 1280 inet6 fe80::d017:69ff:feab:cdef prefixlen 64 scopeid 0x20<link> unspec D0-17-69-AB-CD-EF-00-00-00-00-00-00-00-00-00-00 txqueuelen 1000 (UNSPEC) RX packets 9 bytes 884 (884.0 B) RX errors 0 dropped 4 overruns 0 frame 0 TX packets 13 bytes 1069 (1.0 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 The Central device and Peripheral device are now connected via Bluetooth 6LoWPAN.   Testing Send a ping from the Central device to the Peripheral device. (In this example, the IPV6 address of the Peripheral device is fe80::d017:69ff:fe12:3456.) # ping6 fe80::d017:69ff:fe12:3456%bt0 PING fe80::d017:69ff:fe12:3456%bt0 (fe80::d017:69ff:fe12:3456%bt0) 56 data bytes 64 bytes from fe80::d017:69ff:fe12:3456%bt0: icmp_seq=1 ttl=64 time=181 ms 64 bytes from fe80::d017:69ff:fe12:3456%bt0: icmp_seq=2 ttl=64 time=125 ms 64 bytes from fe80::d017:69ff:fe12:3456%bt0: icmp_seq=3 ttl=64 time=67.7 ms 64 bytes from fe80::d017:69ff:fe12:3456%bt0: icmp_seq=4 ttl=64 time=56.1 ms ...   Benchmarking   Run the iperf3 server on the Peripheral device. # iperf3 -s Run the iperf3 benchmark on the Central device. For example, check the TCP connections. # iperf3 -V -c fe80::d017:69ff:fe12:3456%bt0 You can also check UDP connections. For example, the following example sends UDP 200Kbps bandwidth. # iperf3 -V -c fe80::d017:69ff:fe12:3456%bt0 -u -b 200K   Disclaimer   This document is provided as a reference for utilizing NXP products. Please refer to the official product manuals and application notes for formal specifications. Due to differences in software versions and other conditions, actual behavior may differ from the descriptions provided. This document does not verify all functions, so please be sure to conduct appropriate validation and testing to ensure suitability for your intended use.  

We are pleased to announce that Config Tools for i.MX v25.09 are now available. Downloads & links To download the installer for all platforms, please login to our download site via:  https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX Please refer to  Documentation  for installation and quick start guides. For further information about DDR config and validation, please go to this  blog post. Release Notes Full details on the release (features, known issues...) • The Release Notes format is updated from plain text to markdown. • The newly generated configuration includes the default NXP copyright notice and is licensed under the BSD-3-Clause license. • DDR tool – ODT and Driver Strength Updates for LP4/LP5 on i.MX 943 and i.MX 95 – Improved DRAM Configuration for i. MX 9x devices – Multicore support is enabled for DDR tests on i.MX 943 and i.MX 95 – Linux support for the DDR tool – Vref DQ Setting now available in the GUI – Board-agnostic SM Support for i.MX 943 and i.MX 95 – DDR part number entry is supported in the GUI – Enhanced logging from the target application – Stress test repetition option is enabled – Updated ODT shmoo scenario values on i.MX 943 and i.MX 95 – Support for SNPS FW and PHY Init 2024.09 SP2 on i.MX 943 and i.MX 95 – AHAB image update to align with BSP for CES parts on i.MX 943 and i.MX 95 – New configuration support for 15x15 on i.MX 943 – Improved bus configuration for single-channel setups – LP4/LP5 CS signal configuration now exposed in the GUI for i.MX 943 and i.MX 95 • Clocks – Supported input frequency setting • System Manager – Initial version of the tool

Symptoms   On i.MX8MP, when inputting a 80% duty, 0.4V-1.8V, 3KHz square wave, we observed that the system may hang. We also tested i.MX8MN and i.MX8MM and observed the same phenomenon. In i.MX8MN RM, there's a note in GPC chapter:     We believe that the issue described in this note exists not only in the iMX8MN, but also in the iMX8MP and iMX8MM. Meanwhile, there is not only a problem with power down in this issue, but also a problem with wait mode. Diagnosis   In debugging, we find that avoiding accessing LPCR_A53_AD register in imx_set_cluster_powerdown can fix the issue. So we think that due to frequently power up/down of cores, cores have chances failed to power up. When the IRQ behavior become more complex, because the IRQ is an async event, it will come in any time. if the wait mode is enabled, in some conner case, the GPC internal LPM mode state machine will run into problem, then lead to system failure. Solution   1. A workaround patch that bypass the wait mode setting during the cpuidle.. See the patch attached. 2. Will add the Note about "SCU power down should not be enabled in wait mode" to i.MX8MP and i.MX8MM RM. 3. Will try to identify this issue into errta document, ticket TKT0632147.

We have validated Toshiba Smart NAND in our i.MX6SX platform, and boot successfully. The results are as below: 1. chip part number: THGBR2G5D1JTA00,  page_size: 16k+64  pages_per_block: 256 2. test platform: i.MX6SX Some information to take care of: 1. The pin assignment of smart nand is different from common raw nand, that is, Nand pin1 must connect to Vcc, pin2 connects to Vss, pin23 connects to VssQ, pin24 connects to VccQ, pin38 connects to VccQ 2. The ECC layout of FCB page itself must be set according to the i.MX6SX RM, otherwise FCB can't be read correctly. 3. EccBlock0EccType and EccBlockNEccType in FCB must be set as 0, and raw data can be put in DBBT and firmware without any ECC check codes.

                For the SPI NOR booting on fuse steps. 1.      Please boot your PCB on uboot and type below command for fuse boot setting. MX6Q SABRESD-MFG U-Boot > imxotp blow --force 5 0x0a000030 MX6Q SABRESD-MFG U-Boot > imxotp read 5 Reading fuse at index: 0x5 Fuse at (index: 0x5) value: 0xA000030 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x0 MX6Q SABRESD-MFG U-Boot > imxotp blow --force 6 0x10 Current fuse at (index: 0x6) value: 0x0 Blowing fuse at index: 0x6, value: 0x10 Reloading shadow registers... Operation succeeded fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > 2.      Set the boot mode for 00 as Boot from fuses 3.      You could see the SPI clock on scope after re power on.

Summary of the Issue: We have had customers reporting failure to run MC and SC production parts at 1GHz or higher frequencies. The signature of the fail is that the system will hang once it tries to ramp from the boot frequency of 800MHz to 1GHz or higher. The root cause was tracked to the setting of the LDO_VOLT_CHANGE_EN fuse in production parts. The LDO_VOLT_CHANGE_EN fuse sets the LDO boot voltage to either 1.15V (indicated by a fuse setting of “1”) or 1.1V  (indicated by a fuse setting of “0”). In production parts the fuse is set to “1”, i.e. 1.15V, since this is the optimal setting based on characterization data. On pre-production units the LDO voltage was set to the lower setting of 1.1V (i.e. fuse set to “0”). The reason this is a problem with MC/SC parts is because the fuse is read by the ROM during boot and overwrites the LDO ramp rate bits in the PMU_MISC2 register based on the setting of the fuse. When the LDO_VOLT_CHANG_EN fuse is set to “1” then the LDO ramp up time to spec voltage is set (in PMU_MISC2) to 500uS instead of the 50uS assumed by the CPUFreq driver. This will cause the system to hang when transitioning from the boot frequency to a higher frequency/voltage point since the required voltage to support the higher frequency is not yet present. In real terms, customers who have production i.MX 6Quad/6Dual/6DualLite and 6 Solo parts have seen failures to ramp their products to 1GHz or higher frequencies. This is completely fixed by a software patch that corrects the LDO ramp setting in the PMU_MISC_2 register by setting it back to the fastest ramp time. Note that the LDO_VOLT_CHANGE_EN fuse is not in the reference manual since it is not a customer visible fuse. It is programmed and locked at final test. This is a mandatory fix for all customers. Affected Parts: i.MX 6Quad – all SC and MC parts, consumer and automotive. Industrial MC parts not yet shipping. i.MX 6Dual – all SC and MC parts, consumer and automotive. Industrial MC parts not yet shipping. i.MX 6DualLite – all MC parts consumer parts. Automotive and industrial MC parts not yet shipping. i.MX 6Solo – all MC consumer parts. Automotive and industrial MC parts not yet shipping. Patch Availability and Location: Patches exist for both Linux and Android. They are available on freescale.com. See below for more details. i.MX 6Quad – www.freescale.com/imx6q i.MX 6Dual – www.freescale.com/imx6d i.MX 6DualLite – www.freescale.com/imx6dl  i.MX 6Solo – www.freescale.com/imx6s Select the “Software and Tools” tab and then expand the section “Updates and Patches”.  The relevant patches are: Linux – L3.0.35_1.1.1_LDO_PATCH (i.MX 6Quad/6Dual) Linux – L3.0.35_3.0.3_LDO_PATCH (i.MX 6DualLite/6Solo) Android – IMX6_R13.4103_ANDROID_LDO_PATCH (i.MX 6Quad/6Dual/6DualLite/6Solo) Communication Roll-out: i.MX FAE’s: done (via maillist). Will post copy of this email to i.MX support space by end of day 1 st March. i.MX DFAE’s: 8 th March. Customer notification: 8 th March. i.MX community: 8 th March (to coincide with customer notification). We are also working on an engineering bulletin that describes the change for customers who are not using our provided Linux and Android BSP’s. Target date: TBD. But goal is to make this available on/around mid-March. Best regards, Amanda and Kyle This document was generated from the following discussion: i.MX 6 Series LDO Ramp Issue: Linux and Android Patches Now Available

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-345322 

When I use QMediaPlayer (Qt5.1.1) to play a FHD video, the CPU (imx6dl) usage turns very high and the output is not fluid and also has some frame drop. I found a patch that claims to solve this problem (links below are taking about the same thing) : adding zero-copy-QSGVideoNode for imx6 - Qt by Digia https://www.mail-archive.com/[email protected]/msg08580.html After patch appliance and recompilation of Qt Library and program rebuild, the performance issue remains the same. Does anybody know how to enable this property correctly? Have I missed some points or mandatory steps? Any comment will be appreciated, thanks!

RidgeRun provides a fully featured Embedded Linux Software Development Kit for Freescale iMX6 based applications processors. Freescale iMX6 platform delivers high performance, power efficient applications processors with a robust support network and software portfolio including open source. The complete platform allows for differentiation and rapid development of applications from wireless handsets to other multimedia-enhanced devices. The i.MX6 series processors are a scalable multicore platform that includes single-, dual- and quad-core families based on the ARM® Cortex™-A9 architecture. This architecture is a robust - cross industry and product platform. Whether your product is targeted at consumer electronics, industrial, automotive or security related, this flexible, scalable architecture combined with RidgeRun's easy-to-use SDK's and extension products allows you to concentrate your effort of differentiating features and not product infrastructure. FEATURES Boot loader 2013.07 Linux kernel 3.0.35-4.0.0 Gstreamer-0.10.36 Freescale gst-plugins 3.0.7 Hardware based audio and video codecs SD and NFS file system support Boot from SD3, SD4 or SPI-NOR with an easy installation (Boundary devices boards only) Toolchain to linaro 2012.03 for software floating point and 2013.03 for hardware floating point support For more info please contact: [email protected] or Please Click -> Contact Us

Here are two patchs: Patch 1: 0001-I.MX6-SSI_ASRC_P2P_Capture-for-SabreSD-board-Kernel-.patch Patch 2: 0001-I.MX6-SSI_ASRC_P2P-Capture-for-SebreSD-board.patch Patch 1 is based on patch 2.     memory <-- ASRC_Output FIFO | ASRC_Input FIFO <-- SSI_RX FIFO <-- Audio Codec                                              |           |     ASRC Out clk ASRCK1 <---|           |--->   ASRC In clk None                                              |           |     ASRC OutPut width            |           |       ASRC InPut width and data format     is set by arecord            <---|           |--->   is set by ASRC P2P parameter     parameter                          |           |                                             |           |     support 44100/48000          |           |       support 44100/48000     and S24_LE/S16_LE     <---|           |--->   and S24_LE/S16_LE    You can use:     arecord -Dhw:0,1 -c 2 -f S16_LE/S24_LE -r 44100/48000 XXX.wav     aplay XXX.wav     to test this patch.

Hi All, The new i.MX 6 SL L3.0.35_2.1.0 release is now available on the http://www.freescale.com/site. ·         Files available # Name Description 1 L3.0.35_2.1.0_LINUX_DOCS i.MX   6SoloLite Linux BSP Documentation. Includes Release Notes, Reference Manual,   User guide. API Documentation 2 L3.0.35_2.1.0_LINUX_MMDOCS i.MX 6SoloLite Linux Multimedia Codecs   Documentation. Includes   CODECs Release Notes and User's Guide 3 L3.0.35_2.1.0_ER_SOURCE i.MX   6SoloLite Linux BSP Source Code Files 4 L3.0.35_2.1.0_MM_CODECS i.MX   6SoloLite Linux Multimedia Codecs Sources 5 L3.0.35_2.1.0_AACP_CODECS i.MX   6SoloLite Linux AAC Plus Codec 6 L3.0.35_2.1.0_DEMO_IMAGE i.MX   6SoloLite Linux Binary Demo Files ·         Target HW boards o   i.MX6SL-EVK ·         New features o   Updated thermal equation for i.MX 6SoloLite o   Added Fuse check for all the devices o   Enabled DISPLAY power gating feature on TO1.2 ·         Known issues o   For known issues and limitations please consult the release notes.

ESAI module in i.MX6D/I.MX6D/I.MX6DL/I.MX6S supports several RESET funtions: Reset ESAI Core, Reset both Transmitter and Receiver, Reset Transmitter individually, Reset Receiver individually, Reset Transmitter FIFO and Reset Receiver FIFO. Below is a simple diagram for these RESET functions, which shows reset object and related register configurations. 1.Reset ESAI Core After setting ESAI_ECT ERST bit to be 1, ESAI core and configuration registers will be reset, but Transmitter and Recevier FIFOs can't be reset by the operation. 2. Reset both Transmitter and Receiver After setting ESAI_PCRC & ESAI_PRRC to be 0x000, Transmitter and Receiver can both be reset, The RESET is also called "Personal Reset" in it's reference manual. About PCRC & PRRC bits functionality, we can see the table: From the table, ESAI_PCRC=0x000 and ESAI_PRRC=0x000 will make ESAI disconnet external ESAI pins, and ESAI's Tranmitter and Receiver can't communicate with external audio codec.  See ESAI_PCRC and ESAI_PRRC register below: ---ESAI_PCRC register ---ESAI_PRRC register There are 12 bits in each register to contorl "DISCONNECTION" OR "CONNECTION" with ESAI pins. So for normal operations of ESAI, these 2 registers can't be changed. 3.Reset Transmitter & Receiver individually By setting ESAI_TCR[TPR]=1, Transmitter can be reset individually, and not affect Receiver. By setting ESAI_RCR[RPR]=1, Receiver can be reset individually, and not affect Transmitter . In reference manual, the reset is called "personal reset / individual reset", actually they means the same thing: --Reset Transmitter individually. --Reset Receiver individually. 4.Reset Transmitter FIFO and Reset Receiver FIFO ---By setting ESAI_TFCR[TFR]=1, Tranmitter FIFIO can be reset. ---By setting ESAI_RFCR[RFR]=1, Receiver FIFO can be reset. The Reset requires ESAI is operational, which means at least one pin is defined as an ESAI pin. NXP TIC team Weidong Sun

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343802