P3T1755 Demo   In this space I want to show you the things that you can create usign our products.   In  this demo I demostrate a use case creating a GUI for a Temperature Sensor.   We can create modern GUIs and more with LVGL combined with our powerful processors.               CPU USAGE As we can see  the CPU usage for this demo is around 2%   Pictures         This demo is based on the previous publused articles.   References: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Adding-support-to-P3T1755-on-Linux/ta-p/1855874 https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/How-to-run-LGVL-on-iMX-using-framebuffer/ta-p/1853768  

Symptoms   On i.MX8MP, when inputting a 80% duty, 0.4V-1.8V, 3KHz square wave, we observed that the system may hang. We also tested i.MX8MN and i.MX8MM and observed the same phenomenon. In i.MX8MN RM, there's a note in GPC chapter:     We believe that the issue described in this note exists not only in the iMX8MN, but also in the iMX8MP and iMX8MM. Meanwhile, there is not only a problem with power down in this issue, but also a problem with wait mode. Diagnosis   In debugging, we find that avoiding accessing LPCR_A53_AD register in imx_set_cluster_powerdown can fix the issue. So we think that due to frequently power up/down of cores, cores have chances failed to power up. When the IRQ behavior become more complex, because the IRQ is an async event, it will come in any time. if the wait mode is enabled, in some conner case, the GPC internal LPM mode state machine will run into problem, then lead to system failure. Solution   1. A workaround patch that bypass the wait mode setting during the cpuidle.. See the patch attached. 2. Will add the Note about "SCU power down should not be enabled in wait mode" to i.MX8MP and i.MX8MM RM. 3. Will try to identify this issue into errta document, ticket TKT0632147.

We have validated Toshiba Smart NAND in our i.MX6SX platform, and boot successfully. The results are as below: 1. chip part number: THGBR2G5D1JTA00,  page_size: 16k+64  pages_per_block: 256 2. test platform: i.MX6SX Some information to take care of: 1. The pin assignment of smart nand is different from common raw nand, that is, Nand pin1 must connect to Vcc, pin2 connects to Vss, pin23 connects to VssQ, pin24 connects to VccQ, pin38 connects to VccQ 2. The ECC layout of FCB page itself must be set according to the i.MX6SX RM, otherwise FCB can't be read correctly. 3. EccBlock0EccType and EccBlockNEccType in FCB must be set as 0, and raw data can be put in DBBT and firmware without any ECC check codes.

                For the SPI NOR booting on fuse steps. 1.      Please boot your PCB on uboot and type below command for fuse boot setting. MX6Q SABRESD-MFG U-Boot > imxotp blow --force 5 0x0a000030 MX6Q SABRESD-MFG U-Boot > imxotp read 5 Reading fuse at index: 0x5 Fuse at (index: 0x5) value: 0xA000030 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x0 MX6Q SABRESD-MFG U-Boot > imxotp blow --force 6 0x10 Current fuse at (index: 0x6) value: 0x0 Blowing fuse at index: 0x6, value: 0x10 Reloading shadow registers... Operation succeeded fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > 2.      Set the boot mode for 00 as Boot from fuses 3.      You could see the SPI clock on scope after re power on.

Attached patch enable dual display on i.MX51 wince6. It will set DI0 as main display.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343802 

Summary of the Issue: We have had customers reporting failure to run MC and SC production parts at 1GHz or higher frequencies. The signature of the fail is that the system will hang once it tries to ramp from the boot frequency of 800MHz to 1GHz or higher. The root cause was tracked to the setting of the LDO_VOLT_CHANGE_EN fuse in production parts. The LDO_VOLT_CHANGE_EN fuse sets the LDO boot voltage to either 1.15V (indicated by a fuse setting of “1”) or 1.1V  (indicated by a fuse setting of “0”). In production parts the fuse is set to “1”, i.e. 1.15V, since this is the optimal setting based on characterization data. On pre-production units the LDO voltage was set to the lower setting of 1.1V (i.e. fuse set to “0”). The reason this is a problem with MC/SC parts is because the fuse is read by the ROM during boot and overwrites the LDO ramp rate bits in the PMU_MISC2 register based on the setting of the fuse. When the LDO_VOLT_CHANG_EN fuse is set to “1” then the LDO ramp up time to spec voltage is set (in PMU_MISC2) to 500uS instead of the 50uS assumed by the CPUFreq driver. This will cause the system to hang when transitioning from the boot frequency to a higher frequency/voltage point since the required voltage to support the higher frequency is not yet present. In real terms, customers who have production i.MX 6Quad/6Dual/6DualLite and 6 Solo parts have seen failures to ramp their products to 1GHz or higher frequencies. This is completely fixed by a software patch that corrects the LDO ramp setting in the PMU_MISC_2 register by setting it back to the fastest ramp time. Note that the LDO_VOLT_CHANGE_EN fuse is not in the reference manual since it is not a customer visible fuse. It is programmed and locked at final test. This is a mandatory fix for all customers. Affected Parts: i.MX 6Quad – all SC and MC parts, consumer and automotive. Industrial MC parts not yet shipping. i.MX 6Dual – all SC and MC parts, consumer and automotive. Industrial MC parts not yet shipping. i.MX 6DualLite – all MC parts consumer parts. Automotive and industrial MC parts not yet shipping. i.MX 6Solo – all MC consumer parts. Automotive and industrial MC parts not yet shipping. Patch Availability and Location: Patches exist for both Linux and Android. They are available on freescale.com. See below for more details. i.MX 6Quad – www.freescale.com/imx6q i.MX 6Dual – www.freescale.com/imx6d i.MX 6DualLite – www.freescale.com/imx6dl  i.MX 6Solo – www.freescale.com/imx6s Select the “Software and Tools” tab and then expand the section “Updates and Patches”.  The relevant patches are: Linux – L3.0.35_1.1.1_LDO_PATCH (i.MX 6Quad/6Dual) Linux – L3.0.35_3.0.3_LDO_PATCH (i.MX 6DualLite/6Solo) Android – IMX6_R13.4103_ANDROID_LDO_PATCH (i.MX 6Quad/6Dual/6DualLite/6Solo) Communication Roll-out: i.MX FAE’s: done (via maillist). Will post copy of this email to i.MX support space by end of day 1 st March. i.MX DFAE’s: 8 th March. Customer notification: 8 th March. i.MX community: 8 th March (to coincide with customer notification). We are also working on an engineering bulletin that describes the change for customers who are not using our provided Linux and Android BSP’s. Target date: TBD. But goal is to make this available on/around mid-March. Best regards, Amanda and Kyle This document was generated from the following discussion: i.MX 6 Series LDO Ramp Issue: Linux and Android Patches Now Available

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-345322 

RidgeRun provides a fully featured Embedded Linux Software Development Kit for Freescale iMX6 based applications processors. Freescale iMX6 platform delivers high performance, power efficient applications processors with a robust support network and software portfolio including open source. The complete platform allows for differentiation and rapid development of applications from wireless handsets to other multimedia-enhanced devices. The i.MX6 series processors are a scalable multicore platform that includes single-, dual- and quad-core families based on the ARM® Cortex™-A9 architecture. This architecture is a robust - cross industry and product platform. Whether your product is targeted at consumer electronics, industrial, automotive or security related, this flexible, scalable architecture combined with RidgeRun's easy-to-use SDK's and extension products allows you to concentrate your effort of differentiating features and not product infrastructure. FEATURES Boot loader 2013.07 Linux kernel 3.0.35-4.0.0 Gstreamer-0.10.36 Freescale gst-plugins 3.0.7 Hardware based audio and video codecs SD and NFS file system support Boot from SD3, SD4 or SPI-NOR with an easy installation (Boundary devices boards only) Toolchain to linaro 2012.03 for software floating point and 2013.03 for hardware floating point support For more info please contact: [email protected] or Please Click -> Contact Us

ESAI module in i.MX6D/I.MX6D/I.MX6DL/I.MX6S supports several RESET funtions: Reset ESAI Core, Reset both Transmitter and Receiver, Reset Transmitter individually, Reset Receiver individually, Reset Transmitter FIFO and Reset Receiver FIFO. Below is a simple diagram for these RESET functions, which shows reset object and related register configurations. 1.Reset ESAI Core After setting ESAI_ECT ERST bit to be 1, ESAI core and configuration registers will be reset, but Transmitter and Recevier FIFOs can't be reset by the operation. 2. Reset both Transmitter and Receiver After setting ESAI_PCRC & ESAI_PRRC to be 0x000, Transmitter and Receiver can both be reset, The RESET is also called "Personal Reset" in it's reference manual. About PCRC & PRRC bits functionality, we can see the table: From the table, ESAI_PCRC=0x000 and ESAI_PRRC=0x000 will make ESAI disconnet external ESAI pins, and ESAI's Tranmitter and Receiver can't communicate with external audio codec.  See ESAI_PCRC and ESAI_PRRC register below: ---ESAI_PCRC register ---ESAI_PRRC register There are 12 bits in each register to contorl "DISCONNECTION" OR "CONNECTION" with ESAI pins. So for normal operations of ESAI, these 2 registers can't be changed. 3.Reset Transmitter & Receiver individually By setting ESAI_TCR[TPR]=1, Transmitter can be reset individually, and not affect Receiver. By setting ESAI_RCR[RPR]=1, Receiver can be reset individually, and not affect Transmitter . In reference manual, the reset is called "personal reset / individual reset", actually they means the same thing: --Reset Transmitter individually. --Reset Receiver individually. 4.Reset Transmitter FIFO and Reset Receiver FIFO ---By setting ESAI_TFCR[TFR]=1, Tranmitter FIFIO can be reset. ---By setting ESAI_RFCR[RFR]=1, Receiver FIFO can be reset. The Reset requires ESAI is operational, which means at least one pin is defined as an ESAI pin. NXP TIC team Weidong Sun

Hello Android users Sagar has posted on the Element14 community three clear tutorials (accessible following the link below) to create an Android application on the RiOTboard. RIoTboard: Part 1: Build an Android app on RIoT... | element14 RIoTboard: Part 2: Build an Android App on RIoT... | element14 RIoTboard: Part 3: Build an Android App on the ... | element14 I recommend you to start following those steps to ensure a proper setup of the Android tools. Happy Programming Greg

Here are two patchs: Patch 1: 0001-I.MX6-SSI_ASRC_P2P_Capture-for-SabreSD-board-Kernel-.patch Patch 2: 0001-I.MX6-SSI_ASRC_P2P-Capture-for-SebreSD-board.patch Patch 1 is based on patch 2.     memory <-- ASRC_Output FIFO | ASRC_Input FIFO <-- SSI_RX FIFO <-- Audio Codec                                              |           |     ASRC Out clk ASRCK1 <---|           |--->   ASRC In clk None                                              |           |     ASRC OutPut width            |           |       ASRC InPut width and data format     is set by arecord            <---|           |--->   is set by ASRC P2P parameter     parameter                          |           |                                             |           |     support 44100/48000          |           |       support 44100/48000     and S24_LE/S16_LE     <---|           |--->   and S24_LE/S16_LE    You can use:     arecord -Dhw:0,1 -c 2 -f S16_LE/S24_LE -r 44100/48000 XXX.wav     aplay XXX.wav     to test this patch.

The solution works when I use mx53_loco bsp. Modify u-boot and kernel, keep the same. Then you may find you can't login into the system regardless of whatever you input after freescale login: It confused me for a long time. If you  also met this problem,try to check the iomux-mx53.h(linux/arch/arm/plat-mxc/include/mach/). #define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX   IOMUX_PAD(the fourth argument 0x878 should be changed to 0x0) I think this is a small bug in header files. Haifeng

In our default release , the eboot logo only can be show on WVGA panel. Attached patch file can let the eboot logo show both on DVI XGA and RGB WVGA panel.

i work with IMX6q,i find VDI is not work,And the video picture has Horizontal stripe. i want to know how should i make VDI work? FAE tell me enable g_vdi_enable in mxc_v4l2_tvin.c.but i do it already.The VDI don't  still work. please help me, many thanks

Downloading and building the V4L2 examples V4L2 examples - v0.1 are available at https://github.com/rogeriorps/v4l2-examples To download, just clone the project: $ git clone https://github.com/rogeriorps/v4l2-examples.git Available demos Example1: Display an image coming from camera using V4L2_BUF_TYPE_VIDEO_OVERLAY Example2: Display an image coming from camera using V4L2_BUF_TYPE_VIDEO_OUTPUT Known issues

In the default release the SSI1 doesn't suport double FIFO in audio driver. Attached was the code to support double FIFO with updated DMA script.

Sometimes we need to use an SPI bus to communicate with sensors or another device. Unfortunately, by default on iMX8MN-EVK, we have the ECSPI2 disabled on our BSP.   We can use that peripheral on Linux enabling it in the device tree.   To enable the ECSPI2 on the device tree we have to add the next on imx8mn-evk.dtsi:     status = "okay"; }; +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>;   On iomux node:   + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + pinctrl_ir_recv: ir-recv { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f    after modifying and compiling the device tree you can see the device active like this:     Connection:   Test: spidev_test -D /dev/spidev1.0 -v       You can use the devsheell of yocto to make the changes:   https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/How-to-use-Devshell-to-compile-device-tree-files/ta-p/1727428

If you cannot access the www.youtube.com, you may watch the citrix demo in Youku, the link as fellow: Citrix Receiver for Linux is a software client to access the desktops, applications, and data easily and securely from many types of Linux devices. About Installing Citrix Receiver,please go to Citrix website Receiver The i.MX 6DQ processor incorporates the hardware accelerators Video Processing Unit(VPU) and 3D/2D Graphics Processing Unit. By taking the advantage of i.MX 6DQ hardware accelerators, Freescale integrates H264 hardware decoder to Citrix Receiver for Linux on i.MX6DQ Ubuntu. With accelerated hardware decoding, the computing is offloaded and better performance is achieved. Configuration in the demo: Hardware i.MX6Q: i.MX 6Quad Processors: Quad Core, ARM® Cortex®-A9 Core 1920x1080 HDMI panel Software: Linux kernel 3.0.35 Ubuntu 12.04 hardfloat rootfs Citrix Receiver13.1 with Freescale H264 plug-in

FAE Title Date i.MX Device BSP Description Leo Demo uImage for iMX257 does not support EXT3 filesystem 2/May2013 257 L2.6.31_09.12.00_SDK_images_MX25 For some reason the demo uImage does not support EXT3 filesystems (ext2 is not good for SD cards). kernel has to be recompile with this feature. Xisco start-weston command doesn't work when running from SD card. Only from NFS 3/may/2013 6 RC3.0.35.4.0.0 When compiling rootfs with LTIB, there is a problem that /tmp is tmpfs but keeps the size as 512k, far from common program running requirement, and it's full when system boots up.   When executing start-weston script it needs to write to /tmp and it fails. Only happens with LTIB built BSP.   $ mount -t tmpfs /tmp /tmp        Should be run before executing start-weston Xisco Porting OpenGL ES2 cpp apps for i.MX6 7/may/2013 6 RC3.0.35.4.0.0 When porting OpenGL ES2 cpp apps that were written for i.MX53, you will find an error saying that the function :   fbGetDisplay()   needs more arguments.   All that is needed to fix this error is to change the function to:   fbGetDisplayByIndex(0)   And you will be able to compile your app. Leo Stand-alone MFG and Android MFG are not the same Wed May 15 12:15:17 CDT 2013 6 JB4.2.2_1.1.0 In case you want to flash Android, use the MFG inside the source code tarball and not the stand-alone (the one found directly on the SW & Tools tab). Seems that it takes some time for both to be sync (the same) Leo gst-ffmpeg plugins is broken Thu May 16 13:31:44 CDT 2013 6 RC3.0.35.4.0.0 Attached patch should be applied to gst-ffmpeg code Original Attachment has been moved to: 0001-gstffmpegdemux.c-Remove-deprecated-flow-macros.patch.zip