Step 1: Build r13.4.1         make         /* Store images file for MFGTool use */         make dist    /* Get ota_1.zip, and target_files_1.zip at out/dist, store them in a dedicated directory, for example .../release-1 */ Step 2: Modify any files in source code base; Step 3: make dist    /* Get ota_2.zip, and target_files_2.zip at out/dist, store them in a dedicated directory, for example .../release-2 */ Step 4: MFGTool flash release-1 images; Step 5: cp ota_2.zip to SD; Step 6: start board, then execute following commands under serial terminal;         cp /sdcard/ota_2.zip /cache/ota_2.zip         mkdir /cache/recovery         echo --update_package=/cache/ota_2.zip > /cache/recovery/command         sync         reboot recovery         Then you can see the upgrade successful. Step 7: MFGTool flash release-1 images; Step 8: ./build/tools/releasetools/ota_from_target_files -i .../release-1/target_files_1.zip .../release-2/target_files_2.zip ./diff_from_1_to_2.zip Step 9: cp diff_from_1_to_2.zip to SD; Step10: start board, then execute following commands under serial terminal;         cp /sdcard/diff_from_1_to_2.zip /cache/diff.zip         mkdir /cache/recovery         echo --update_package=/cache/diff.zip > /cache/recovery/command         sync         reboot recovery

Agenda: 1. How-to M4 boot-up from TCM, DDR, OCRAM or QSPI in i.MX7D SABRE board 2. About multicore communication, Linux / Cortex-A and FreeRTOS / Cortex-M    a. RPMsg Ping-Pong FreeRTOS demo    b. RPMsg String Echo FreeRTOS demo 3. Multi-core Resource Sharing and Protection, RDC (Resource Domain Controller), Master Assignment Registers, Peripheral Mapping and Memory region Map 4. RDC settings in FreeRTOS BSP

Introduction EMV stands for Europay, MasterCard and VISA, and is a global standard for inter-operation of integrated circuit cards (ICC) and ICC reader terminals (like point of sale (POS) terminals, automated teller machines (ATMs)) for authenticating credit and debit payment cards transactions. Any IC card reader must be certified to be EMV compliant. The EMV standard defines the interaction at the physical, electrical, data and application levels between the IC cards and IC card terminal. For the contact smartcards it is based on standard ISO/IEC 7816. Some of the i.MX embeds a Subscriber Identification Module (SIM) which was designed to facilitate the communication to a mobile phone SIM card. It could be used to communicate indirectly with a banking smartcard due to the listed limitations in regards to the EMV requirements. Electrical Limitations The POS terminal must support 1.8V, 3.3V, and 5V smartcards. Depending on the i.MX, 1.8V or 3.3V could be supported but not both, and 5V is definitely out of the range of the I/O supplies. => a level adapter component is required between the i.MX and the smartcard. Protocol Limitations The communication between the IC card and the reader is asynchronous (almost a UART), but based on a common clock for synchronous operation. The ISO7816 standard defines the following: 1 ETU = F / D * 1 / f ETU is Elementary Time Unit, which is somehow the nominal time to transmit a bit (0 or 1). F or Fi is the clock rate conversion integer. D or Di is the baud rate adjustment integer. f is the frequency of the communication clock used between the controller and the smartcard. Below is a partial list of what the controller must support to pass the EMV certification, and the known limitations of the SIM controller: - baud rate at x1 (Fi/Di=372/1) => default speed for all smart cards =>  supported. - baud rate at x2 (Fi/Di=372/2 = 186/1) => a higher speed for some smart cards => not supported. - baud rate at x4 (Fi/Di=372/4 93/1) => a higher speed for some smart cards => not supported. - message length of 12ETU => specified for T=0 type smart card => supported. - error of -0.2ETU on message length of 12ETU => 11.8ETU smart card => not supported. - message length of 11ETU => specified for T=1 type smart card => supported. - error of -0.2ETU on message length of 11ETU => 10.8ETU smart card => not supported. Conclusion For these reasons, the i.MX SIM controller does not allow to pass the EMV certification without the usage of an external controller that must care of all these missing features. The SIM can still be used to communicate with that external controller such Atmel AT83C26, NXP TDA8023, Terridian, or On Semi. Freescale does not have driver neither reference design to support that configuration. This company has the expertise to work with EMV certification for the i.MX258 + a companion smartcard controller: http://www.alcineo.com

Hello everyone, this post is intended to add support to one of the most popular NFC chips on the market (PN532).  On this example I will use the I.MX93 EVK as reference board and focused in I2C communication for the PN532 Chip.    Details:   I.MX93 EVK  PN532 Module (I2C, SPI, UART)  BSP Linux 6.6.36_2.1.0 (Yocto)      STEP 1 (IMAGE COMPILATION).    At first, we need to compile our image for our board (in my case I.MX93 EVK) to add the NFC layer (Details on Yocto User's Guide😞😞 $ mkdir yocto-bsp $cd yocto-bsp $ repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-scarthgap -m imx-6.6.36-2.1.0.xml $ repo sync $DISTRO=fsl-imx-wayland MACHINE=imx93evk source imx-setup-release.sh -b imx93evk-build   Then, add the support for NFC in our local.conf file:  $ nano conf/local.conf   We will add the below lines: CORE_IMAGE_EXTRA_INSTALL += "libnfc" CORE_IMAGE_EXTRA_INSTALL += "libnfc-dev"   Then, we can compile the image with:  $ bitbake imx-image-full   NOTE:  libnfc is a complete coverage of low-level PN53x chipset commands written in pure and plain C for portability and speed.  libnfc-dev are the development files and headers to use in our low-level applications.    By default, the NXP BSP support the NFC pn532 driver with a tool called nfctool, but this one is very limited compared with the libnfc.      STEP 2 (DEVICE TREE MODIFICATION).    We need to add the below lines to the Device tree:  &lpi2c5 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c5>; pinctrl-1 = <&pinctrl_lpi2c5>; status = "okay"; nfc@24 { compatible = "nxp,nxpnfc"; //we can set the "nxp,pn533" driver but it will just work for the nfctool mentioned before reg = <0x24>; clock-frequency = <400000>; interrupt-parent = <&gpio2>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; }; };    And to the iomux section(same in device tree):  pinctrl_lpi2c5: lpi2c5grp { fsl,pins = < MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e >; };     STEP 3 (Connection with PN532 MODULE).     For this example, we must connect the Module with the I.MX93 RP Header as follows:  PN532_imx93evk.jpeg   I.MX93 SIDE  PN532 SIDE  GND  GND  VCC  VCC  GPIO_IO22  SDA  GPIO_IO23  SCL  GPIO_IO18  IRQ    STEP 4 (BOOT BOARD AND CREATE libnfc.conf FILE).    Once when we have booted our board and selected our modified Device Tree, we should see our i2c-4 under /dev of our Linux OS: root@imx93evk:~# ls /dev | grep i2c i2c-0 i2c-1 i2c-2 i2c-4   And see our specific device (0x24) with the i2cdetect tool:   root@imx93evk:~# i2cdetect -y 4 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- 24 -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- --     Now, we need to create a file called libnfc.conf under /etc/nfc/ (You can create that directory if does not exist).  This file must contain information about how the libnfc layer will communicate with the i2c device:    # Allow device auto-detection (default: true) # Note: if this auto-detection is disabled, user has to set manually a device # configuration using file or environment variable allow_autoscan = false # Allow intrusive auto-detection (default: false) # Warning: intrusive auto-detection can seriously disturb other devices # This option is not recommended, user should prefer to add manually his device. allow_intrusive_scan = true # Set log level (default: error) # Valid log levels are (in order of verbosity): 0 (none), 1 (error), 2 (info), 3 (debug) # Note: if you compiled with --enable-debug option, the default log level is "debug" log_level = 2 # Manually set default device (no default) # To set a default device, you must set both name and connstring for your device # Note: if autoscan is enabled, default device will be the first device available in device list. #device.name = "_PN532_SPI" #device.connstring = "pn532_spi:/dev/spidev0.0:500000" device.name = "_PN532_I2c" device.connstring = "pn532_i2c:/dev/i2c-4"   As you can see, the most important line to modify is the device.connstring, that is the charged of interaction and connection between the PN53x Module and the libnfc layer. In my case is pn532_i2c:/dev/i2c-4.    Now we can use the NFC module:  root@imx93evk:~# nfc-list nfc-list uses libnfc 1.8.0 NFC device: _PN532_I2c opened root@imx93evk:~#   And read UID of TAGs:  root@imx93evk:~# nfc-poll nfc-poll uses libnfc 1.8.0 NFC reader: _PN532_I2c opened NFC device will poll during 36000 ms (20 pollings of 300 ms for 6 modulations) ISO/IEC 14443A (106 kbps) target: ATQA (SENS_RES): 00 44 UID (NFCID1): 04 17 b5 d2 a2 11 90 SAK (SEL_RES): 00 Waiting for card removing...nfc_initiator_target_is_present: Target Released done. root@imx93evk:~#   Also, attached is a little application using the NFC headers installed with libnfc-dev. Tha application will do a poll with a 10 seconds time out. If Tag is not detected in 10 seconds, the app will close. If a tag is detected before the timeout, the app will print the UID of the NFC TAG:   OUTPUT of timeout: root@imx93evk:~# ./nfc-app NFC reader: _PN532_I2c opened Waiting for an NFC tag (timeout: 10 seconds)... No NFC tag detected within the timeout period. root@imx93evk:~#   OUTPUT when tag is detected: root@imx93evk:~# ./nfc-app NFC reader: _PN532_I2c opened Waiting for an NFC tag (timeout: 10 seconds)... Tag detected - UID: 04:16:BC:D2:A2:11:90 root@imx93evk:~#   To compile the app just copy the attached nfc-app.c file to the i.MX93 EVK and compile using this command: root@imx93evk:~# gcc nfc-app.c -o nfc-app -lnfc     I hope this thread can be helpful!   Best regards, Salas.  

Installing the new release (Ubuntu 22.04) was detected some NXP boards as iMX8MNEVK, iMX8MM-EVK, iMX8MP-EVK and iMX8ULP-EVK had an issue with the WIFI module that basically it does not initialize at boot. Remember, the supported WIFI modules in Ubuntu 22.04 in the EVKs are the following:       • NXP 88W8987       • NXP 88W9098       • NXP 88W8997       • NXP IW416       • NXP 88W8801       • NXP IW612 To initialize the WIFI module of NXP EVKs in Ubuntu 22.04 you can set the following command in console:   sudo modprobe moal mod_para=nxp/wifi_mod_para.conf   That command find the correct driver for our WIFI module and then initialize it, but this only works when Ubuntu is working and if you reset the EVK you need to set the command again.   The definitive solution is create a custom startup script as a service:   Step 1: Go to etc/systemd/system   cd etc/systemd/system   Step 2: In this directory create a new file with the name of your preference but the extension must be .service. You can do it with nano or vim: sudo nano or sudo vim   The file must contain: [Unit] Description=”Wifi Start” [Service] ExecStart=sudo modprobe moal mod_para=nxp/wifi_mod_para.conf [Install] WantedBy=multi-user.target   Now save the file, in my case the name was wifi_start.service.   Step 3: Now we need to enable the script in the startup/boot sequence following the command: sudo systemctl enable wifi_start.service   Remember in wifi_start.service is the name as you saved your file.   Finally, each time you boot your board, the WIFI module will initialize automatically.   Boards tested: iMX8MN (With WIFI module NXP 88W8987) iMX8MM (With WIFI module NXP 88W8987) iMX8MP (With WIFI module NXP 88W8997) iMX8ULP (With WIFI module NXP IW416)  

i.MX8DXL DDR3L EVK board, nor flash using is MT25QU512ABB8ESF-0SIT. This doc will show reference of FlexSPI configuration parameters to make booting from MT25Q flash, with QUAD pad and DDR mode. HW: i.MX8DXL DDR3L EVK board SW: Linux 5.4.70 BSP From RM 5.9.3.2 FlexSPI serial flash BOOT operation, the FlexSPI boot flow as : fushi_peng_0-1623055384030.png   FlexSPI configuration parameters,  could be think as two kind group: parameter for FlexSPI controller,  parameter related to the operation on nor flash.   Full parameter table check check i.MX8DXL RM Table 5-20. FlexSPI Configuration block. Let us check MT25Q data sheet for its feature, note our target is DDR mode(80MHZ) and QUAD pad:   fushi_peng_1-1623055541300.png   Now let us change the FlexSPI configuration parameters: 1>readSampleClkSrc , set as 2 , that is loop back from SCK pad; this filed default set as 0, as found default value booting will met failure in this use case, so change to 2. 2>deviceModeCfgEnable set 1, deviceModeSeq.seqNum set 1 , deviceModeSeq. seqId set to 4; deviceModeArg set 0x5f. i.MX8DXL will send some cmd to flash to make MT25Q enter DDR mode and QUAD mode, so deviceModeCfgEnable =1. For seqNum=1, seqId =4; means index 4 of LUT table will store this sequence, and cost one LUT entry. We will explain how to change LUT entry later. For deviceModeArg=0x5f, check MT25Q data sheet, its enhanced volatile register could be write to configure the flash working mode: fushi_peng_2-1623055599319.png  3>controllerMiscOption as 0x40, this parameter only for FlexSPI controller itself, means as” External device works using DDR commands”. 4>deviceType=1(Serial Nor),  sflashPadType=4 (QUAD pad),  serialClkFreq=4(80MHZ CLK), these parameter also only for FlexSPI controller. 5>sflashA1Size fill actual size, in terms of bytes 6>LUT entry changes, check 8DXL RM Table 5-21: fushi_peng_3-1623055642496.png So LUT entry 0 is sequence for Read command, entry 1 is for Read Status sequence, entry 3 is for Write Enable sequence,  entry 15 is for Dummy command sequence. Other index LUT entry(for example 2,4,6,7,8,10,12,13,14) is could be used for store your sequence for some cmd your flash device neede. We store sequence of writing MT25Q enhance volatile register as LUT entry 4. Check 8DXL RM,  Figure 15-6. LUT and sequence structure:   fushi_peng_4-1623055681631.png Each LUT entry (sequence) will using 16 byte,  one sequence consists of up to 8 instructions, each instruction will using 16bit. Each instruction  format as opcode—num_pads—operand. Check RM 15.2.4.8 Programmable Sequence Engine, for supported instructions: fushi_peng_5-1623055714204.png fushi_peng_6-1623055725961.png   Actually the Write enable sequence is run first before the other sequence, as we will write Mt25Q volatile register, before that need issue Write enable sequence. Check MT25Q data sheet: fushi_peng_7-1623055771117.png fushi_peng_8-1623055777691.png For this sequence only need one instruction, that is 0x0406, at this time still using is SDR and one pad mode:  Opcode (CMD_SDR),  one pad (0), operand (6).   LUT entry 1, Read status sequence, it is READ STATUS REGISTER (05h) of MT25Q , check data sheet: fushi_peng_9-1623055815109.png It use two instructions: 0x0405: opcode(CMD_SDR), pad (one pad), operand (0x5, READ STATUS REGISTER) 0x2404: opcode(READ_SDR), pad (one pad), operand (0x4 , byte number)   LUT entry 4, that is for make MT25Q enter DDR mode and quad pad: From MT25Q data sheet: fushi_peng_10-1623055838270.png It will use two instructions, that is 0x0461: opcode (CMD_SDR),  one pad (0), operand (0x61 WRITE ENHANCED VOLATILE CONFIGURATION REGISTER) 0x2001: opcode (WRITE_SDR 08), one pad(0), operand (1 byte data size) The 0x5f will be send out as data.   Next check LUT entry read , at this time MT25Q had enter QUAD pad and DDR mode: LUT entry 0, Read sequence, it is fast read data from MT25Q, from data sheet: fushi_peng_11-1623055868279.png fushi_peng_12-1623055877661.png will use four instructions , that is : 86ED, opcode (CMD_DDR ), pad ( four pad), operand (0xEDh fast read) 8a18, opcode (RADDR_DDR), pad (four pad), operand (0x18 , three byte address) B210, opcode(DUMMY_ADDR), pad (four pad), operand(0x10, dummy cycle) A604, opcode (READ_DDR), pad (four pad) , operand (0x4, data byte)   Reference: 1.i.MX8DXL Reference Manual 2.MT25Q data sheet              

  Question: How can we generate an ARM DS5 DStream format DDR initialization script using the DRAM Register Programming Aid?  Answer: Some RPAs include a  "DStream .ds file" tab for the ARM DS5 debugger specific commands. The i.MX6UL/ULL/ULZ DRAM Register Programming Aids for example already has this supported. However, the user can easily create  the .ds format from the existing .inc format. The basic steps to convert .inc files to .ds format are as follows: 1)  Replace the one instance of setmem /16 with mem set 2)  In that same line, replace 0x020bc000 = with 0x020bc000 16 3)  Use a Replace All command to change setmem /32 with mem set 4)  Use a Replace All command to change = with 32 5)  Use a Replace All command to change // with # 6)  Save as a .ds file.   Question: When using a 528MHz DRAM Controller interface with a DDR memory of a faster speed bin, which speed bin timing options should one use? Answer: For example, let’s assume our MX6DQ design is using a DDR3 memory from a DDR3-1600 speed bin.  However, the maximum speed of the MMDC interface for the MX6DQ using DDR3 is 528MHz.  Should we use the 1600 speed bin (800MHz clock speed) or the 1066 speed bin (533MHz clock speed)?  In short, the user should use the timings rated for the maximum speed (frequency) with which you are running, in this case DDR3-1066 (533MHz).  In some cases, like when using the MX6DL, the maximum DDR frequency is 400MHz.  In this case, you would want to try and use 800 timings found in the AC timing parameters table.  However, most DDR3 devices have speed bin tables that may go only as low as 1066, in which case you would use the closest speed bin to your operational frequency (i.e. the 1066 speed bin table).     Question: Some timing parameters may specify a min and max number, which should I use? Answer: In most cases, you will want to choose the minimum timings.  Some DRAM controllers may have a tRAS_MAX timing parameter, in which case you would obviously use the maximum tRAS parameter given in the DRAM data sheet. Also, for timing parameters tAONPD and tAOFPD, we also want to use the maximum values given in the DDR3 data sheet. These represent the maximum amount of time the DDR3 device takes to turn on or off the RTT (termination), therefore, we should wait at least this amount of time before issuing any commands or accesses.   Question: Some timing parameters state things like “Greater of 3CK or 7.5ns”; which should I use? Answer: This depends on your clock speed.  Say you are running at 533MHz.  At 533MHz, 7.5ns equates to 4CKs.  In this case, 7.5ns at 533MHz is GREATER than 3CK, so we would use the 7.5ns number, or 4CKs. At 400MHz, 7.5ns equates to 3CKs.  In this case, we’d simply use 3CKs.   Question: I have a design that will throttle the DDR frequency (dynamic frequency scaling).  At full speed, I plan to run at 533MHz, and then I plan to throttle down to say 400MHz whenever possible.  Do I need to re-calculate my 400 MHz timing parameters that were initially set for 533MHz? Answer: It is not necessary to re-calculate timing parameters for 400MHz, and you can re-use the ones for 533MHz.  The timings at 533 MHz are much tighter than 400 MHz, and the key here is to NOT violate timings.  Also, it may be a bit of a hassle maintaining two sets of timing parameters, especially if later in the design, you swap DDR vendors that might require you to re-calculate some timing parameters.  It’s easier to do it once and to come up with a combined worse-case timing parameters for 533MHz, which you know will work at 400MHz.  But, if you don’t mind maintaining two sets of timing parameters, and really want to optimize timings down to the last pico-second for 400MHz, then knock yourself out.   Question: Can I use these Register programming aids for both Fly by and T- Topology ? Answer Yes The DDR register programming aid is agnostic to the DDR layout. The same spreadsheet works for both topologies. We recommend running write leveling calibration for both topologies and the values returned by the Write Leveling routine from the Freescale DDR stress test should be incorporated back to the customer specific initialization script. The DDR stress test also has a feature whereby it evaluates the write leveling values returned from calibration and increments WALAT to 1 if the values exceed a defined limit. The DDR stress test informs the user when the Write Additional latency (WALAT) exceeds the limit and should be increased by 1, and reminds the user to add it back in the customer specific initialization script if required.   WALAT - 0 00000000 WALAT: Write Additional latency. Recommend to clear these bits. Proper board design should ensure that the DDR3 devices are placed close enough to the MMDC to ensure the skew between CLK and DQS is less than 1 cycle.     Question: Can I use the DEFAULT Register programming aid values for MDOR when using an Internal OSC instead of the recommended 32.768 KHZ XTAL ? Answer No, NXP recommends reprogramming these values based on the worse case frequency (Max clock) of the internal OSC of the device to guarantee JEDEC timings are met. Please refer to Internal Oscillator Accuracy considerations for the i.MX 6 Series for more details  

The following are a couple of recommendations for setting up a Host machine for building the Android Nougat 7.1.1_1.0.0 BSP. Some of these recommendations are not exclusive of the Nougat release and may help in other scenarios. These also apply to using Virtual Machines as Host. Installing Open JDK 8 on Ubuntu 14.04 As mentioned on the Android guide for Establishing a Build Environment (http://source.android.com/source/initializing.html) there are no available supported OpenJDK 8 packages for Ubuntu 14.04, which is the version recommended and tested on the Nougat Android BSP. An alternative is downloading the Ubuntu 15.04 Open JDK 8 packages and installing them manually, which can be done by following this procedure: Download the .deb packages for 64-bit architecture from archive.ubuntu.com: openjdk-8-jre-headless_8u45-b14-1_amd64.deb with SHA256 0f5aba8db39088283b51e00054813063173a4d8809f70033976f83e214ab56c0 http://archive.ubuntu.com/ubuntu/pool/universe/o/openjdk-8/openjdk-8-jre-headless_8u45-b14-1_amd64.deb  openjdk-8-jre_8u45-b14-1_amd64.deb with SHA256 9ef76c4562d39432b69baf6c18f199707c5c56a5b4566847df908b7d74e15849 http://archive.ubuntu.com/ubuntu/pool/universe/o/openjdk-8/openjdk-8-jre_8u45-b14-1_amd64.deb  openjdk-8-jdk_8u45-b14-1_amd64.deb with SHA256 6e47215cf6205aa829e6a0a64985075bd29d1f428a4006a80c9db371c2fc3c4c http://archive.ubuntu.com/ubuntu/pool/universe/o/openjdk-8/openjdk-8-jdk_8u45-b14-1_amd64.deb  Once you have downloaded these three packages and checked the checksum for them install the packages (optional) install them by running: $ sudo apt-get update $ sudo dpkg -i openjdk-8-jre-headless_8u45-b14-1_amd64.deb $ sudo dpkg -i openjdk-8-jre_8u45-b14-1_amd64.deb $ sudo dpkg -i openjdk-8-jdk_8u45-b14-1_amd64.deb‍‍‍‍   Increasing SWAP to compensate for the lack of RAM Having insufficient RAM especially on the linking part of the image build may cause a number of issues that are difficult to troubleshoot. In these cases it’s good to take a look at the resource monitor to see if indeed the RAM was depleted. One way to make up for the limited RAM is using a bigger swap. Google recommends at least 16GB of RAM/swap so it’s not uncommon to create a 10GB swap when working in VM, to do this please use the following commands.    $ sudo fallocate -l 10g /mnt/10GB.swap $ sudo chmod 600 /mnt/10GB.swap $ sudo mkswap /mnt/10GB.swap $ sudo swapon /mnt/10GB.swap‍‍‍‍   Increasing heap size to avoid out of memory errors It is possible to encounter an out of memory error with the recommendation “try increasing heap size witj java option ‘-Xmx<size>’. If you encounter this error or would like to proactively avoid it you may run the following commands that will increase heap size to four gigabytes and then reset the Jack Server by killing it and starting it again. With the android environment initialized: $ cd my android $ export JACK_SERVER_VM_ARGUMENTS="-Dfile.encoding=UTF-8 -XX:+TieredCompilation -Xmx4g" $ jack-admin kill-server && jack-admin start-server‍‍‍‍‍‍  Fixing Jack Servers errors due to multiple users on the Host Android Nougat uses Jack Server as mono-user by default. If this is not the case for your host you would need to choose different port numbers for each user and adjust SERVER_NB_COMPILE accordingly. You can also disable the Jack server by setting SERVER=false in your $HOME/.jack. Alternatively, you may also use the patch available on the following link to myandroid/prebuilts/sdk. It will help to fix the mono-user build restriction. When installing the jack-server, it will detect if Jack server is running in the same build machine and then generate a random ports for my build instead of using the default one. https://groups.google.com/forum/#!topic/android-building/UWhJrXH8Vig

i.MX8/8X/8XL在汽车中的应用 • 娱乐导航 • 虚拟仪表 • 电子座舱 • 360环视与ADAS • C-V2X Tbox

Question: Is SN65LVDS315 (MIPI CSI-1) compatible with our i.MX6 MIPI CSI-2 interface? CSI-2 extends CSI-1 with multiple lanes, but both standards use the same D-PHY layer. Answer: No, the i.MX6 MIPI CSI-2 interface is not compatible with CSI-1 devices. Standards that require backward compatibility to legacy standards always state that the standards are backward compatible. The CSI-2 standard does not say that. (I have a copy of the standard and I have read it specfically for that reason)  The CSI-2 standard does say that a specifically designed PHY, built to D-PHY MIPI01 specification is used for CSI-2. The PHY's used for CSI-1 and CSI-2 are different and they are not compatible. There are some processors that do have compatiblity for CSI-1 and CSI-2, but if you read closer, you will find that they have two different modes (and probably two different sets of pins): One for CSI-2 and One for CSI-2/CSI-1 legacy. It is interesting that a company would choose to inlcude a dying technology in a newer processor, but my guess is that they have a number of other CSI-1 devices they are trying to sell before they can't be used anywhere and nobody wants them. if the customer is looking for a parallel camera interface to CSI-2 converter IC, may I recommend the Toshiba TC358746 device. I have not used it specifically, but I have worked with a Toshiba rep on an HDMI to MIPI CSI-2 project that input into the i.MX6 processor. Once all the correct parameters were determined, it worked very well. Much higher data rate flow.

Basic Linear Algebra Subprograms (BLAS) is a specification that prescribes a set of low-level routines for performing common linear algebra operations such as vector addition, scalar multiplication, dot products, linear combinations, and matrix multiplication. OpenBLAS is an optimized BLAS library which is uesd for deep learning accelerator in Caffe/Caffe2. I enable it in Yocto (Rocko) by adding bb file. And I build on i.MX6QP, i.MX7ULP and i.MX8MQ and also run its test example successfully. You can find test example(openblas_utest) under folder image/opt/openblas/bin of OpenBLAS work directory. Currently, version 0.3.0 is supported in the bb file. +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ update to v 0.3.6 and enable mutli-thread by set USE_OPENMP=1 and USE_THREAD=4 when compiling this library.

The purpose of this document is to specify the maximum LPDDR3, LPDDR4, & LPDDR4X densities that are supported by i.MX 8ULP processor along with a running list of tested memories to aid project feasibility assessment capabilities of customers that are evaluating the SoCs for usage in their products.  It is strongly recommended to consult with NXP and the memory vendor the final choice of the memory part number to ensure that the device meets all the compatibility, availability, longevity and pricing requirements. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs. For any questions related to specific DRAM part numbers please contact the respective DRAM vendor. For any questions regarding the i.MX SoC please contact your support representative or enter a support ticket.  LPDDR4/LPDDR4X Maximum Support Density Please note that the SoC limits the addressable DDR memory map range to 2GB. SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8ULP 32-bit 16Gb/2GB single-rank, dual-channel  device with 16-row addresses (R0-R15) 1, 2, 6,11   LPDDR4 - list of validated memories The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Memory Vendor Validated Memory Part#  Notes i.MX 8ULP 16Gb/2GB Micron MT53D512M32D2DS-053 WT:D  10 16Gb/2GB Micron MT53E512M32D1ZW-046 WT:B  8 64Gb/8GB Micron MT53E2G32D4DE-046 WT:A  3, 4, 8 32Gb/4GB Micron MT53E1G32D2FW-046 AUT:B  3, 4, 10 16Gb/2GB Nanya NT6AN512T32AV-J2 3, 7, 8 8Gb/1GB Forsee FL4C2001G-D9  3, 10   LPDDR4x - list of validated memories The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Mamory Vendor Validated Memory Part# Notes i.MX 8ULP 16Gb/ 2GB Nanya NT6AP512T32AV-J2  3, 7, 8 2Gb/ 256MB Fidelix FMF2D32VAC-4CDIR 3 4Gb/ 512MB Winbond W66CQ2NQUAFJ  3, 8 8Gb/1GB Alliance Memory AS4C256M32MD4V-062BAN  3, 8 32Gb/4GB Micron MT53E1G32D2FW-046 AUT:B (Z42M) 3, 4, 10 16Gb/ 2GB Micron MT53D512M32D2DS-053 WT:D  10 16Gb/ 2GB Micron MT53E512M32D1ZW-046 WT:B  9   LPDDR3 Maximum Support Density Please note that the SoC limits the addressable DDR memory map range to 2GB. SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8ULP 32-bit 16Gb/2GB Single Channel, Dual Chip Select 5,11   LPDDR3 - list of validated memories The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Memory Vendor Validated Memory Part#  Notes i.MX 8ULP 16Gb/2GB Micron  MT52L512M32D2PF-107 WT:B  8   Note 1: The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC and on the memory device used on NXP evaluation boards, and on the JEDEC standards JESD209-4/JESD209-4B (LPDDR4/4X). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 2: Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification). Note 3: The memory part number did not undergo full JEDEC verification however, it passed all functional testing items. Note 4: As the i.MX 8ULP DDR memory map is limited to 2GB, only up to 2GB of the device can be utilized even though the device density exceeds the 2GB range. Note 5: The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC and on the memory device used on NXP evaluation boards, and on the JEDEC standards JESD209-3C (LPDDR3). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.  Note 6: The SoC supports also LPDDR4/4X devices with 17-row address bits however, given the SoC's memory map constraints (see Note 4), full density of those devices cannot be utilized since the dual channel (x32) 17-row address memory devices have the density of 4GB and higher. Note 7: By default, LPDDR4/4X devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity. Please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured. Note 8: Part is active. Reviewed Jan 2026 Note 9: Part is active as MT53E512M32D1ZW-046BWT:B.  Note 10: Part is obsolete. Note 11: i.MX 8ULP does not support Non-Power of 2 Memory densities (e.g. 3,6,12 Gb).

JTAG Hardware and Software There are many opened and proprietary JTAG solutions. Here are some of them: Proprietary IAR Systems In-Circuit Debugging Probes Macraigor usb2Demon Segger - Jlink Free and Open Source Software GDB OpenOCD Open Hardware Turtelizer

How to use UART4 on iMX8M from Linux User Space   The UART4 on iMX8MM-EVK and iMX8MN-EVK are thinking of debugging the M core which is not usable on Linux user space by default on pre-compiled images.   To use the UART4 on Linux user space you have to do the next modifications on the device tree and atf to assign that peripheral to Linux User Space     https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c     iMX8MN-EVK   imx8mn_bl31_setup.c   https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c   /* Master domain assignment */ RDC_MDAn(RDC_MDA_M7, DID1), /* peripherals domain permission */ - RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), + RDC_PDAPn(RDC_PDAP_UART4, D0R | D0W), RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R),       Device tree configurations for iMX8MN-EVK   iMX8MN-EVK.dtsi   https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi   &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MN_CLK_UART3>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; }; + &uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MN_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + status = "okay"; + }; ********************** pinctrl_uart3: uart3grp { fsl,pins = < MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + };   iMX8MM-EVK   https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c   imx8mm_bl31_setup.c   /* Master domain assignment */ RDC_MDAn(RDC_MDA_M7, DID1), /* peripherals domain permission */ - RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), + RDC_PDAPn(RDC_PDAP_UART4, D0R | D0W), RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R),   Device tree configurations for iMX8MM-EVK   iMX8MM-EVK.dtsi   https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi   &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MM_CLK_UART3>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; }; + &uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; + }; ********************** pinctrl_uart3: uart3grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + };   iMX8MP-EVK   https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c   imx8mp_bl31_setup.c   RDC_MDAn(RDC_MDA_M7, DID1), RDC_MDAn(RDC_MDA_LCDIF, DID2), RDC_MDAn(RDC_MDA_LCDIF2, DID2), RDC_MDAn(RDC_MDA_HDMI_TX, DID2), /* peripherals domain permission */ + RDC_PDAPn(RDC_PDAP_UART4, D0R | D0W), RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), RDC_PDAPn(RDC_PDAP_WDOG1, D0R | D0W), RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R),   Device tree configurations for iMX8MP-EVK   iMX8MP-EVK.dts   https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mp-evk.dts   &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MP_CLK_UART3>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; fsl,uart-has-rtscts; status = "okay"; }; + &uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; + }; ************************************ pinctrl_uart3: uart3grp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + };     After compiling the image with the changes previously shown, we obtained this result:   Chavira_0-1700668282092.png    

This doc will show: i.MX6SLL EVK board without connect hardware LCD display, using FreeRDP to share screen to remote PC which in same network, PC take this shared screen could run any command on i.MX6SLL EVK board. HW: i.MX6SLL EVK board, PC, usb network adapter SW: i.MX6SLL Linux 5.15.72_2.2.0 BSP release, and code change in this doc 1>yocto-5.15.72/6sll-bld/conf/local.conf, add below line, as freerdp depend on ffmpeg. LICENSE_FLAGS_ACCEPTED+="commercial" 2>pixman need switch to 0.42.0, enter folder yocto-5.15.72/6sll-bld/tmp/work/cortexa9t2hf-neon-poky-linux-gnueabi/pixman/1_0.40.0-r0/pixman-0.40.0, fetch latest 0.42.0 version code from https://github.com/freedesktop/pixman.git 3>freerdp need use 2.8.0, enter folder yocto-5.15.72/6sll-bld/tmp/work/cortexa9t2hf-neon-poky-linux-gnueabi/freerdp/1_2.6.1-r0/git should checkout to 2.8.0 tag; then to use neon accelerate freerdp related function, such as color space conversion, image codec encoding, apply patch freerdp-codechange-neon.diff. 4>Enter yocto-5.15.72/sources/meta-openembedded/meta-oe/recipes-support/freerdp, file freerdp_2.6.1.bb change as freerdp-2.6.1-bbfile.diff 5> bitbake -c compile ffmpeg bitbake -c install ffmpeg bitbake -c compile pixman bitbake -c install pixman bitbake -c compile freerdp bitbake -c install freerdp 6> Copy generated new libs to i.MX6SLL Linux rootfs: cp /root/imx6sllevk-linux-lib/lib* /usr/lib/ cd /usr/lib/ rm libfreerdp-client2.so.2 libfreerdp2.so.2 libpixman-1.so.0 libwinpr-tools2.so.2 libwinpr2.so.2 ln -s libfreerdp-client2.so.2.8.0 libfreerdp-client2.so.2 ln -s libfreerdp2.so.2.8.0 libfreerdp2.so.2 ln -s libpixman-1.so.0.42.0 libpixman-1.so.0 ln -s libwinpr-tools2.so.2.8.0 libwinpr-tools2.so.2 ln -s libwinpr2.so.2.8.0 libwinpr2.so.2 ln -s libavcodec.so.58.134.100 libavcodec.so.58 ln -s libavutil.so.56.70.100 libavutil.so.56 ln -s libswresample.so.3.9.100 libswresample.so.3 Make sure: libfreerdp-client2.so.2 -> libfreerdp-client2.so.2.8.0 libfreerdp2.so.2 -> libfreerdp2.so.2.8.0 libwinpr-tools2.so.2 -> libwinpr-tools2.so.2.8.0 libwinpr2.so.2 -> libwinpr2.so.2.8.0 libswresample.so.3 -> libswresample.so.3.9.100 libavutil.so.56 -> libavutil.so.56.70.100 libavcodec.so.58 -> libavcodec.so.58.134.100 7>i.MX6SLL Linux OS, file /etc/xdg/weston/weston.ini, change start-on-startup to true [screen-share] command=WLOG_APPENDER=file WLOG_FILEAPPENDER_OUTPUT_FILE_NAME=output.log WLOG_FILEAPPENDER_OUTPUT_FILE_PATH=/tmp /usr/bin/weston --backend=rdp-backend.so --shell=fullscreen-shell.so --no-clients-resize --rdp-tls-cert=/etc/freerdp/keys/server.crt --rdp-tls-key=/etc/freerdp/keys/server.key start-on-startup=true 8> i.MX6SLL Linux OS, run below cmd: mkdir /etc/freerdp mkdir /etc/freerdp/keys /root/imx6sllevk-linux-lib/winpr-makecert -path /etc/freerdp/keys mv /etc/freerdp/keys/imx6sllevk.crt /etc/freerdp/keys/server.crt mv /etc/freerdp/keys/imx6sllevk.key /etc/freerdp/keys/server.key service weston stop service weston start 9>Plug usb network adapter to i.MX6SLL EVK board J10; i.MX6SLL board and PC must in same network, ping without problem. i.MX6SLL Linux OS, there are two process name as "weston", one process is weston rdp backend will share screen to PC. If only one weston process, need check did miss copy any new lib or check libary file name. 10>PC side: wfreerdp.exe /v:IPADDRESS_OF_IMX6SLLEVK There will prompt dialog box for user name and password, just press ESC, then PC side will show i.MX6SLL Linux desktop screen; Click console button of i.MX6SLL Linux OS desktop, within that console input any i.MX6SLL Linux OS cmd, check result of it from PC side. Known issue: wfreerdp.exe is downloaded from https://ci.freerdp.com/job/freerdp-nightly-windows/ If run latest wfreerdp.exe but show nothing of remote desktop, try attached version wfreerdp.exe(3.0.0-dev). Also you can try check log files first: i.MX6SLL Linux OS file /tmp/output.log; PC side generated log file as: wfreerdp.exe /v:IPADDRESS_OF_IMX6SLLEVK /log-level:TRACE > rdp.log Reference: 1>https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applicat... 2>https://github.com/FreeRDP 3>https://github.com/freedesktop/pixman 4>https://github.com/DLTcollab/sse2neon    

You can but building times will take much longer (approximately 2 times longer for the core-image-minimal) compared to a build done on a native machine. In case you can not do the build on a native machine, make sure your virtual has enough hard-disk room (at least 50GB). For example, these are the build folders sizes after baking core-image-minimal: build$ du -h --max-depth=1 1.3G    ./sstate-cache 3.2M    ./cache 12K    ./.hob 32K    ./conf 22G    ./tmp 23G    . The tmp folder is by far the largest (containing building statistics, source code, deployed images, etc.) build/tmp$ tree -L 2 -d . ├── buildstats │   ├── cogl-imx6qsabresd │   ├── fsl-image-gui-imx6qsabresd │   ├── fsl-image-gui-sdk-imx6qsabresd │   ├── mesa-dri-imx6qsabresd │   ├── mesa-imx6qsabresd │   └── pseudo-native-imx6qsabresd ├── cache │   └── default-eglibc ├── deploy │   ├── images │   ├── licenses │   └── rpm ├── log │   ├── cleanlogs │   └── cooker ├── pkgdata │   ├── all-poky-linux │   ├── all-poky-linux-gnueabi │   ├── armv7a-vfp-neon-poky-linux-gnueabi │   ├── imx6qsabresd-poky-linux │   └── imx6qsabresd-poky-linux-gnueabi ├── sstate-control ├── stamps │   ├── all-poky-linux │   ├── all-poky-linux-gnueabi │   ├── armv7a-vfp-neon-poky-linux-gnueabi │   ├── imx6qsabresd-poky-linux │   ├── imx6qsabresd-poky-linux-gnueabi │   ├── work-shared │   └── x86_64-linux ├── sysroots │   ├── imx6qsabresd │   ├── imx6qsabresd-tcbootstrap │   └── x86_64-linux ├── work │   ├── all-poky-linux │   ├── all-poky-linux-gnueabi │   ├── armv7a-vfp-neon-poky-linux-gnueabi │   ├── imx6qsabresd-poky-linux │   ├── imx6qsabresd-poky-linux-gnueabi │   └── x86_64-linux └── work-shared     └── gcc-4.7.2-r13

This is ov5645 driver and tested with i.MX6 L3.0.35 BSP .  It is modified based on ov5640.c. P.S. The power down function for OV5645 is different from the OV5640. So modify the function in your_board.c like this: static void mx6q_mipi_powerdown(int powerdown) {     if (!powerdown)         gpio_set_value(MIPI_PWDN, 1);     else         gpio_set_value(MIPI_PWDN, 0);     msleep(5); }

Introduction The SABRE Board for Smart Devices Based on the i.MX 6 Series is an evalutaion board featuring the i.MX6 Quad Core Cortex-A9 processor. Freescale ported the Linux Operating System (as of this writing version 3.0.35) and the Board Support Package (BSP) containing the Linux Kernel, build system called LTIB, GCC compiler tools, boot loader, u-boot, and root file system is available for download, install, and build. LTIB is a perl script and is the acroynm for Linux Target Image Builder. This document describes setting up a CentOS 6.3 64-bit host in a virtual machine for using the BSP and running the images on i.MX6Q-SDB evaluation board. References Description Reference CentOS 6.3 LiveCD installed in a virtual machine from virtual box. http://centos.org CentOS-6.3-x86_64-LiveCD.iso 9953ff1cc2ef31da89a0e1f993ee6335 Virtual Box - A Virtual Machine used for creating the CentOS host. Virtual Box installed on Windows 7 64-bit Pro, then create the VM. Allocated 20 GB Hard disk and 1 MB RAM. The steps for installations are found at the virtual box web site. http://www.virtualbox.org The BSP provides, a build system called ltib, GNU tools, U-Boot, Linux Kernel, and root file system: Download archive from http://freescale.com/sabresdb L3.0.35_12.09.01.0_GA_source.tar.gz 5ab4198278e92e03be74ca602227afad Document Conventions Bold lines are Linux commands and edits run on CentOS. The '$' indicates running the command as a regular user The '#' indicates running the command as root user. CentOS Host Setup For this example a virtual machine is used, however a dedicated PC running only CentOS linux could be used. 1. Add user login to sudo'ers file           Login as user root and run the visudo command          # visudo           Add the following line and save the file:           user     ALL=(ALL)     ALL 2. Update the system packages:           $ sudo yum udpate 3. Install package for "ltib" operations:           $ sudo yum install make gcc gcc-c++ kernel-devel bison libuuid-devel ncurses-devel zlib-devel lzo-devel intltool libtool tcl rpm-build perl-ExtUtils-MakeMaker ld-linux.so.2 zlib-1.2.3-27.el6.i686 4. Update sudo'ers file for supporting ltib rpm           $ sudo visudo           Add the following line and save the file:           user     ALL=NOPASSWD: /bin/rpm,/opt/freescale/ltib/usr/bin/rpm Install BSP The sources are in a tar gziped archive file which is downloaded from http://freescale.com/sabresdb, selecting the Software & Tools tab then expanding Run-time Software in the middle of the page. A free login is required for download which can be registered for by selecting the Login at the top right of the freescale.com page. Once downloaded, verify the md5 checksum (see references above for the value). $ mkdir ~/imx6 $ tar -zxf L3.0.35_12.09.01.01_GA_source.tar.gz -C ~/imx6 $ cd ~/imx6/*source $ ./install Read and accept the licensing information. Choose a directory to install too, for this example entered .. which is the parent directory. Build the i.MX6Q SDB $ cd ~/imx6/ltib $ ./ltib After some time (depends on how fast your host computer is) the menuing system is shown which allows you to select build configurations. The second screen selects the development platform which is imx6q for the SDB. For this example the Min profile is chosen which is the default. Use the arrow keys to move and the enter key to select. The space bar selects/deselects an entry. Use the right arrow key to move to <Exit> and press the enter key. The save dialog box is presented, save. The next menu is the iMX6x Base Boards which leaving all as default except for the U-boot board selection which is mx6q_sabresd for the SDB. Save and exit. Images When ltib completes, the images are found in <ltib>/rootfs/boot. Bootloader = u-boot.bin Linux Kernel = uImage File system = </ltib>/rootfs

Wondering how to manage and install the various rpms generated under tmp/deploy/rpm? smart is the application you need on the target to replace apt-get Please set your local.conf with the following: # It is also recommended you use build history, which adds some sanity checks to package versions, in conjunction with the server that # is running the PR Service. To enable build history, add the following to each building system's # It is recommended to activate "buildhistory" for testing the PR service INHERIT += "buildhistory" BUILDHISTORY_COMMIT = "1" PRSERV_HOST = "localhost:0"  # This will set up your host computer as Package Revision Server // PACKAGE_FEED_URIS = "http://10.170.96.7/imx7rpm" #please place any server ip addr, this one is mine. add also the following to enable the package management (smart): EXTRA_IMAGE_FEATURES += "package-management" Setup your own http server, and link the server repository with your tmp/deploy/rpm repo (your are free to use your preferred http server). Since Morty (yocto 2.4), smart has been deprecated, and now the package management is done with dnf (from Debian). Please check dnf document to get more to know about dnf. The dependencies are still poorly controlled. After compiling a pkg the easiest remain: dnf install package.rpm example: root@imx8mmevk:~# dnf install libfuse2-2.9.7-r0.aarch64.rpm Failed to synchronize cache for repo 'oe-remote-repo-imx8m-imx8mqevk-arm', disabling. Dependencies resolved. ===============================================================================================================  Package                  Arch                    Version                   Repository                    Size =============================================================================================================== Installing:  libfuse2                 aarch64                 2.9.7-r0                  @commandline                  56 k Transaction Summary =============================================================================================================== Install  1 Package Total size: 56 k Installed size: 212 k Is this ok [y/N]: y Downloading Packages: Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction   Preparing        :                                                                                       1/1   Installing       : libfuse2-2.9.7-r0.aarch64                                                             1/1   Running scriptlet: libfuse2-2.9.7-r0.aarch64                                                             1/1 /sbin/ldconfig: /usr/lib/libOpenVG.so is not a symbolic link   Verifying        : libfuse2-2.9.7-r0.aarch64                                                             1/1 Installed:   libfuse2.aarch64 2.9.7-r0 Complete!

Q: i.Mx53 and a kernel based on our latest Linux BSP (Kernel Version 2.6.35) – They do see problems when mounting SATA Disk which is used for their rootfs. Has anyone seen this before? I am just wondering if the upcoming release might address and fix this? From the MCU i MX Product Update Call_May 2013.ppt presentation i.MX53  external release June 30 th 2013, freescale.com •       There will be patches/features for i.MX53 including Yocto for this kernel  L2.6.35 BSP release •       Validation testing Where can I check which patches / features are in this release? Is there already a Release Note? this is the kernel for the legacy release: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/log/?h=imx_2.6.35_maintain The main proposal for the next legacy release is not upgrade kernel, is only make a yocto release. And if you take meta-fsl-arm on master you will find everything from legacy release. I upstreamed every change I made internaly A: Rootwait is in the command line. Please note they can boot with Kernel version 3.2 - but customer requires 2.6.35 Kernel for other reasons. Please find attached the log files I received. A text bootlog (note sometimes booting works) but it is not stable and reliable on 2.6.35 - same HW seems stable on 3.2 Kernel Regarding to the failed messages contained in customer's log, it's a random issue. SATA driver reports that there is an " SError: { DevExch }" on the PHY connection. It seems that the SATA PHY connection is not stable enough. Can you make a double check on the cable connection and the power supply? You can disable the following configuration when build the 2.6.35 kernel image config SATA_AHCI_FSL_NO_HOTPLUG_MODE         bool "Freescale i.MX SATA AHCI NO HOTPLUG mode"         depends on SATA_AHCI_PLATFORM != n         default n         help           In order to decrease the pwr consumption, release the CLK resources such as usb_phy1_clk, when there is no SATA device adaptored into the AHCI SATA port. The HOTPLUG feature can't be enabled in this situation. Please disable this option if the HOTPLUG is mandatory required.           If unsure, say N. ============================ BTW, I just verified the RFS on SATA on i.MX53 LOCO. It's ok. Here is the log: Starting kernel ... Initializing cgroup subsys cpuset Initializing cgroup subsys cpu Linux version 2.6.35.3-01275-ge6b3f3b (r65037@shlinux1) (gcc version 4.7.3 20121001 (prerelease) (crosstool-NG hg+-946d6d133a90) ) #52 PREEMPT Tue Jul 30 11:27:17 CST 2013 CPU: ARMv7 Processor [412fc085] revision 5 (ARMv7), cr=10c53c7d CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache Machine: Freescale MX53 LOCO Board Memory policy: ECC disabled, Data cache writeback Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 250880 Kernel command line: noinitrd console=ttymxc0,115200 root=/dev/sda1 rootwait rw ... mxc_rtc mxc_rtc.0: setting system clock to 1970-01-01 00:00:01 UTC (1) Waiting for root device /dev/sda1... ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) ata1.00: ATA-8: SanDisk SSD P4 32GB, SSD 8.00, max UDMA/133 ata1.00: 62533296 sectors, multi 1: LBA48 ata1.00: configured for UDMA/133 ata1: EH complete scsi 0:0:0:0: Direct-Access     ATA      SanDisk SSD P4 3 SSD  PQ: 0 ANSI: 5 sd 0:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sda: sda1 sda2 sd 0:0:0:0: [sda] Attached SCSI disk VFS: Mounted root (ext2 filesystem) on device 8:1. Is there a possibility to tweak timing parameters? Maybe that could help to get it more robust? Are there other parameters we can try to play with and could explain failing Sata RFS on some i.Mx53 boards? I got more info from customers and also "hints" to other forum entries realted to that problem. http://lists.debian.org/debian-arm/2012/03/msg00059.html http://debian.2.n7.nabble.com/Linux-2-6-35-3-Kernel-for-ARM-and-SATA-problems-td1664800.html """ Linux version 2.6.35.3-mx53qsb (mike@ubuntu) (gcc version 4.6.1 (Ubuntu/Linaro 4.6.1-9ubuntu3) ) #3 PREEMPT Sat Mar 17 15:34:48 PDT 2012 CPU: ARMv7 Processor [412fc085] revision 5 (ARMv7), cr=10c53c7f CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache Machine: Freescale MX53 LOCO Board ... ata1: SATA max UDMA/133 irq_stat 0x00000040, connection status changed irq 28 ... ata1: SATA link down (SStatus 1 SControl 300) ata1: exception Emask 0x10 SAct 0x0 SErr 0x4000000 action 0xe frozen t4 ata1: irq_stat 0x00000040, connection status changed ata1: SError: { DevExch } ata1: hard resetting link ata1: SATA link down (SStatus 1 SControl 300) ata1: EH complete """ http://www.raspberrypi.org/phpBB3/viewtopic.php?f=9&t=4256&start=175 As mentioned custoemr sees simlar problems with our test image. Maybe one way to check, can you provide me our u-boot and uImae you did the test with? Customer confirmed their HW is compatible with MX53 LOCO Board so I would like to make sure they use correct SW and use what you tested. A bit strange is also that this Problem shows never up on a 3.2 based kernel. However the end customer requires to stay on 2.6.35 for other reasons. - kernel 3.2 which is able to initialize always. - protocol logs for good and bad case trans -p uImage.mx5.35 File keyword is ngbl7927a Data transfer to Austin Transcend repository started.   File size is 2.94 MB. Transfer Method:  Serial with no encryption. File 'uImage.mx5.35' (size 2.94 MB) transcended. Retrieve the file with the keyword:  ngbl7927a TransWeb URL:  http://transweb.freescale.net/index.cgi?go=KEYWORD&KEYWORD=ngbl7927a This file will be deleted in three working days. Local Deletion Time:  Thu Aug 15 23:51:16 2013 CST Greenwich Mean Time:  Fri Aug 16 04:51:16 2013 GMT I know that i.MX53 SATA doesn't have the adjust-window like the adjust window contained by i.MX6Q SATA. As I know that we didn‘t release 3.2 kernel version BSP, right? Regarding to the experience of ”http://debian.2.n7.nabble.com/Linux-2-6-35-3-Kernel-for-ARM-and-SATA-problems-td1664800.html”, it seems that the updates of the SATA stack of Linux level up the timing-compatibility of SATA. Derived from the URL listed above. ”I did trace the problems I having to the ahci code in the kernel not properly handling an ahci CONINIT event generated by my WD5000BEVT drive.  Seems this drive has extra SATA features implemented so that it can be used in hot-plug arrays and these features aren't recognized by the kernel driver so it just seems to shut down the drive and ignore it.  The other SATA drive that I do have working with the kernel doesn't implement the extra features so the kernel is happy.  Presumably these problems were fixed in later kernels and the patches didn't make it into Freescales 2.6.35.3 branch. On the other hand, the kernel might be fine and the firmware in the drive isn't conforming to the ahci specs, but I think that wold cause problems with the drive on other systems. ” This document was generated from the following discussion: i.MX53 Sata rootfs problem