i.MX8DXL DDR3L EVK board, nor flash using is MT25QU512ABB8ESF-0SIT.
This doc will show reference of FlexSPI configuration parameters to make booting from MT25Q flash, with QUAD pad and DDR mode.
HW: i.MX8DXL DDR3L EVK board
SW: Linux 5.4.70 BSP
From RM 5.9.3.2 FlexSPI serial flash BOOT operation, the FlexSPI boot flow as :
FlexSPI configuration parameters, could be think as two kind group: parameter for FlexSPI controller, parameter related to the operation on nor flash.
Full parameter table check check i.MX8DXL RM Table 5-20. FlexSPI Configuration block.
Let us check MT25Q data sheet for its feature, note our target is DDR mode(80MHZ) and QUAD pad:
Now let us change the FlexSPI configuration parameters:
1>readSampleClkSrc , set as 2 , that is loop back from SCK pad; this filed default set as 0, as found default value booting will met failure in this use case, so change to 2.
2>deviceModeCfgEnable set 1, deviceModeSeq.seqNum set 1 , deviceModeSeq. seqId set to 4; deviceModeArg set 0x5f.
i.MX8DXL will send some cmd to flash to make MT25Q enter DDR mode and QUAD mode, so deviceModeCfgEnable =1.
For seqNum=1, seqId =4; means index 4 of LUT table will store this sequence, and cost one LUT entry. We will explain how to change LUT entry later.
For deviceModeArg=0x5f, check MT25Q data sheet, its enhanced volatile register could be write to configure the flash working mode:
3>controllerMiscOption as 0x40, this parameter only for FlexSPI controller itself, means as” External device works using DDR commands”.
4>deviceType=1(Serial Nor), sflashPadType=4 (QUAD pad), serialClkFreq=4(80MHZ CLK), these parameter also only for FlexSPI controller.
5>sflashA1Size fill actual size, in terms of bytes
6>LUT entry changes, check 8DXL RM Table 5-21:
So LUT entry 0 is sequence for Read command, entry 1 is for Read Status sequence, entry 3 is for Write Enable sequence, entry 15 is for Dummy command sequence.
Other index LUT entry(for example 2,4,6,7,8,10,12,13,14) is could be used for store your sequence for some cmd your flash device neede. We store sequence of writing MT25Q enhance volatile register as LUT entry 4.
Check 8DXL RM, Figure 15-6. LUT and sequence structure:
Each LUT entry (sequence) will using 16 byte, one sequence consists of up to 8 instructions, each instruction will using 16bit.
Each instruction format as opcode—num_pads—operand.
Check RM 15.2.4.8 Programmable Sequence Engine, for supported instructions:
Actually the Write enable sequence is run first before the other sequence, as we will write Mt25Q volatile register, before that need issue Write enable sequence.
Check MT25Q data sheet:
For this sequence only need one instruction, that is 0x0406, at this time still using is SDR and one pad mode: Opcode (CMD_SDR), one pad (0), operand (6).
LUT entry 1, Read status sequence, it is READ STATUS REGISTER (05h) of MT25Q , check data sheet:
It use two instructions:
0x0405: opcode(CMD_SDR), pad (one pad), operand (0x5, READ STATUS REGISTER)
0x2404: opcode(READ_SDR), pad (one pad), operand (0x4 , byte number)
LUT entry 4, that is for make MT25Q enter DDR mode and quad pad:
From MT25Q data sheet:
It will use two instructions, that is
0x0461: opcode (CMD_SDR), one pad (0), operand (0x61 WRITE ENHANCED VOLATILE CONFIGURATION REGISTER)
0x2001: opcode (WRITE_SDR 08), one pad(0), operand (1 byte data size)
The 0x5f will be send out as data.
Next check LUT entry read , at this time MT25Q had enter QUAD pad and DDR mode:
LUT entry 0, Read sequence, it is fast read data from MT25Q, from data sheet:
will use four instructions , that is :
86ED, opcode (CMD_DDR ), pad ( four pad), operand (0xEDh fast read)
8a18, opcode (RADDR_DDR), pad (four pad), operand (0x18 , three byte address)
B210, opcode(DUMMY_ADDR), pad (four pad), operand(0x10, dummy cycle)
A604, opcode (READ_DDR), pad (four pad) , operand (0x4, data byte)
Reference:
1.i.MX8DXL Reference Manual
2.MT25Q data sheet
