embWiSe Technologies (acronym for Embedded Wireless Systems Engineering), provides complete embedded WiFi drivers for different WiFi chipsets. embWiSe is pleased to be part of the Freescale's i.MX community and is fully committed to provide its WiFi driver support on all of the i.MX platforms. embWiSe's WiFi driver software solution mitigates engineering leadtime and time-to-market issues and reduces TCO for device designers. embWiSe has design-ins in several Mobile,CE and other connected devices across the world - including smartphones,featurephones,printers,DSCs and handheld devices for different applications and verticals. Specifically, embWiSe offeres SDIO-WiFi + Bluetooth drivers on WinCE6.0, WEC7 and WEC2013 Operating Systems on i.MX51,i.MX53 and i.MX6 platforms. The WiFi driver is integrated with the native SDIO stack and security supplicants of WEC7 and WEC2013. embWiSe also provides HCI Bluetooth driver over SDIO and UART interfaces, integrated with the native BT stack. Additionally, embWiSe offers SDIO-WiFi drivers on other embedded OS platforms including ThreadX,Nucleus Plus,QNX,uC/OS and uITRON. embWiSe also provides value-added engineering services to integrate,test and validate the WiFi drivers on custom hardware platform. For more details, visit http://www.embwise.com or contact info@embwise.com for more specific information.

Introduction The Intel® Neural Compute Stick 2 (Intel® NCS 2) is Intel’s newest deep learning inference development kit. Packed in an affordable USB-stick form factor, the Intel® NCS 2 is powered by latest VPU (vision processing unit) – the Intel® Movidius™ Myriad X, which includes an on-chip neural network accelerator called the Neural Compute Engine. With 16 SHAVE cores and a dedicated hardware neural network accelerator, the NCS 2 offers up to 8x performance improvement+ over the previous generation. Ref: https://software.intel.com/en-us/articles/run-intel-openvino-models-on-intel-neural-compute-stick-2   The NCS 2 officially supported hardware platform is x86 PC and Raspberry Pi. In this guide, we will introduce how to implement in i.MX8MQ. Please see attached guide for more details.

The attched package includes mbedTLS and DCP/RNGB driver based on SDK2.2, you can apply it on Windows Installer: MCUXpresso SDK2.2 for i.MX 6ULL 1. fsl_dcp.c/fsl_dcp.h and fsl_rngb.c/fsl_rngb.h under devices\MCIMX6Y2\drivers is dcp ang rngb driver. 2. Some files under middleware\mbedtls-2.4.0\port\sdk are porting code for mbedTLS 3. Example codes are under folder boards\evkmcimx6ull which have driver example and mbedTLS example. 4, The patch package only support IAR toolchain. 5, Due to SDK don't support allocation of non-cachable memory dynamically, so some static non-cachable bufferes in sdk_mbedtls.c is used for shared memory with hareware. So mbedTLS don't be used for multi-thread concurrently.

I am designing settop using iMX.6Q sabre solution. What is the android platform key? Why need  the android platform key? Thank in advance

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MX6X_3.14.28_Uboot_V1-20150917.doc

For IMX8QM and iMX8QXP, the DDR config is in SCFW porting kit with DDR script. After boot, for iMX8QM, the LPDDR4 clock is set to 1.6GHz, and for iMX8QXP, after boot, the LPDDR4 clock is set to 1.2GHz. Their clock source is a HPPLL (High Performance PLL) , the HPPLL work frequency range is 1.25GHz to 2.5GHz. But for some product, due to some EMC signal test requirement, sometimes we need adjust the DDR clock a little, the attached patches can be used as reference to do such test. iMX8QM:    HPPLL = 1600MHz, DRC clock = 800MHz, DDR clock = 1600MHz. iMX8QXP:    HPPLL = 2400MHz, DRC clock = 600MHz, DDR clock = 1200MHz. After applied attached two reference patches in SCFW porting kit, they will be: iMX8QM:    HPPLL = 1584MHz, DRC clock = 792MHz, DDR clock = 1584MHz. iMX8QXP:    HPPLL = 2388MHz, DRC clock = 597MHz, DDR clock = 1194MHz. If you want to try set other clock frequency for iMX8QM, you can change the followed lines: ......  uint32_t rate2 = SC_792MHZ;  /* DRC clock */ ......  DSC_AIRegisterWrite(0x12,0,4,0x00000084);  /* DRC_0: (24M*0x84/2) = 1584M, valid dividder: 0x68~0xD0 */  //This is the HPPLL frequency ......  DSC_AIRegisterWrite(0x28,0,4,0x00000084);  /* DRC_1: (24M*0x84/2) = 1584M, valid dividder: 0x68~0xD0 */  //This is the HPPLL frequency ...... If you want to try set other clock frequency for iMX8QXP, you can change the followed lines: ......  uint32_t rate2 = 597000000U;  /* DRC clock */ ......  DSC_AIRegisterWrite(0x24,0,4,0x000000C7);  /* DRC_0: (24M*0xC7/2) = 2388M, valid dividder: 0x68~0xD0 */  //This is the HPPLL frequency ......

本文旨在说明基于i.MX8X如何设计硬件平 台，包括相关设计资源的收集与学习，硬件原 理图设计，layout，启动(bring up)，量产准备， 及正式量产后的失效分析与失效控制。主要是 帮助厘清硬件开发相关从头到尾的问题。 请注意本文为培训和辅助文档，部分内容源 自PMIC/i.MX8X硬件开发指南，并作中文翻 译，强调重点，和查缺补漏，本文不是官方文 档的替代，请一切以官方文档为准。 目录： i.MX8X硬件参考平台 ................................................. 3 2 i.MX8X硬件设计资源 ................................................. 5 i.MX8X芯片相关设计资源 ............................................... 5 i.MX8QXP MEK板外设相关设计资源 ........................... 10 i.MX8QXP 硬件接口规范 .............................................. 11 3 i.MX8X原理图设计检查点 ........................................ 13 PMIC+i.MX8X供电能力和上电时序 .............................. 13 PMIC电源输出端设计 ................................................... 17 I.MX8X电源输入端及去耦设计 ..................................... 22 LPDDR4内存设计 ........................................................ 23 DDR3L内存设计 ........................................................... 25 I2C总线设计 ................................................................. 26 Reset，Wdog reset和On/Off设计建议 ......................... 27 PCIe设计 ...................................................................... 29 USB设计 ...................................................................... 30 晶体时钟设计 ............................................................... 32 JTAG信号端接设计 ...................................................... 34 未使用接口管脚的端接处理 .......................................... 35 GPIO管脚的设计策略 ................................................... 37 调试接口建议 ............................................................... 37 4 i.MX8X 布线设计检查点 ........................................... 40 PMIC电源输出端布线建议 ............................................ 40 i.MX8X端去耦电容摆放 ................................................ 41 电源布线建议 ............................................................... 41 PCB叠层建议 ............................................................... 43 内存布线通用建议 ........................................................ 43 LPDDR4内存布线建议 ................................................. 44 DDR3L内存布线建议.................................................... 45 内存信号完整性仿真建议 ............................................. 47 内存JEDEC信号兼容性测试 ......................................... 48 高速电路板布线建议..................................................... 49 时钟建议 ...................................................................... 50 信号线阻抗建议 ............................................................ 53 USB布线建议 ............................................................... 54 5 i.MX8X硬件散热设计 ............................................... 54 6 i.MX8X硬件启动bring up .......................................... 56 Bring up需要参考的文档与使用工具............................. 56 i.MX8X Bring up需要准备的文档与使用工具 ............................. 60 Bring up检查列表 .......................................................... 65 7 试产与量产前检查点 ................................................. 67 内存稳定性 ................................................................... 67 ESD与EMI考虑 ............................................................. 68 产线设计 ....................................................................... 69 8 i.MX8X失效分析流程 ................................................ 70 NXP失效分析服务 ........................................................ 70 NXP FA失效分析流程 ................................................... 70 筛查是否是芯片原生问题 .............................................. 72 9 量产厂线的EOS/ESD控制 ........................................ 73 什么是EOS/ESD ........................................................... 73 设计中的EOS/ESD风险检查点 ..................................... 75 生产产线中的EOS/ESD风险与防护 .............................. 78

Basic Linear Algebra Subprograms (BLAS) is a specification that prescribes a set of low-level routines for performing common linear algebra operations such as vector addition, scalar multiplication, dot products, linear combinations, and matrix multiplication. OpenBLAS is an optimized BLAS library which is uesd for deep learning accelerator in Caffe/Caffe2. I enable it in Yocto (Rocko) by adding bb file. And I build on i.MX6QP, i.MX7ULP and i.MX8MQ and also run its test example successfully. You can find test example(openblas_utest) under folder image/opt/openblas/bin of OpenBLAS work directory. Currently, version 0.3.0 is supported in the bb file. +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ update to v 0.3.6 and enable mutli-thread by set USE_OPENMP=1 and USE_THREAD=4 when compiling this library.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-341641 

The i.MX28 family of multimedia applications processors is the latest extension of Freescale's ARM9 product portfolio. The i.MX28 family integrates display, power management, and connectivity features unmatched in ARM9-based devices, reducing system cost and complexity for cost sensitive applications. It also integrates CAN, USB and Ethernet connectivity with full AEC-Q100 automotive qualification for automotive applications. i.MX Family Comparison Product Information on Freescale.com i.MX280 i.MX280 Multimedia Applications Processor i.MX281 i.MX281 Multimedia Applications Processor i.MX283 i.MX283 Multimedia Applications Processor i.MX285 i.MX285 Multimedia Applications Processor i.MX286 i.MX286 Multimedia Applications Processor i.MX287 i.MX287 Multimedia Applications Processor Evaluation/Development Boards and Systems MCIMX28EVKJ: i.MX28 Evaluation Kit How to add support for a new NAND How to add a New on imx28 with Win CE Running a mainline kernel on a MX28EVK board How to enable SPI NOR boot for iMX28 (Spansion s25fl256s) Embedded Software and Tools Android OS for i.MX Applications Processors i.MX28 Software and Development Tool Resources Additional Resources Adding Support For a New NAND with i.MX28–NAND Analysis Adding Support For a New NAND with i.MX28 on Win CE Board bring-up and DDR initialization tools i.MX as a USB Playback/Capture Device on One OTG Port i.MX28: GPIO interrupt on both rising and falling edges How to enable SPI NOR boot for iMX28 (Spansion s25fl256s) Running a Mainline Kernel on an i.MX28 EVK Board Running mk_mx28_sd on Ubuntu 12.04 Ubuntu 12.04 64-bit Precise Pangolin Host Setup for Building i.MX28 L2.6.35_MX28_SDK_10.12_SOURCE Use LCD_D11 pin for enet reset in iMX28

When working with IPU applications, sometimes image format converter is needed to check images generated by IPU that are not readable by PC (e.g. RGB565, common i.MX framebuffer format -> png or jpg) or generate a RGB picture from an encoded file to be read by IPU (e.g. png -> RGB565 framebuffer). There are some useful tools on Linux and some also available on Windows that can perform these conversions. I listed 5 tools with some usage examples below. IMAGEMAGICK // Display a 800x600 rgb image display -size 800x600 -depth 8 rgb:output.rgb // Show information of output.rgb identify -size 1296x972 -depth 8 output.rgb // Convert a 640x480 grayscale raw rgb file to png convert -size 640x480 -depth 8 imagefile.rgb image.png // To list all available color formats identify -list format For more information about Imagemagick and its format support. access: http://www.imagemagick.org/script/formats.php FFMPEG // List available formats for ffmpeg ffmpeg -pix_fmts // Convert raw rgb565 image to png ffmpeg -vcodec rawvideo -f rawvideo -pix_fmt rgb565 -s 1024x768 -i freescale_1024x768.raw -f image2 -vcodec png screen.png // Convert png to raw rgb565 ffmpeg -vcodec png -i image.png -vcodec rawvideo -f rawvideo -pix_fmt rgb565 image.raw // Convert a 720x480 NV12 (YUV 420 semi-planar) image to png ffmpeg -s 720x480 -pix_fmt nv12 -i image-nv12.yuv -f image2 -pix_fmt rgb24 image-png.png // Convert a 640x480 uyvy422 image to png ffmpeg -s 640x480 -pix_fmt uyvy422 -i image-uyvy422.yuv -f image2 -pix_fmt rgb24 image-uyvy422.png MENCODER http://www.mplayerhq.hu/DOCS/HTML/en/encoding-guide.html TRANSCODING http://www.transcoding.org/cgi-bin/transcode?Examples GRAPHICSMAGICK http://www.graphicsmagick.org/

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343116 

The attached document describes how to integrate the souphttpsrc plugin and make it work.

The customer would like to test BT.656 using Test mode. Is it supported? 38.4.3.3 Test mode in RM shows only one CSIx_SENS_CONG setting. Does it mean Test mode support only one as follows? Does Test mode support other settings? CSIx_EXT_VSYNC = 0x1 CSIx_DATA_WIDTH = 0x1 CSIx_SENS_DATA_FORMAT = 0x0 CSIx_PACK_TIGHT = 0x0 CSIx_SENS_PRTCL = 0x1 CSIx_SENS_PIX_CLK_POL = 0x1 CSIx_DATA_POL = 0x0 CSIx_HSYNC_POL = 0x0 CSIx_VSYNC_POL = 0x0 For example, customer want to know if Test mode support  CSIx_SENS_PRTCL=0x2or 0x3 instead of 0x1? customer want to know if Test mode support CSIx_SENS_DATA_FORMAT=0x1or 0x2 instead of 0x0? Answer: CSI CM TEST MODE is working as below: 1,only ungated mode. 2,data width should be configured to 8 3,data format should be configured to rgb888 It cannot be other format such as bt656. It uses CSI1_TST_CTRL register to configure {R,G,B} 24 bit value and taking it as RGB888/YUV444 format for further process.  The generated image size is due to the configured width & height in the registers.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-344579 

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-345751 

This table shows how to configure i.MX51 EVK DIP Switches to boot from SD card and how to boot from internal ROM to use ATK: DS1 DS2 DS3 DS4 DS5 DS5 DS7 DS8 DS9 DS10 Boot from SD/MMC Card 0 0 0 0 0 0 1 1 0 0 Boot from i.ROM (ATK) 1 1 0 0 0 0 1 1 0 1