iMX8QM, IMX8QXP: How to adjust DDR clock for EMC test

[#1]

For IMX8QM and iMX8QXP, the DDR config is in SCFW porting kit with DDR script.

After boot, for iMX8QM, the LPDDR4 clock is set to 1.6GHz, and for iMX8QXP, after boot, the LPDDR4 clock is set to 1.2GHz. Their clock source is a HPPLL (High Performance PLL) , the HPPLL work frequency range is 1.25GHz to 2.5GHz.

But for some product, due to some EMC signal test requirement, sometimes we need adjust the DDR clock a little, the attached patches can be used as reference to do such test.

iMX8QM:

   HPPLL = 1600MHz, DRC clock = 800MHz, DDR clock = 1600MHz.

iMX8QXP:

   HPPLL = 2400MHz, DRC clock = 600MHz, DDR clock = 1200MHz.

After applied attached two reference patches in SCFW porting kit, they will be:

iMX8QM:

   HPPLL = 1584MHz, DRC clock = 792MHz, DDR clock = 1584MHz.

iMX8QXP:

   HPPLL = 2388MHz, DRC clock = 597MHz, DDR clock = 1194MHz.

If you want to try set other clock frequency for iMX8QM, you can change the followed lines:

......

 uint32_t rate2 = SC_792MHZ;  /* DRC clock */

......

 DSC_AIRegisterWrite(0x12,0,4,0x00000084);  /* DRC_0: (24M*0x84/2) = 1584M, valid dividder: 0x68~0xD0 */  //This is the HPPLL frequency

......

 DSC_AIRegisterWrite(0x28,0,4,0x00000084);  /* DRC_1: (24M*0x84/2) = 1584M, valid dividder: 0x68~0xD0 */  //This is the HPPLL frequency

......

If you want to try set other clock frequency for iMX8QXP, you can change the followed lines:

......

 uint32_t rate2 = 597000000U;  /* DRC clock */

......

 DSC_AIRegisterWrite(0x24,0,4,0x000000C7);  /* DRC_0: (24M*0xC7/2) = 2388M, valid dividder: 0x68~0xD0 */  //This is the HPPLL frequency

......