i.MX Processors Knowledge Base

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Question: LVDS in split mode (dual lvds) is used. In this configuration, only LVDS0_CLK is used. What is the suggestion for the LVDS1_CLK? The HW user guide says that if this is unused, then to leave it floating. Would we also suggest the same for this case or would termination be more appropriate? Or is there some possible way to gate this clock? (if so, it isn't obvious in the RM) Answer: According to the MX6 Developer's Guide, any unused LVDS pins should be left floating, so the LVDS1_CLK pair, in this case should be left floating. In order to minimize any potential EMC, the lands for those balls should not have any additional traces leading away. To add a bit more information, the customer ran some tests and found that the clock gate bits for the LVDS1 are essentially ignored in Dual mode. The only way to disable it is if they are both disabled which is not helpful in this case. It seems that the Dual mode setting overrides the CG.

Description by Google: Wi-Fi scan-only mode is a new platform optimization that lets users keep Wi-Fi scan on without connecting to a Wi-Fi network, to improve location accuracy while conserving battery. Apps that depend on Wi-Fi for location services can now ask users to enable scan-only mode from Wi-Fi advanced settings. Wi-Fi scan-only mode is not dependent on device hardware and is available as part of the Android 4.3 platform. Comments by Freescale: In order to enable wifi scan mode, we should make sure wifi driver shouldn't be removed while switching off wifi from Setting. Additionally, android4.3 has introduced one CTS test to force us to change all loadable modules into kernel built in. The reason is loadable modules are often used by rootkits and other exploits. so there will be big risk in security. OK, now let's try to keep up with the pace of AOSP. For AR6003, we are using compat-wireless driver which accommodates all linux kernel since 2.6.We are now using olca-3.4 wifi driver but our kernel version is 3.0.35. It is not a simple change to be directly compiled into kernel since it is lack of the basic file structure for ath6kl driver. This has been double confirmed by support guy from Atheros. More terribly, Atheros has no plan to publish new version for AR6003 but just maintain it. Yeah, my pitiful baby. Say goodbye to scan mode. This is why this document come into being. AR6003 is our default wifi module bounded to our imx6 serial board. So formal release will lose this important feature for this limitation. Here I will give out patches to enable this feature using another wifi module-----Realtek 8723as. Ok, now let's welcome this new star. Patches description: Patch for kernel--------Change loadable driver modules to compiled into kernel, this will let wlan0 and p2p0 interfaces still can be operated although you have switched off wifi in Setting UI. Patch for device/fsl--------Firstly, I delete one rfkill operation in init.rc which is obsolete for BT setting. If still keep it here, it will soft block wifi interface through mac80211 rfkill. Then I clean up some setting for wifi driver module. Patch for hardware/libhardware_legacy-------Since wifi driver is already directly built in kernel, HAL will have no need to load driver now. Refactor it and optimize it. Test it manually: If you have one sdio rtl8723as wifi module in hand, you can test it like the following to see wifi scan mode works: Firstly, disable wifi in Setting UI. then you can check netcfg result, you will see wlan0 and p2p0 are still there, only down state: Go "advanced" menu in wifi setting,Turning on the checkbox of "Scanning always available". Check netcfg result again, Oh Oh, wlan0 and p2p0 are up: Manually "scan" through "wpa_cli" tool, you will see it works:

Question: After a JTAG Reset with his GHS MULTI Probe on i.MX6 Hardware, read the SRC_SRSR register the corresponding reset source bits (JTAG reset) are not set. The contents: SRSR = 0x1 WARM Boot = 0x0 jtag_sw_rst = 0x0 jtag_rst_b = 0x0 wdog_sw_rst = 0x0 ipp_user_reset_b = 0x0 cpu_reset_b = 0x0 ipp_reset_b = 0x1 Tried to reproduce this with my DSTRAM probe, and issued a "reset reset.system" command in DS-5 Debugger but Program Counter stays at current vaule. Obviously my SRSR bits don't change either. Answer: Seems " jtag_rst_b" is a HW reset, please check the connection between JTAG port and i.Mx6 JTAG_TRST pin. And confirm the waveform on rest pin when JTAG reset run.

Question: How much control of the bitrate does the i.MX6's VPU provide? VPU API includes a bitrate setting in the EcnOpenParam, is this a maximum, minimum, or something else? To encode two 1280x1080 streams at 30fps with a bit rate of at least 20Mbps, from the information in the following thread, it looks like this isn't supported due to VPU bandwitdh, Is there any limit on bitrate due to the VPU's processing bandwidth? I.e., if the stream is limited to one 1280x1080 channel, can we choose a maximum bit rate and if so, how do we determine what it is? Answer: The bitRate field in the EncOpenParam structure is the desired target bit rate in kbps. If 0, there is no rate control and frames are encoded based on the quantization parameter specified by the quantParam field in EncParam.structure. It seems upper limit is 20Mbps for 1280x1080@30fps. So you should specified bitrate=2000 in your use case. In general, the maximum bitrate is about 30Mbps. Vpu driver will return invalid parameter if the appointed bitrate reach out of the range (0, 32767kbps). Please refer to Q&A: MX6 VPU H.264 Dual Stream Encode Limits.

Question: Is it true ture that MX6 VPU is capable of encoding dual H.264 streams that are 1024x600 at 60fps? There are slides that claim three 720p30 streams or two 1080p30 streams simultaneously. There is little guidance as to what the VPU limits in resolution, frame rate and bit rate are for other resoluitons and frame rates. Is there any information that can be used to decide if the VPU can encode an arbitrary video stream or multiple arbitrary video streams? Since memory bandwidth will enter into this decision at some point has anyone quantified the memory bandwidth requirements verses video resolution and frame rate? Answer: Maximum supported trhoughput, is 72,576,000 pixels /s @ VPU frecuency of 266 mhz 2 x 1024 x 600 x 60hz = 73,728,000 So this is not supported. If framerate is lower i.e. 30hz then it will be supported.

Hi All, The new i.MX 6 Q/D/DL/S/SL L3.0.35_4.1.0 GA release is now available on the http://www.freescale.com/site. · Files available # Name Description 1 L3.0.35_4.1.0_LINUX_DOCS i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux BSP Documentation. Includes Release Notes, Reference Manual, User guide. API Documentation 2 L3.0.35_4.1.0_LINUX_MMDOCS i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux Multimedia Codecs Documentation. Includes CODECs Release Notes and User's Guide 3 L3.0.35_4.1.0_SOURCE_BSP i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux BSP Source Code Files 4 L3.0.35_4.1.0_MM_CODECS i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux Multimedia Codecs Sources 5 L3.0.35_4.1.0_AACP_CODECS i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux AAC Plus Codec 6 L3.0.35_4.1.0_DEMO_IMAGE_BSP i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux Binary Demo Files 7 L3.0.35_4.1.0_UBUNTU_RFS_BSP i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo and i.MX 6Sololite Linux File System for the Ubuntu Images 8 i.MX_6D/Q_Vivante_VDK_146_Tools Set of applications for the Linux L3.0.35_4.1.0 BSP, designed to be used by graphics application developers to rapidly develop and port graphics applications. Includes applications, GPU Driver with vprofiler enabled and documentation. 9 IMX_6DL_6S_MFG_TOOL Tool and documentation for downloading OS images to the i.MX 6DualLite and i.MX 6Solo. 10 IMX_6DQ_MFG_TOOL Tool and documentation for downloading OS images to the i.MX 6Quad and i.MX 6Dual. 11 IMX_6SL_MFG_TOOL Tool and documentation for downloading OS images to the i.MX 6Sololite. · Target HW boards o i.MX 6Quad SABRE-SDP o i.MX 6Quad SABRE-SDB o i.MX 6Quad SABRE-AI o i.MX 6DualLite SABRE-SDP o i.MX 6DualLite SABRE-AI o i.MX 6SL EVK · New features o BSP New Features on i.MX 6D/Q, i.MX 6DL/S and MX 6SL: § HDCP § CEC § GPU4.6.9p12 § Audio playback IRAM/SDMA § V4L capture resize on MX6SL § MX6DQ disable the double line fill feature of PL310 · Known issues o For known issues and limitations please consult the release notes.

Question: Clarify if the delay units, mentioned in i.MX6 RM in two places are the same : 1. There are delay units for data strobes, that are considered in calibration procedures. 2. There are delay units for clocks SDCLK, mentioned in section 44.12.54 “MMDC PHY CK Control Register (MMDCx_MPSDCTRL)” of the RM. General delay units description states : “ The delay issued by the delay-line (according to the configured value) is absolute and takes into account the operating and temperature conditions. The delay-line has a resolution that may vary from device to device; an increment of 1 delay unit may vary between 20 pSec to 50 pSec.” It may be guessed that the same relates to SDCLK delays, but preliminary i.MX6 specs mention that bit fields SDCLKx_DEL (x=0,1) control SDCLK delay, that can be up to 1 cycle. This means SDCLKx_DEL step is 1/4 of the SDCLK. Please clarify SDCLK delays (SDCLKx_DEL) in more details. Answer: "The delay elements in the SDCLK path are similar to those in the data strobes but they are not exactly the same. The delay is on the order of picoseconds, though, not a full SDCLK cycle as might have been interpreted from the older document."

Q: how to do PCIe compliance measurement on the Sabre SDB? Phase Jitter on the PCIe reference clock had been see problem. Pin C7 "CLK1_N" and Pin D7 "CLK1_P" were used like on the Sabre SD. During Compliance meassurments margin of -80% and more.... was seen. Is there a known issue? Has someone done a similar compliance measurement on the Sabre SDB? A: The PCIe TX compliance tests on i.MX6 SD boards in TK's Open Lab. Based on the internal PLL clock, i.MX6 SD boards pass the PCIe TX compliance tests. 1, please check the capacitor on NVCC_PLL_OUT, it should no less than 10uF, 22uF is better. 2, please check if the 24MHz input crystal is good enough. 50ppm is required. 3, please check the test step: 1.1 TX Test Configuration and Procedures Overview of Test Steps 1. Integrate the patch for PCIE test to mainline, recompile the Kernel , and replace the old image of the board under test. · Make sure the following configuration has been set, when re-compiling the kernel image. # MX6 Options: # CONFIG_IMX_PCIE=y 2. Correctly set up the test environment: · Connect the compliance load board (CLB x1/x16) revision 2.0 into the slot of DUT, and change the switch and jumpers to select x1 . · Connect the lane under test to oscilloscope via differential probe and matched coaxial , do remember that cable calibration should be done before test. · Connect the clock signal to the oscilloscope. The clock must have SSC enabled or disabled to be consistent with settings for the system during normal operation. · Power on the system. 3. After I.MX6x enters Polling.Compliance , press the Toggle Button on CLB to select the output , make sure the data waveform is compliance pattern, 5.0GT/s for GEN2, 2.5GT/s for GEN1. 4. Follow the Oscilloscope operation instruction, set it to the right mode. 5. Capture and save at least 1 million * 200 ps of data and clock simultaneously at the sample rate of 50GS/s for GEN2, or 250,000 UI * 400 ps of data at the sample rate of 25GS/s for GEN1. 6. Run free software Sigtest to analyze the PCIE TX signal. 7. Customer could adjust the parameters of the PCIE_PHY by changing IOMUXC_GPR8 register settings to get the test past. a. The default of this Register is configured as: imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN1, 0 << 0, IOMUXC_GPR8); imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6, IOMUXC_GPR8); imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12, IOMUXC_GPR8); imx_pcie_clrset(IOMUXC_GPR8_TX_SWING_FULL, 127 << 18, IOMUXC_GPR8); imx_pcie_clrset(IOMUXC_GPR8_TX_SWING_LOW, 127 << 25, IOMUXC_GPR8); b. write the Register, Address: 20E_0000h base + 20h offset = 20E_0020h; command: /unit_tests/memtool -32 0x020e0020= FFFD4000 This document was generated from the following discussion: i.Mx6 PCIe compliance

Q: What is quality level of IBIS file? In chapter 8.6 in IMX6DQ6SDLHDG (Rev.0). It says the following about quality assurance. ===== All models (GPIO, DDR, LVDS, MLB) have passed the following checks: • IBISCHK without errors or unexplained warnings • Data for basic simulation checked • Data for timing analysis checked • Data for power analysis checked • Correlated against Spice simulations Validation reports can be provided upon demand. ==== A: In addition, please see http://www.vhdl.org/pub/ibis/quality_wip/checklist/Using_IQ_2.0_checklist.pdf. This document says about quality level. According to these information, the IBIS quality level is IQ4 (IQ3 + data for power analysis checked) + "Correlated against Spice simulations". This document was generated from the following discussion: IBIS QUALITIY LEVEL

Q: Can OpenGL/OpenVG work on any of our boards with a 16-bit DDR bus? Here is GPU state dump when run some of the GPU SDK tutorials on their imx6 solo board with a 16-bit DDR bus: Mounting rootfs VFS: Mounted root (nfs filesystem) readonly on device 0:12. Freeing init memory: 156K Starting init GPU[0]: ************************** *** GPU STATE DUMP *** ************************** axi = 0x000000B1 idle = 0x7FFFFF86 FE not idle SH not idle PA not idle SE not idle RA not idle DMA appears to be stuck at this address: 0x1882F230 dmaLow = 0x08010583 dmaHigh = 0x80003400 dmaState = 0x00000904 command state = 4 (PAR_ADR1_ST) command DMA state = 1 (CMD_START_ST) command fetch state = 2 (FET_VALID_ST) DMA request state = 0 (REQ_IDLE_ST) cal state = 0 (CAL_IDLE_ST) VE request state = 0 (VER_IDLE_ST) RA debug registers: [0x00] 0x0108C378 [0x01] 0x0042FB12 [0x02] 0x0042FB11 [0x03] 0x0000022C [0x04] 0x10220033 [0x05] 0x0885C800 [0x06] 0xC054CBFE [0x07] 0x68100000 [0x08] 0x00000000 [0x09] 0x00000000 [0x0A] 0x00000000 [0x0B] 0x00000000 [0x0C] 0x12344321 [0x0D] 0x12344321 [0x0E] 0x12344321 [0x0F] 0x12344321 signature = 0x12344321 (1 read attempt(s)) TX debug registers: [0x00] 0x00000000 [0x01] 0x00000000 [0x02] 0x00000000 [0x03] 0x00000000 [0x04] 0x00000000 [0x05] 0x00000000 [0x06] 0x00000000 [0x07] 0x00000000 [0x08] 0x00000000 [0x09] 0x00000000 [0x0A] 0x00000000 [0x0B] 0x00000000 [0x0C] 0x00000000 [0x0D] 0x00000000 [0x0E] 0x00000000 [0x0F] 0x00000000 failed to obtain the signature (read 0x00000000). FE debug registers: [0x00] 0x1882F450 [0x01] 0x08010594 [0x02] 0x00000001 [0x03] 0x00000256 [0x04] 0x00080049 [0x05] 0x0000000D [0x06] 0x00009571 [0x07] 0x00007445 [0x08] 0x00000004 [0x09] 0x00000000 [0x0A] 0x00000000 [0x0B] 0x00000000 [0x0C] 0x00000000 [0x0D] 0xA3105D67 [0x0E] 0x000000D0 [0x0F] 0xBABEF00D signature = 0xBABEF00D (1 read attempt(s)) PE debug registers: [0x00] 0x0108C369 [0x01] 0x00000000 [0x02] 0x0108C369 [0x03] 0x00000000 [0x04] 0xA0000000 [0x05] 0xABC00000 [0x06] 0xBC000000 [0x07] 0xCDE00000 [0x08] 0xD04045C0 [0x09] 0x204045C0 [0x0A] 0x0D863084 [0x0B] 0x00000000 [0x0C] 0xBABEF00D [0x0D] 0xBABEF00D [0x0E] 0xBABEF00D [0x0F] 0xBABEF00D signature = 0xBABEF00D (1 read attempt(s)) DE debug registers: [0x00] 0x00000000 [0x01] 0x00000000 [0x02] 0x00000000 [0x03] 0x00000000 [0x04] 0x00000000 [0x05] 0x00000000 [0x06] 0x00000000 [0x07] 0x00000000 [0x08] 0x00000000 [0x09] 0x00000000 [0x0A] 0x00000000 [0x0B] 0x00000000 [0x0C] 0x00000000 [0x0D] 0x00000000 [0x0E] 0x00000000 [0x0F] 0x00000000 failed to obtain the signature (read 0x00000000). SH debug registers: [0x00] 0x0049AB4C [0x01] 0x0000000B [0x02] 0x00000411 [0x03] 0x00020A95 [0x04] 0x00000000 [0x05] 0x000F024E [0x06] 0x000F424C [0x07] 0x010BEC30 [0x08] 0x0108C368 [0x09] 0x000020DF [0x0A] 0x00000693 [0x0B] 0x00000000 [0x0C] 0x00000000 [0x0D] 0x00000000 [0x0E] 0x00000000 [0x0F] 0xDEADBEEF signature = 0xDEADBEEF (1 read attempt(s)) PA debug registers: [0x00] 0x640006FE [0x01] 0x64000000 [0x02] 0x00000810 [0x03] 0x00000690 [0x04] 0x00000230 [0x05] 0x0000022D [0x06] 0x00000000 [0x07] 0x00000000 [0x08] 0x00000003 [0x09] 0x0000AAAA [0x0A] 0x0000AAAA [0x0B] 0x0000AAAA [0x0C] 0x0000AAAA [0x0D] 0x0000AAAA [0x0E] 0x0000AAAA [0x0F] 0x0000AAAA signature = 0x0000AAAA (1 read attempt(s)) SE debug registers: [0x00] 0x00000000 [0x01] 0x00000000 [0x02] 0x00000000 [0x03] 0x00000000 [0x04] 0x00000000 [0x05] 0x00000000 [0x06] 0x00000000 [0x07] 0x00000000 [0x08] 0x00000000 [0x09] 0x00000000 [0x0A] 0x00000000 [0x0B] 0x00000000 [0x0C] 0x00000000 [0x0D] 0x00000000 [0x0E] 0x00000000 [0x0F] 0x00000000 failed to obtain the signature (read 0x00000000). MC debug registers: [0x00] 0x00000000 [0x01] 0x00000000 [0x02] 0x00000000 [0x03] 0x00000000 [0x04] 0x12345678 [0x05] 0x12345678 [0x06] 0x12345678 [0x07] 0x12345678 [0x08] 0x12345678 [0x09] 0x12345678 [0x0A] 0x12345678 [0x0B] 0x12345678 [0x0C] 0x12345678 [0x0D] 0x12345678 [0x0E] 0x12345678 [0x0F] 0x12345678 signature = 0x12345678 (1 read attempt(s)) HI debug registers: [0x00] 0x0000F719 [0x01] 0x19C020C8 [0x02] 0x1EBC2426 [0x03] 0xAAAAAAAA [0x04] 0xAAAAAAAA [0x05] 0xAAAAAAAA [0x06] 0xAAAAAAAA [0x07] 0xAAAAAAAA [0x08] 0xAAAAAAAA [0x09] 0xAAAAAAAA [0x0A] 0xAAAAAAAA [0x0B] 0xAAAAAAAA [0x0C] 0xAAAAAAAA [0x0D] 0xAAAAAAAA [0x0E] 0xAAAAAAAA [0x0F] 0xAAAAAAAA signature = 0xAAAAAAAA (1 read attempt(s)) Other Registers: [0x0040] 0x00924A66 [0x0044] 0x06F47370 [0x004C] 0x06F47370 [0x0050] 0x00DE8E6E [0x0054] 0x00DE8E6E [0x0058] 0x00924A66 [0x005C] 0x001254D6 [0x0060] 0x001254D6 [0x043C] 0x00000000 [0x0440] 0x00000000 [0x0444] 0x00000000 [0x0414] 0x3C000000 [<8003b21c>] (unwind_backtrace+0x0/0xfc) from [<80308114>] (_DumpGPUState+0x4ec/0x6b4) [<80308114>] (_DumpGPUState+0x4ec/0x6b4) from [<80308324>] (gckOS_Broadcast+0x38/0xe8) [<80308324>] (gckOS_Broadcast+0x38/0xe8) from [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) from [<80311294>] (gckEVENT_Submit+0x8c/0x328) [<80311294>] (gckEVENT_Submit+0x8c/0x328) from [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) from [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) from [<80306580>] (drv_ioctl+0x108/0x250) [<80306580>] (drv_ioctl+0x108/0x250) from [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) from [<800edc9c>] (sys_ioctl+0x38/0x60) [<800edc9c>] (sys_ioctl+0x38/0x60) from [<80035580>] (ret_fast_syscall+0x0/0x30) A: This GPU driver stack dump indicates GPU stuck when VDDPU_CAP was under spec values (1.2V) so GPU was not correctly powered. Was fixed by adjusting PMU_REG_CORE[REG1_TARG]. AFAIK, GPU drivers have some DDR bank configuration, so you may see a different problem though.

Q: ”We noticed that the specified risetime of this signal is max 5nS, while the Sable board schematic shows it driven from open collector/drain using only the 100k haulup provided in the chip. This will have risetimes of 10‘s (if not 100‘s!) of ns. The worrying thing is that the latest datasheet update specifically clarifies this rise time spec, so presumably it‘s considered important. Which is right? If the rise time spec needs to be met, we need a small haul up resistor or an active drive. In that case what rail should be used to haul/drive POR_B high?” It appears to be correct, and what is interesting I checked the PFUZE timing in the datasheet ”tr4 Rise time of RESETBMCU - 0.2 ms” Device: i.MX6Q OS: Linux Dev Board: i.MX6Q SDB A: The 5ns rise/fall time requirement does not apply to i.MX6. This was probably carried over from the i.MX53 where it was required. This will be removed from the datasheet but it will likely not be until the September time frame. We're not doing an update to any of the electrical parameters of the datasheet right now.

Q: What is the Min LPDDR2 clock frequency allowed by the i.MX6? The Jedec Spec for LPDDR2 allows for a min tck period of 100ns. Are there any required relashionship between the DDR clock frequency and other clocks in the i.MX6? A: The JEDEC maximum period for the MX6 is 100nS as per the LPDDR2 specification. There is a minimum period during boot, before everything is configured and fully up to speed of 18nS. Are you saying the imx6 memory controller can operatate down to the min frequecies specified in the LPDDR2 JEDEC spec? Given that there is no limit specified in the data sheet, it should operate that slowly, provided the clocking can be set for it to operate so slowly. I would imagine that the core will need to be running slowly as well, since it does not make sense to slow the memory bus without slowing the core down as well.

Q: What is i.Mx6 ECSPI max frequency? https://community.freescale.com/message/338305 But in the RM we clearly state 60 MHz is the default config while Boot from SPI. I cannot measure it because I have no board where I can boot from SPI Nor. Also if I look at clocking, PLL is 480MHz divided by 8 is fixed thus we get 60 MHz. Next divider can be either 1, thus ECSPI_CLK_ROOT = 60MHz or 2, thus ECSPI_CLK_ROOT = 30 MHz. A: From i.MX6 Datasheet (IMX6DQCEC, Rev. 2.3, 07/2013), Table 52 (ECSPI Master Mode Timing Parameters) : ECSPIx_SCLK Cycle Time–Read • Slow group 55 ns • Fast group 40 ns ECSPIx_SCLK Cycle Time–Write 15 ns So, only for writing we can get ~60 MHz.

Qt framework Qt is a cross-platform complete development framework with tools designed to streamline the creation of stunning native applications and amazing user interfaces for desktop, embedded and mobile platforms. Qt's cross-platform full framework and tools enables developers to target various desktop, embedded, mobile and real-time operating systems with one code base. Qt brings freedom to the developer saving development time, adding efficiency and ultimately shortening time to market. Building Qt Compile Qt for i.MX28 Building QT5 for i.MX53 Building QT for i.MX6 Qt on iMX6 Installing tools Installing and Configuring QT Creator (Ubuntu) Qt5 with Qt3D over Wayland rootfs Demos Qt5 Cinematic Experience Demo on i.MX6 Video - IMx 53 Qt5 qt3d demo Qt5 with Qt3D over Wayland rootfs Information Qt5 on i.MX6 DO's and DONT's Best Practices for QML

ERR005723 PCIe: PCIe does not support L2 Power Down Description: When PCIe works as Root Complex, it can exit L2 mode only through reset. Since PCIe doesn't have a dedicated reset control bit, it cannot exit L2 mode. Projected Impact: PCIe does not support L2 Power Down Workarounds: The PCIe can be put in PDDQ mode to save on PCIe PHY power and wakeup only by the OOB (Out of Band) wakeup signal (since wakeup by a beacon from link partner is not supported) driven from the link partner (End Point). This signal could be used as a GPIO interrupt to exit this mode. The limitation of this workaround is that the link partner cannot be put into L2. Proposed Solution: No fix scheduled Linux BSP Status: No software workaround available SW workaround used to fix ERR005723 in Linux BSP Why the original workarounds can’t be implemented in Linux BSP * PCIe controller doesn’t have the reset mechanism that can be used when re-insmod the PCIe driver without power down/up PCIe module. * During the PCie driver rmmod/insmod operations, the PCIe CLKs would be turned off/on. IC can’t guarantee that the PCIe PHY can work well and re-establish the PCIe link properly. One SIMPLE SW workaround for this errata imx: pcie: toggle bit18 of grp1 fix pcie can't exit L2 issue. Set bit18 of gpr1 before enter into supend, and clean it after resume, can fix the following errata. Errata ERR005723_PCIe PCIe does not support L2 Power Down. About the details, please refer to the attached patch. "0001-imx-pcie-toggle-bit18-of-grp1-fix-pcie-can-t-exit-L2.patch" The conception of the other SW workaround (System warm-reset) The procedures of the original suspend/resume. Suspend User suspend command echo mem > /sys/power/state All driver call suspend function SRPG, ARM save all state to memory Enter Stop mode and Power down ARM Resume: GPC receive IRQ Wake up system Power on ARM domain. ROM code running Jump to SRPG point Recovery ARM status from memory Call all devices resume function. Because PCIe only reset by system reset, we need change above follow. Resume: GPC receive IRQ Wake up system Power on ARM domain. ROM code running Jump to SRPG point Warm Reset system, memory context will be kept. But all peripheral status lost. ROM code running Jump to SRPG point again. Recovery ARM status from memory Call all devices resume function. Resume function call init to initialize it. And recover to the status saved before. Impact: Can’t support usb remote wake up, which required 4ms responsive Longer latency, warm reset need some ms. The recovery of the device status needs some more ms. Risk: Current BSP have not tested above follow Device driver have not supported this follow yet. Need additional work to enable \debug\test it. Modules enabled in this workaround now: * UART* ENET* PCIe Tests procedure. HW: one i.MX6Q SD boards, and one INTEL pciex1 1000M CT network card. SW(The images used by me are attached): * Apply the attached patches(kernel and uboot) to the kernel/uboot source codes, re-build, get the images. Kernel is based on imx_3.0.35_4.0 release, uboot , is based on imx_v2009.08 # build out SD/MMC and USB driver to make DRAM hibernate work # build pcie in. *procedure of the suspend/resume tests; # unload ep's driver --> suspend/resume --> reload ep's driver. NOTE: Please make sure that the command line contains “no_console_suspend”The command used to enable the console input wake up after login the consol:echo enabled > /sys/devices/platform/imx-uart.0/tty/ttymxc0/power/wakeup Log when the INTEL CT 1G network card is used: -------------------------------log--------------------------------------------PM: Syncing filesystems ... done.  start suspendFreezing user space processes ... (elapsed 0.01 seconds) done.Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.add wake up source irq 101add wake up source irq 99add wake up source irq 103add wake up source irq 51add wake up source irq 58PM: suspend of devices complete after 15.482 msecsPM: late suspend of devices complete after 0.823 msecsDisabling non-boot CPUs ...CPU1: shutdownCPU2: shutdownCPU3: shutdownIMX PCIe imx_pcie_pltfm_suspend entering.IMX PCIe imx_pcie_pltfm_suspend exit.  suspendedU-Boot 2009.08-00679-g6ec6783 (May 20 2013 - 14:50:20)  resumeCPU: Freescale i.MX6 family TO1.2 at 792 MHzsrc 0x92eac8resume 0x92eac8jump to resumeIMX PCIe imx_pcie_pltfm_resume entering.IMX PCIe imx_pcie_pltfm_resume pcie start re-link.IMX PCIe port imx_pcie_pltfm_resume: re-link up.Enabling non-boot CPUs ...CPU1: Booted secondary processorCalibrating delay loop (skipped) already calibrated this CPU i.MXC CPU frequency driver CPU1 is upCPU2: Booted secondary processorCalibrating delay loop (skipped) already calibrated this CPU i.MXC CPU frequency driver CPU2 is upCPU3: Booted secondary processorCalibrating delay loop (skipped) already calibrated this CPU i.MXC CPU frequency driver CPU3 is up PM: early resume of devices complete after 0.974 msecs remove wake up source irq 58 imx-ipuv3 imx-ipuv3.0: IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7) imx-ipuv3 imx-ipuv3.1: IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7) remove wake up source irq 51 remove wake up source irq 103 remove wake up source irq 101 remove wake up source irq 99 PM: resume of devices complete after 54.174 msecs Restarting tasks ... done. PHY: 1:01 - Link is Up - 100/Full  resume is ok, reload ep’s driver num is 61 e1000e: Intel(R) PRO/1000 Network Driver - 1.3.10-k2 e1000e: Copyright(c) 1999 - 2011 Intel Corporation. e1000e 0000:01:00.0: Disabling ASPM L0s e1000e 0000:01:00.0: (unregistered net_device): Failed to initialize MSI-X interrupts. Falling back to MSI interrupts. e1000e 0000:01:00.0: (unregistered net_device): Failed to initialize MSI interrupts. Falling back to legacy interrupts. e1000e 0000:01:00.0: eth1: (PCI Express:2.5GT/s:Width x1) 00:1b:21:3a:18:8b e1000e 0000:01:00.0: eth1: Intel(R) PRO/1000 Network Connection e1000e 0000:01:00.0: eth1: MAC: 3, PHY: 8, PBA No: E42641-005 e1000e: eth1 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx PING 192.168.0.1 (192.168.0.1): 56 data bytes 64 bytes from 192.168.0.1: seq=0 ttl=64 time=3.126 ms 64 bytes from 192.168.0.1: seq=1 ttl=64 time=0.244 ms 64 bytes from 192.168.0.1: seq=2 ttl=64 time=0.232 ms 64 bytes from 192.168.0.1: seq=3 ttl=64 time=0.206 ms 64 bytes from 192.168.0.1: seq=4 ttl=64 time=0.222 ms 64 bytes from 192.168.0.1: seq=5 ttl=64 time=0.207 ms 64 bytes from 192.168.0.1: seq=6 ttl=64 time=0.250 ms 64 bytes from 192.168.0.1: seq=7 ttl=64 time=0.209 ms 64 bytes from 192.168.0.1: seq=8 ttl=64 time=0.154 ms 64 bytes from 192.168.0.1: seq=9 ttl=64 time=0.211 ms --- 192.168.0.1 ping statistics --- 10 packets transmitted, 10 packets received, 0% packet loss round-trip min/avg/max = 0.154/0.506/3.126 ms PM: Syncing filesystems ... done.  ep’s functions are ok, re-do the suspend/resume tests Freezing user space processes ... (elapsed 0.01 seconds) done. -------------------------------end-------------------------------------------- Original Attachment has been moved to: uboot_patch_image.zip Original Attachment has been moved to: 0001-imx-pcie-toggle-bit18-of-grp1-fix-pcie-can-t-exit-L2.patch.zip Original Attachment has been moved to: kernel_patch_image.zip

i.MX Processors Knowledge Base

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