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Secure designs begin with a security model consisting of policies, an understanding of the threat landscape and the methods used to enforce physical and logical security. To protect firmware execution given today’s threat landscape, there must be a policy to only allow execution of authenticated firmware. The methods used to enforce this policy rely on MCU security technology to create a protected boot flow. The boot firmware can contain public key cryptography to authenticate application code. In addition to these components integrated in the end device, there are tools and steps that must be taken in the manufacturing environment using manufacturing hardware for code signing and host programs for provisioning. Join this session to explore the design and implementation of a secure boot by making use of the Arm mbed TLS open source software and protect against firmware attacks.
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Learn how to create a secure / non-secure application and debug on a secure Cortex-M33 NXP device.
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Learn about using NXP’s high-performance line of Arm® microprocessors for real-time industrial control applications. The Open Industrial Linux® SDK provides multiple levels of real-time performance, and provides support for Ethernet Time-Sensitive Networking (TSN).
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This presentation provides an overview of the new toolchain to support the S32 platform of MCUs and application processors, this includes an IDE with new project generation, extensive collateral for ease of use and getting started as well as the next-generation Debugger tools, a new Flash tool specifically design for the S32 platform, the S32 configuration tool plus numerous software products integrated into the toolchain for ease of customer use.
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This class will teach you how to spin a BLDC, PMSM or ACIM motor with KMS. You do not need prior motor control experience. You will use the KMS GUI to do motor tuning and MCUXpresso IDE to develop a stand-alone motor control project. Bring your own motor and we will test it with KMS. With your registration please indicate the voltage and max current of your motor.
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With its broad portfolio, NXP is uniquely positioned to propose a full system allowing a scalability from NCAP to L4/L5 autonomous driving. To address such scalability, NXP has faced some challenging decisions about the system partitioning, performance, safety decomposition, AI Acceleration and Programming language. All these challenges will be addressed during the session.
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NXP recently announced its first Azure Sphere-certified crossover applications processor chip, the i.MX 8ULP-CS SoloLite with Azure Sphere, and plans to build additional Azure Sphere-certified chips as part of the NXP i.MX 9 series. Join this tech talk to learn about Azure Sphere and what it means to have a highly secured solution from the hardware to the cloud. We’ll discuss the specific challenges of building and securing connected devices and what sets the i.MX 8ULP-CS apart. We’ll dig into the four components of Azure Sphere, all of which are included with the i.MX 8ULP-CS: Microsoft Pluton on NXP EdgeLock™ secure enclave for a secured hardware root of trust, the secured Azure Sphere OS, the cloud-based Azure Sphere Security Service, and the ongoing OS updates and security improvements supported by Microsoft experts for the lifetime of the device. Presenters: Sudhanva Huruli, Program Manager, Azure Sphere Naama Bak, Business Development and IoT Security, NXP Semiconductors
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Hands-on class diving into advanced debugging and trace features featured in MCUXpresso IDE.
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In-vehicle wireless charging solutions portfolio overview, automotive grade hardware and software offerings, market success stories, technical description of charging deliver and control, foreign object detection, NFC and AUTOSAR integration, and special considerations for in-vehicle operation.
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This class will provide an overview of the i.MX RT series, key peripheral, including a demo using the i.MX RT EVK.
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Learn about NXP's secured IoT Gateway platform with sensor fusion, local and cloud analytic. IoT data aggregation, sensor fusion and analytic processes are run in VMs providing VM isolation advantage. IoT processes can also run in Virtualized Network Functions (VnF) that can run as service chains across end-to-end virtualized network equipment.
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DDR4 (and beyond) dramatically increased the complexity of DDR configuration - even after simulation. More importantly, knowing the right parameters for DDR can make or break the performance of your product. Learn how to configure, optimize and validate DDR functionality directly on your board. Understand the tools and techniquest to obtain the data eye margins, reduce the time for DDR board bring-up and functional validation from weeks to hours.
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Introduction to A100x secure authenticator, authentication protocols, what to look for in security IC, and potential use cases.
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Introduction to i.MX RT products and automotive qualified variants for multimedia applications requiring real time processing and low bill of materials.
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Explores the fast-growing Automotive Gateway market, identifying key use cases and requirements, and how gateways will evolve over the next decade.
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Along with industry leading performance and integration, the i.MX RT crossover processor family integrates strong security protections. With the latest NXP software and tools, every design can integrate boot authentication and encrypted execution. Join this session to use the MCUXpresso Tools to protect your design. Learn about the threats and attacks that can be mitigated for every embedded design.
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Join this session to understand the breakthrough security features integrated in the recently launched LPC5500 MCU Family. Along with Arm® TrustZone® technology the LPC5500 SRAM PUF based key management makes security easy to use and easy to deploy. This session will start off by introducing the scope of securing a smart connected device. It will explain the need for addressing device life cycle in a scalable way that is easy to use and easy to deploy. Then it will detail the protected key management achievable when using LPC5500 with MCUXpresso Software & Tools.
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