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Hello everyone, SEGGER's Real Time Transfer (RTT) is the new technology for interactive user I/O in embedded applications. It combines the advantages of SWO and semihosting at very high performance. Bi-directional communication with the target application Very high transfer speed without affecting real-time behavior Uses debug channel for communication No additional hardware or pin on target required Supported by any J-Link model Supported by ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 and Renesas RX100/200/600 Complete implementation code providing functionality and freedom Here, I'd like to share you the SEGGER RTT porting project on S32K144 as attached. SW requirements: S32DS for ARM v2.2 IDE + S32K1xx SDK RTM 3.0 HW requirements: S32K144-EVB  + J-LINK debugger   For SEGGER RTT, you can refer to: About Real-Time Transfer: https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/   RTT SEGGER Wiki: https://wiki.segger.com/RTT#SEGGER_RTT_TerminalOut.28.29;   Using Segger Real Time Terminal (RTT) with Eclipse: https://mcuoneclipse.com/2015/07/07/using-segger-real-time-terminal-rtt-with-eclipse/   Hope this project can help you, and enjoy the RTT! Best regard, Enwei Hu.
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I write a doc and a demo about LPUART hardware flow control, runs on s32k144 evb board with RTM 3.0.0, the flow control function work normally. If you have any question please contact me. 
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           The hardware of this routine is based on S32K142EVB, the IDE is S32_Design_Studio for ARM 2018.R1, SDK version is S32K1xx_RTM_3.0.0, PTB12 is used to simulate Hall pulse output,PTC12 and PTC13 are buttons to change the flip frequency of PTB12 port, and PTB13 is used as the input capture port. When using the demo program in this article, you need to connect PTB12 and PTB13 ports.   Here we assume that we are using a brushed DC motor!   1.The Hall sensor       The Hall sensor is a magnetic induction sensor. The magnetic ring and the Hall element form an induction combination. The magnetic ring rotates with the rotor. The Hall induction magnetic ring rotates with the rotor. , 3-pole pairs, 4-pole pairs, etc., each pair of poles is divided into two levels of N.S. A pair of magnetic poles outputs one pulse signal, and multiple magnetic poles output multiple pulse signals. The number of magnetic pole stages determines the number of pulse signals. , the higher the accuracy.   Hall sensor 2.The relationship between the motor magnetic ring series and the output Hall waveform 5 pole pairs 3.Determination of motor rotation direction         The direction of the motor is judged by the phase difference of the two Hall signals. As shown in the figure below, the phase of Sensor A is ahead of Sensor B, so it can be considered that the current rotation direction of the motor is clockwise.   4.Calculation of motor speed         The speed of the motor can be calculated by the pulse width of the pulse, and the number of revolutions of the motor can be calculated by the number of pulses. Assuming that the Hall magnetic ring of the motor has 5 pairs of poles, it means that there are five pulses in one revolution of the motor, and the speed of the motor = 60 / (t1 * 5) rev/min. The number of pulses can be obtained by the edge capture function of the FTM. Motor speed and stroke         Assuming that the clock of the FTM is 2MHz, then it takes 1/2000000 seconds for the counter to add 1. Since the unit of the motor speed is rpm, the calculation formula of the motor speed is : -> Motor Speed = 60 / (5 * a* (1 / 2000000))         In this formula, '5' is the number of pole pairs of the magnetic ring, and 'a' is the difference of the counter corresponding to the falling edge of two consecutive pules.         Let’s do a test, the square wave in the below figure is the outputs of PTB12, and the output pulse period is 32.1ms. Then the time required for the motor to rotate once should be:32.1ms *5 = 160.5ms, then the speed of the motor should be: 60 * 1000 / 160.5 = 373.83rpm.   PTB2 output square wave          The below picture is directly obtained by the debugger. It can be seen that the speed of the motor at this time is 373, which is not much different from the value measured by the oscilloscope, which is 373.83. This is because I did not use the floating-point calculation result in the program. In summary, we use the input capture function of the FTM module completes the calculation of the motor speed.   debuger monitor results 5.How to calculate the direction of rotation of the motor         Above we calculated the speed of the motor, but did not make judgement on the direction of the rotation of the motor. As mentioned above, the rotation direction of the motor is judged by the phase difference of the two Hall pulse waveforms. Usually, we think of using the timestamp to judge the current state of the phase, so we will enable the two input captures, and then calculate the two Halls timestamp of the falling edge of the pulse.         In fact, there is a simpler method, it only needs to read the high and low state of the other Hall pulse level when the falling edge of one hall pulse is interrupted. In short, we only need to enable one input capture, and the other to be used as a GPIO port.
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Greetings, if you want to use the open source EmbSysRegView plugin in your Eclipse environment: this article describes how to add the S32K CMSIS-SVD files to it: Adding CMSIS-SVD Files to EmbSysRegView 0.2.6.r192 and Eclipse Happy SVDing 🙂 Erich
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Audio Video Bridging(AVB) is a protocol for the transport of audio and video streams over Ethernet-based networks, which makes it possible to deliver high volumes of data in real-time to multiple destinations with very low latency. This reference design board demonstrates the usage for AVB over S32K148. Alternatively, it can be an S32K148 evaluation board of 100pin version besides S32K148EVB-Q144 and S32K148EVB-Q176. Below shows the board layout, diagram, and main features. Figure 1. S32K148AVB-RDB Layout   S32K148AVB-RDB Diagram(Rev B) Figure 2. S32K148AVB-RDB Diagram S32K148AVB-RDB Features Figure 3. S32K148AVB-RDB Features In terms of the software, we provide several examples to show the AVB/TSN usages and other applications. The avb_listener_talker project is the main example which implements most features and demonstrates by connecting 2 AVB boards by Ethernet cable.   Figure 4. S32K148AVB-RDB Code Examples Below software stack and middleware are implemented. ✓ RTOS: FreeRTOS ✓ Peripherial Driver: SDK RTM 3.0 (Work with Processer Expert) ✓ AVB Stream: RTM 1.0 ✓ AVB AudioIf: RTM 1.0 ✓ gPTP Stack Version: 1.3.4 ✓ Lwip Stack Version: 2.1.2 •Note: Even though we did a lot of tests, it’s still the customer’s responsibility to ensure the total quality by themselves when it’s integrated into a real application project, all the sample codes and user guide documentation are just reference for the customer. •Note: We do not have an FCC or CE certificate for this board.   Now we have 50 pcs boards available in Chongqing, China. For applying for the board, please contact NXP sales or GPIS marketing.  Since the AVB stack is not free of use, for accessing the code please contact NXP sales or GPIS marketing. For technical discussion, please contact Jeremy.he@nxp.com or Frankie.zeng@nxp.com.  
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*******************************************************************************  The purpose of this demo application is to present a usage of the  ADC_SAR and BCTU IP Driver for the S32K3xx MCU.  The example uses the PIT0 trigger to trigger BCTU conversion list to  perform parallel conversions on ADC0/ADC1. Three ADC channels  are selected to be converted on each ADC:  ADC0: S8 , P0, S8  ADC1: S10, S13, S17  Converted results from BCTU FIFO are moved by DMA into result array.  ADC channel S10 is connected to board's potentiometer, and converted value is  used to dim board's LED.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: Lauterbach * Target: internal_FLASH ********************************************************************************
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You can find here a reference code for a march c software test in order to test RAM memories
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******************************************************************************** * Detailed Description: * * Example shows possible setting for PWM duty cycle update using DMA. * FTM0 ch0 is set to Edge aligned mode with 20KHz period. * Initialization trigger is routed back to HW trigger 1 using TRGMUX, so this HW * trigger can be used for CnV synchronization. * DMA on FTM0 ch0 is enabled (on ch0 CHF flag) and DMA ch0 configured to update C0V * from duty cycle variable. * NOte CHF is not set for 0% and 100% duty cycle, thus no DMA trigger is generated. * * Green LED is dimming as duty is changing. * * ------------------------------------------------------------------------------ * Test HW: S32K118EVB-Q64 * MCU: PS32K118LAMLH 0N97V * Compiler: S32DS.ARM.2.2 * SDK release: S32SDK_S32K1xx_RTM_3.0.3 * Debugger: Lauterbach, OpenSDA * Target: internal_FLASH * ******************************************************************************** Revision History: 1.0 Sep-16-2021 Petr Stancik Initial Version *******************************************************************************/
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Hello,      NXP does a big change on document structure.     Generally, you can find pin assignment table, interrupt mapping and memory map table in RM. But now, these information change to Excel files and attached in RM.   For example on S32K.    You will find the words in RM, like 'For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual.'    Then, please go to attachment tab of your PDF file viewer, like Adobe Acrobat Reader DC.     These steps are also fit for MPC57xx , S32R family. Cheers! Oliver
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*******************************************************************************  The purpose of this demo application is to present a usage of the  UART IP Driver for the S32K3xx MCU.  The example uses LPUART6 for transmit & receive five bytes using the DMA.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    
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【RTD400 MCAL 3】 K312 MCU clock system configuration 1. Abstract This document is talking about how to configure the clock system in the MCU of the K3 chip MCAL. This topic was always disdainful to talk about when I was doing LLD before, because the clock system of K3 is too simple, with internal fast and slow clock sources, external fast and slow clock sources, a PLL multiplier, and then various core peripherals to share. K3's RM even made a few options to frame the rules. From the perspective of LLD, especially the perspective of S32DS CT configuration, it is even more concise and clear. Here is a CT picture to show it:   Fig 1     Fig 2 With such a clock system, you can generate code with just a few taps and pokes. However, LLD is too free, and MCAL often encounters problems. Therefore, I decided to spend some time to understand the entire clock system of this MCAL MCU. This article takes K312 as an example to explain. Other K3 series are similar. 2. Clock system theory and configuration 2.1 K312 clock system From the clock chapter of RM, you can see the whole system block diagram:     Fig 3 This block diagram clearly shows the situation of each part. There are four clock sources: Internal fast clock FIRC: 48MHz, +/-5% error, maximum startup time 25us Internal slow clock SIRC: 32KHz, +/-10% error, maximum startup time 3ms External fast clock FXOSC: 8-40MHz, startup stabilization time FXOSC_CTRL[EOCV] × 128 External slow clock SXOSC: 32.768KHz, startup stabilization time SXOSC_CTRL[EOCV] x 128 One PLL: input 8-40MHZ, VOC output 640M-1280Mhz, PLL_PHIn_CLK output 25-480MHz. MUX_0: Output CORE_CLK, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE_CLK, DCM_CLK MUX_1: Output system timer STM0_CLK MUX_3: Output FLEXCAN0-2 clock MUX_4: Output FLEXCAN3-5 clock MUX_5: Output CLKOUT_STANDBY MUX_6: Output CLKOUT_RUN MUX_11: Output TRACE_CLK RTC_CLK: RTC clock 2.1.1 PLL From the PLL perspective, we need to know which values ​​the frequency multiplier is related to, which can be calculated using the following formula:     Fig 4 If it is an integer, the red box in the above figure is the common method, and this article will also use the above method to configure. PLL_PHI is the clock output by the final PLL, which is provided to the MC corresponding to other MUXs for selection. 2.1.2 MUX_0 System The MUX_0 system with details can be seen from RM:     Fig 5 As you can see, the clock source of MUX_0 can be two types: PLL or internal FIRC. Then the core clock can be generated later, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE_CLK, DCM_CLK. So what is the specific frequency of the generated clock? In principle, it can meet the maximum clock corresponding to each module, but the K3 series also makes some option recommendations. For example, K312 recommends using option B mode when RUN, especially the HSE clock, which usually needs to strictly meet the option recommendation. 2.1.3 MUX_6 Clock output In order to check the corresponding clock situation in the chip, the corresponding clock can be output through the CLKOUT pin. The CLKOUT pin can correspond to the selection of multiple clock sources. The specific situation is as follows:     Fig 6 The yellow content in the figure is what K312's CLKOUT_RUN can support. After the clock is configured, the corresponding clock will be selected to test whether the output is consistent with the configuration. 2.1.4 option B Recommended Solution In this article, K312 will configure the clock of option B in EB.     Fig 7 2.2 EB configuration        First, create a new K312 EB project. For the specific creation method, please refer to the previous article: [S32K3 Tools Part] How to port RTD's existing MCAL demo to other K3 chips This article will focus on the clock configuration corresponding to the MCU module based on RTD400 MCAL. For MCU configuration, two documents need to be consulted as reference books: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Mcu_TS_T40D34M40I0R0\doc: RTD_MCU_UM.pdf and RTD_MCU_IM.pdf If you don’t know how to configure, just follow the default values ​​recommended by the document. The following figure is an overview of the MCU. The main configured modules have the following three components: General, McuClockSettingConfig, McuModeSettingConf     Fig 8 2.2.1 General configuration In addition to Figure 8, you need to turn on the internal and external fast and slow clock control and PLL control, and add the corresponding API, as well as the crystal oscillator frequency. If this is not turned on, the corresponding configuration later will not be able to be configured.     Fig 9 2.2.2 McuClockSettingConfig configuration        This is the core area of ​​MCU clock configuration, which includes clock source, PLL, and various MUX conditions. First, you need to add a clock configuration:     Fig 10 Click in and there will be detailed configuration:     Fig 11 There are 17 items in total. You can keep the default configuration for options 1 and 6. Since the board does not connect to the external slow crystal oscillator 5, it is not configured. The rest should be configured according to the actual situation. The following explains them one by one: 2.2.2.1 McuFIRC configuration    Internal fast clock, 48MHz:     Fig 12 2.2.2.2 McuSIRC configuration Internal slow clock 32Khz     Fig 13 2.2.2.3 McuFXOSC configuration External crystal oscillator 16MHZ, fill in according to the actual connection situation.     Fig 14 2.2.2.4 McuCgm0ClockMux0 configuration Mux0 configuration, here are configured core clock, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE, DCM_CLK, is to meet the optionB requirements, and the clock comes from PLL_PHI0_CLK. When actually configuring, first configure the PLL clock to output the correct PLL_PHI0_CLK, PLL_PHI1_CLK clock.     Fig 15 2.2.2.5 McuCgm0ClockMux1 configuration     Fig 16 It can be configured according to the clock source required by the actual module. 2.2.2.6 McuCgm0ClockMux3 configuration Configure the clock source of the FLEXCAN0-2 module:     Fig 17 2.2.2.7 McuCgm0ClockMux4 configuration Configure the clock source of the FLEXCAN3-5 module:     Fig 18 2.2.2.8 McuCgm0ClockMux5 configuration Configure the clock source of the CLKOUT_STANBY module:     Fig 19 2.2.2.9 McuCgm0ClockMux6 configuration Configure the clock source of the CLKOUT_RUN module     Fig 20 2.2.2.10 McuCgm0ClockMux11 configuration Configure the clock source of the TRACE_CLK module     Fig 21 2.2.2.11 McuRtcClockSelect configuration Configure the clock source of the RTC module     Fig 22 2.2.2.12 McuPLL configuration Configure the clock source of the PLL module     Fig 23 2.2.2.13 McuClockReferencePoint configuration Configure the reference clock and the clock source selection interface of the peripheral modules.     Fig 24 At this point, the clock configuration is complete. For verification, you can use the CLKOUT_RUN output to output the corresponding clock to pin PTD10 for viewing. 2.2.3 McuModeSettingConf  configuration In Mcu's McuModeSettingConf->McuPeripheral, you need to turn on the peripherals you want to use:     Fig 25 2.2.4 PORT  configuration Because the internal clock needs to be output to CLKOUT_RUN, K312's PTD10 MSCR106 is checked, so the PORT pin is added as follows:     Fig 26 3. Test Result Next, on the S32K312-EVB board, we modify the clock source of EB's CLKOUT_RUN to test whether the clock matches the configuration. Commonly used MCU-related drivers are as follows:     Fig 27 The calling sequence of system startup MCU initialization is as follows: 1). Mcu_Init() 2). Mcu_InitClock() 3). Mcu_GetPllStatus() - Till PLL is locked. 4). Mcu_DistributePllClock() 5). Mcu_SetMode() 6). Mcu_InitRamSection() - If required The corresponding main code is as follows: #include "Mcu.h" #include "Mcu_Cfg.h" #include "Port.h" #include "Dio.h" #include "Port_Cfg.h" #include "Platform.h" void TestDelay(uint32 delay); void TestDelay(uint32 delay) { static volatile uint32 DelayTimer = 0; while(DelayTimer < delay) { DelayTimer++; } DelayTimer = 0; } /** * @brief Main function of the example * @details Initialize the used drivers and uses the Icu * and Dio drivers to toggle a LED on a push button */ int main(void) { uint8 count = 0U; uint8 u8TimeOut = 100U; /* Initialize the Mcu driver */ #if (MCU_PRECOMPILE_SUPPORT == STD_ON) Mcu_Init(NULL_PTR); #elif (MCU_PRECOMPILE_SUPPORT == STD_OFF) Mcu_Init(&Mcu_Config_VS_0); #endif /* (MCU_PRECOMPILE_SUPPORT == STD_ON) */ /* Initialize the clock tree and apply PLL as system clock */ Mcu_InitClock(McuClockSettingConfig_0); #if (MCU_NO_PLL == STD_OFF) while ( MCU_PLL_LOCKED != Mcu_GetPllStatus() ) { } Mcu_DistributePllClock(); #endif /* Apply a mode configuration */ Mcu_SetMode(McuModeSettingConf_0); /* Initialize all pins using the Port driver */ Port_Init(NULL_PTR); /* Initialize Platform driver */ Platform_Init(NULL_PTR); while (count++ < 10) { Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q172, STD_HIGH); Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q257, STD_HIGH); TestDelay(5000000); Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q172, STD_LOW); Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q257, STD_LOW); TestDelay(5000000); } // Exit_Example(TRUE); return (0U); } #ifdef __cplusplus } #endif 3.1 CLKOUT FIRC_CLK DIV2     Fig 28 It can be seen that the original 48Mhz clock of FIRC is divided by 2 and the clock waveform of 24Mhz is obtained, which is correct! 3.2 CLKOUT SIRC_CLK DIV2     Fig 29 It can be seen that the original 32Khz clock of SIRC is divided by 2 and the clock waveform of 16khz is obtained, which is correct! 3.3 CLKOUT FXOSC_CLK DIV10     Fig 30 It can be seen that the original 16Mhz clock of FXOSC is divided by 10 and the clock waveform of 1.6Mhz is obtained. 3.4 CLKOUT PLLPH0 CLK DIV10     Fig 31 It can be seen that the original 120Mhz clock of PLLPH0 is divided by 10 and the 12Mhz clock waveform is obtained, which is correct. 3.5 CLKOUT CORE CLK DIV10     Fig 32 It can be seen that the original 120Mhz clock of CORE is divided by 10 and the 12Mhz clock waveform is obtained, which is correct. 3.6 CLKOUT PLLPH1 CLK DIV4     Fig 33 It can be seen that the original 48Mhz clock of PLLPH1 is divided by 4 and the 12Mhz clock waveform is obtained. 3.7 CLKOUT HSE CLK DIV10     Fig 34 It can be seen that the original 60Mhz clock of HSE is divided by 10 and the clock waveform of 6Mhz is obtained, which is correct. 3.8 CLKOUT AIPS_PLAT CLK DIV10     Fig 35 It can be seen that the original 60Mhz clock of AIPS_PLAT_CLK is divided by 10 and the clock waveform of 6Mhz is obtained, which is correct. 3.9 CLKOUT AIPS_SLOW CLK DIV10     Fig 36 It can be seen that the original 30Mhz clock of AIPS_SLOW_CLK is divided by 10 and the clock waveform of 3Mhz is obtained, which is correct.  
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1 Abstract After learning S32K3 PWM and have written some MCAL codes, this is the first MCAL article record starts with the combination of K344 EMIOS+ICU+TRIMUX+LCU, which can involve comprehensive configurations such as PORT, DIO, EMIOS, interrupt ICU, TRIGMUX, LCU, etc. The board platform is still based on NXP official S32K344EVB, RTD400, and the function is: use two channels of EMIOS0 and one channel of EMIOS1. After one channel of EMIOS 0 outputs PWM, it connects LCU through TRIGUMX to generate a set of complementary PWM, and the other channel can realize hardware interrupt control of PWM duty cycle through SW5 PT26 button. One channel of EMIOS1 is directly connected to the PTA29 onboard red light, and the brightness is gradually changed by changing the PWM duty cycle, and then the breathing light effect is realized by directly changing the on and off cycle. At the same time, when the PWM turns off the red light, the onboard green light is turned on through DIO, and when the PWM turns on the red light, the DIO turns off the onboard green light. Text description is always less intuitive than graphic description, so here is the picture:      Fig 1 2. Function realization This article is based on porting the MCAL code to the S32DS demo. Then, on the S32DS platform, MCAL related modules are configured through EB, and then compiled and downloaded for simulation through S32DS. Of course, if you like the command line mode, you can directly use the xmd file configured by EB, and then compile with VScode. The process is also very simple. This article will not go into details about the command line method.     2.1 Hardware and software platform Board:S32K344EVB,also can use other K3 boards. IDE:S32DS3.5 RTD: K344 RTD 400 MCAL tool: EBtresos Studio 29.0 2.2 Software control process Before talking about the specific MCAL configuration, here is the software flow chart of the functions in this article:                                                                             Fig 2 Here you can see that the default situation is the one configured through MCAL, and then the PWM frequency is also modified in the code, and the PWM duty cycle is modified by keystrokes and loop delays. 2.3 Resource Allocation Overview The hardware resources and functions used in this article are listed as follows: Fig 3 The configuration of emios related buses is as follows: Fig 4 It should be noted here that for the master bus and bus mode in MCL emios, it is necessary to select the appropriate PWM mode and counter bus in the PWM module, otherwise either the configuration will be wrong or the correct PWM waveform cannot be generated. From the official S32K3 RM, you can check the clock channel and bus type: Fig 5 For example, if EMIOS_CH23 is selected in PWM0, then this bus corresponds to bus A, and this clock can be used for all channels, so PWM0 is CH12 and can use Bus A. CH22 corresponds to bus F, and this clock can also be used for all channels, so it is no problem to select Bus F for PWM1 CH4. CH0 corresponds to bus B, and this clock corresponds to channels 0-7, so it can also be used for PWM2 is CH2. When selecting the counter bus clock source for your EMIOS channel, you must consider the channel coverage of the counter bus. In addition to the selection of the counter bus, there is also the PWM mode selection, which is easier to handle. For clock counting up, select OPWMB, and for clock counting up and down, select OPWMCB center-aligned PWM.      In actual use, the mode selection is usually determined based on one's own PWM requirements, and then based on the following RM table: Fig 6 You can find the channel types that the corresponding mode can support, and then select the corresponding channel, counter bus, etc. according to the channel type in Figure 5. With these basic knowledge, we can directly enter the EB configuration. 2.4 EB configuration    Here we list all the modules used in EB tresos related to this article, and focus on the modules that require specific configuration. Fig 7 2.4.1 Dio module The DioPort interface needs to be configured. The main purpose is to configure PTA30, onboard green light, select DioPort Id=1, Dio Channel Id=14. The rules for DioPortId and Dio Channel Id are as follows:     Channel = DioChannelId + DioPortId∗16 For S32K3X4 derivatives – Port AL=0 – Port AH=1 – Port BL=2 – Port BH=3 – Port CL=4 – Port CH=5 – Port DL=6 – Port DH=7 – Port EL=8 – Port EH=9 – Port FL=10 – Port FH=11 – Port GL=12 – Port GH=13 PTA30=>30=DioChannelId(14)+DioPortId*16 2.4.2 Icu module First, configure IcuSiul2, the goal is to enable the input interrupt of onboard SW5, PTB26. PTB26 corresponds to EIRQ[13], Then, the corresponding interrupt situation is as follows: Fig 8 Fig 9 (1) Icu->IcuSiul2->IcuSiul2Channels:13 (2) Icu->IcuChannel configuration is: Fig 10 Select IcuChannelRef as the previously configured IcuSiul2Channels, and add the interrupt notification function: User_EdgeDetect, note that this function is the name of the user interrupt processing function that needs to be added in the code.    (3)Icu->IcuHwInterruptConfigList-> ICU Peripheral ISR Name: SIUL2_0_IRQ_CH_13,IcuIsrEnable enable 2.4.3 Mcl module This module is mainly used to configure emios counting clock, trgmux, and LCU configuration. (1)Mcl->Trgmux Logic Instance->Hardware Instance: TRGMUX_IP_HW_INST_0   (2) Mcl->Trgmux Logic Group: Fig 11 The main purpose is to connect PWM1 Emios0_ch4 to LCU0_IN0 through Trigmux. (3)Mcl->LCU Configuration Here is the configuration of the LCU module. The main function is to configure the logic input and logic output. There is one input IN0 and two outputs OUT0 and OUT1. Fig 12 Fig 13 Fig 14 OUTPUT0  value is 0XAAAA=43690, OUTPUT1 value is 0X5555=21845 The purpose of this is to generate a pair of complementary PWMs from the input PWM. Fig 15 (4)Mcl->Emios Common Add two Emios, EMIOS_0 and EMIOS_1, which means two EMIOS are used. EMIOS0 is configured with two master bus channels: CH_22 and CH_0, and has different mode types, counting up and down and counting up. EMIOS1 is configured with one master bus channel: CH_23, counting up Corresponding to Figure 4. Fig 16 Fig 17 Note that the channel here is not the actual PWM output channel, but the counter bus channel of the PWM channel, which has the ability to provide clocks. 2.4.4 Mcu module   This module is the basis for the entire MCU to configure the clock. When using the default setting of the original RTD PWM demo, there is only one point that needs attention Mcu->McuClockSettingConfig_0->McuClockReferencePoint->McuClockReferencePoint_0->core clock 48MHZ. This clock is the source of the EMIOS clock. With the clock source, it is not difficult to calculate the actual PWM frequency according to the set period. For example, if a 1Khz PWM is required, you can configure period=48M/1K=48000 2.4.5 Platform module Platform->Interrupt Controller->IntCtrlConfig0, enable SIUL_1_IRQn, and add Handler as: SIUL2_EXT_IRQ_8_15_ISR Note that this SIUL2_EXT_IRQ_8_15_ISR is not written randomly, but must correspond to the one in Siul2_Icu_Ip_Irq.c, otherwise an error will be reported. Fig18 Different interrupts have different interrupt service functions. You need to find the function name defined in the code and fill it into EB. EB configuration is as follows: Fig 19 2.4.6 Port module The configuration of 8 pins is as follows: Fig 20 As you can see, there are 3 main EMIOS PWMs, one input interrupt, one output GPIO, and two output LCU complementary PWMs. 2.4.7 Pwm module Mcl configures the counter clock channel of EMIOS. The PWM channels to be output need to be configured in the Pwm module and linked to the MCU clock source and the emios counter bus source in Mcl. (1) Pwm->PwmEmios Add two groups for the corresponding EMIOS modules. For example, this article uses EMIOS0 and EMIOS1, so two need to be added: Fig 21 For PwmEmios_1, there is one channel, and the configuration is as follows: Fig 22 PwmEmiosBusRef: /Mcl/Mcl/MclConfig/EmiosCommon_1/EmiosMclMasterBus_0 Fig 23 As you can see, the busRef of PwmEmios_1 here is Emios_ch_23 in Mcl, that is, BusA. That is to say, the bus reference clock used by EMIOS1_CH12 comes from EMIOS1_CH23, that is, Bus A. There are two channels configured in PwmEmios_0, and the configuration is as follows: Fig 24 Fig 25 The bus reference clock used by EMIOS0_CH4 comes from EMIOS0_CH22, which is Bus F. Another EMIOS0 channel: Fig 26 Fig 27 The bus reference clock used by EMIOS0_CH2 comes from EMIOS0_CH0, that is, Bus B, so select Bus BCDE. At this point, we can clearly understand the relationship between the real PWM output channel and the internal MCL Emios counter bus channel. (2)Pwm->PwmEmios With the specific information of PWM configured above, we can directly configure the PWM channels. There are three channels in total: PWM0, PWM1, PWM2, which are also the flags needed in the code. Fig 28 2.5 main code   #include "Pwm.h" #include "Mcu.h" #include "Port.h" #include "Mcl.h" #include "Platform.h" #include "Dio.h" #include "Icu.h" //#include "check_example.h" #define NUM_BLINK_LED (uint32)10U #define DELAY_TIMER (uint32)5000000U #define MCL_EMIOS_1_CH_23 (uint16)279U #define MCL_EMIOS_0_CH_22 (uint16)22U Mcl_LcuSyncOutputValueType PWM_OutputList[2]; volatile uint8 UserCountIrqCH0; void TestDelay(uint32 delay); void TestDelay(uint32 delay) { static volatile uint32 DelayTimer = 0; while(DelayTimer<delay) { DelayTimer++; } DelayTimer=0; } void User_EdgeDetect(void) { /* increment IRQ counter */ UserCountIrqCH0++; if(UserCountIrqCH0 % 2 == 0) { Pwm_SetDutyCycle(PwmChannel_2, 0X6000); } else { Pwm_SetDutyCycle(PwmChannel_2, 0X2000); } } int main(void) { uint8 num_blink = 0U, i = 0; uint16 duty_cnt = 0; UserCountIrqCH0 = 0U; /* Initialize the Mcu driver */ Mcu_Init(&Mcu_Config_VS_0); /* Initialize the clock tree */ Mcu_InitClock(McuClockSettingConfig_0); /* Apply a mode configuration */ Mcu_SetMode(McuModeSettingConf_0); Platform_Init(NULL_PTR); /* Initialize all pins using the Port driver */ Port_Init(&Port_Config_VS_0); /* Initialize Mcl driver */ Mcl_Init(&Mcl_Config_VS_0); /* Initialize the Icu driver */ Icu_Init(NULL_PTR); Icu_EnableEdgeDetection(IcuChannel_0); Icu_EnableNotification(IcuChannel_0); /* Initialize Pwm driver , after that Led on*/ Pwm_Init(&Pwm_Config_VS_0); /* PTA29 duty cycle is 50% */ Pwm_SetDutyCycle(PwmChannel_0, 0X4000); // PTB16,pwm1 , emios0_ch4, use trigmux LCU output 2 Complementarity PWM Mcl_LcuSyncOutputValueType lcuEnable[2U]; lcuEnable[0].LogicOutputId = 0; lcuEnable[0].Value = 1U; lcuEnable[1].LogicOutputId = 1; lcuEnable[1].Value = 1U; Mcl_SetLcuSyncOutputEnable(lcuEnable, 2U); TestDelay(DELAY_TIMER); /* Set new period for all channels used external counter bus */ Mcl_Emios_SetCounterBusPeriod(MCL_EMIOS_1_CH_23, 4800, FALSE); // pwmchannel_0 10Khz Mcl_Emios_SetCounterBusPeriod(MCL_EMIOS_0_CH_22, 1200, FALSE);// for PwmChannel_1, 20Khz // PWM0: 10kHZ //PWM1: 20KHZ //PWM2:1KHZ // PTA29 10kHZ /* PTA29 duty cycle is 50% */ Pwm_SetDutyCycle(PwmChannel_0, 0X4000); /* Setup new duty cycle to the pin*/ Pwm_SetDutyCycle(PwmChannel_1, 0x4000); for(i=0; i <= 10; i++) { duty_cnt = i * 0x800; Pwm_SetDutyCycle(PwmChannel_0, duty_cnt); TestDelay(DELAY_TIMER); } /* Using duty cycle 0% and 100% to Blink LED */ while(1) { /* pwm1 when duty cycle is 75% */ Pwm_SetDutyCycle(PwmChannel_1, 0X6000); //Led off Pwm_SetDutyCycle(PwmChannel_0, 0X0000); //red off Dio_WriteChannel(DioConf_DioChannel_Digital_ledgreenPTA30, STD_HIGH); //green on TestDelay(DELAY_TIMER); /* pwm 1 when duty cycle is 25% */ Pwm_SetDutyCycle(PwmChannel_1, 0X2000); //Led ON Dio_WriteChannel(DioConf_DioChannel_Digital_ledgreenPTA30, STD_LOW); //Green OFF Pwm_SetDutyCycle(PwmChannel_0, 0X8000); //RED ON TestDelay(DELAY_TIMER); num_blink++; } /* De-Initialize Pwm driver */ Pwm_DeInit(); //Exit_Example(TRUE); return 0U; }   3. Test Result After power-on, the onboard red light flashes, then gradually turns bright from off, and flashes alternately with the green light. Test PWM1 PTB16: EMIOS0_CH4, the waveform is 20Khz after stabilization, and the duty cycle changes alternately between 25% and 75%. PWM2 PTB14: EMIOS0_CH2, after stabilization, the frequency is 1KHZ, and as the onboard SW5 is pressed, the duty cycle changes alternately between 25% and 75%. Test PTD3, PTD2, it can be seen that it is a pair of complementary waveforms, and the frequency is the same as PTB16, and the duty cycle change rule is also the same. It can be seen that the key interrupt, 3 main PWM, and 2 LCU PWM in this article are already working. Fig 29 Fig 30  
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*******************************************************************************  The purpose of this demo application is to present a usage of the LPI2C-0 as MASTER and LPI2C-1 SLave, using DMA for TX & RX for the S32K3xx MCU.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************
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******************************************************************************* The purpose of this demo application is to place variables in DTCM memory for the S32K3xx MCU.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** ZERO table : is for bss segment variables :  contains RAM start & end address of BSS section which need to be initialized with ZER). Init_table : is for DATA segment variables : contains RAM start address of DATA section & START & end address of ROM address where the initialization values of the variables are stored.   Startup file startup_cm7.s call function init_data_bss() . Inside this function uses these section :-- Variables declared :-- Linker file changes :--   startup_cm7.s file changes :--   MAP file :--     Debug window results :--         https://www.kernel.org/doc/html/v5.9/arm/tcm.html   Due to being embedded inside the CPU, the TCM has a Harvard-architecture, so there is an ITCM (instruction TCM) and a DTCM (data TCM).  The DTCM can not contain any instructions, but the ITCM can actually contain data.   TCM is used for a few things: FIQ and other interrupt handlers that need deterministic timing and cannot wait for cache misses. Idle loops where all external RAM is set to self-refresh retention mode, so only on-chip RAM is accessible by the CPU and then we hang inside ITCM waiting for an interrupt. Other operations which implies shutting off or reconfiguring the external RAM controller.  
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********************************************************************************  Detailed Description:  Example shows FlexCAN 0 usage in RUN/VLPR modes using SDK.  CAN bitrate is set to 250bit/s.  MCU enters VLPR mode by pressing SW3 button. CAN std message is sent with data VLPRmode"  MCU exits VLPR to RUN mode when one of following happens:  - CAN std message with RX_MSG_ID is received and MCU is in VLPR  - SW2 button is pressed (PTC12 interrupt). CAN std message is sent with data "RUN mode"  Blue LED is dimming and the rate is different for each power mode due to different  system clock (48Mhz vs 4MHz)  ------------------------------------------------------------------------------  Test HW: S32K116EVB-Q48  MCU: PS32K116LAM 0N96V  Compiler: S32DS.ARM.2.2  SDK release: S32SDK_S32K1xx_RTM_3.0.3  Debugger: Lauterbach, OpenSDA  Target: internal_FLASH ********************************************************************************
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1. Abstract The S32K344 ADC is a SAR ADC with a resolution which can up to 14 bits. It has a variety of software and hardware triggering methods, supports various external trigger sources, and introduces BCTU so that the trigger resources can be externally connected to multi-channel EMIOS and TRIGMUX, adding more ADC trigger sources. This article mainly explains the following ADC software and hardware triggering methods, and provides supporting codes.     Fig 1 It is mainly divided into 5 parts: (1) SW+ADC: software trigger, by adding timer PIT, the software trigger ADC is called regularly to complete channel sampling, and the collected value is printed out through UART printf. (2) SW+BCTU+ADC: software trigger, by adding timer PIT, the software trigger BTCU is called regularly to complete ADC channel sampling, and the collected value is printed out through UART printf. (3) PIT+TRIGMUX+ADC: hardware trigger, connect PIT to ADC through TRIGMUX, trigger ADC channel sampling through PIT hardware, and print the conversion value after the sampling conversion is completed. (4) EMIOS+BCTUHW+ADC: hardware trigger, through EMIOS timing trigger BCTU to complete the corresponding ADC single channel sampling, due to the high sampling rate, only the BCTU sampling value is printed regularly. (5) EMIOS+BCTUHWLIST+ADC: hardware trigger, through EMIOS timing trigger BCTU to complete ADC list channel sampling, due to the high sampling rate, the list channel value sampled by BCTU is printed regularly. 2. ADC SW HW Trigger 2.1 Hardware and software platform SW: RTD400 LLD,S32DS3.5 HW:S32K3X4EVB-T172 2.2 SW+ADC software trigger     In fact, the original ADC demo of RTD400 already has ADC software and BCTU software trigger. This article adds PIT timing software trigger based on this function, and prints it out through UART printf, making it more convenient to check the ADC test value through serial port printing. The block diagram structure of the software triggering ADC in this article is as follows:     Fig 2      The S32K344EVB board has a potentiometer connected to ADC1_S10, PTA11:   Fig 3 Therefore, the software trigger in this section is mainly used to collect ADC1_S10. The UART printing port uses the serial port of the onboard emulator: LPUART6_RX PTA15, LPUART6_TX PTA16, with a baud rate of 115200. For the software trigger demo in this article, the main configuration involves the following modules: (1)Pins:   Fig 4 ADC1_s10: PTA11 is the voltage of the onboard potentiometer to be tested, which is adjustable. PTA29: Connect the onboard D13 red light to test the PIT timer interrupt and enter the flashing state, used as the breathing light of the PIT. PTA16: UART6_TX, used to send the collected ADC value. (2)clocks Used to configure the system clock. You need to pay attention to the UART6 clock source of 40Mhz, the ADC1 clock source of 160Mhz, and the PIT0 clock source of 40Mhz (3)Peripherals Involved peripheral modules Siul2_Port,Siul2_Dio, Pit, Lpuart_Uart, Adc_Sar_Ip, IntCtrl_Ip. Siul2_Port: Add 4 pins ADC PTA11 MSCR 11, RED LED PTA29 MSCR 29, UART6_RX PTA15 MSCR 15, UART6_RX PTA16 MSCR 16. Siul2_Dio: Add the module mainly to allow related API functions to come in, so as to control GPIO pins. Pit: Used to generate 1S timing, the main configuration is as follows:   Fig 5                                                             Fig 6 Lpuart_Uart: Fig 7 Adc_Sar_Ip:   Fig 8                                                                         Fig 9 It should be noted here that ADC calibration prescale and Adc prescaler vale need to meet the following conditions, which can be found on S32K3RM:   Fig 10 Since the clock source of ADC1 is 160MHz, the calibration division is configured as 4 and the conversion division is configured as 2. IntCtrl_Ip:   Fig 11 The purpose is to open the interrupt of PIT and LPUART6, and register the corresponding handler. CT configuration is completed, and the code is generated. Next, move to the main function and add the following code: void AdcEndOfChainNotif1(void) { notif_triggered1 = TRUE; data1 = Adc_Sar_Ip_GetConvData(ADCHWUNIT_1_BOARD_INITPERIPHERALS_INSTANCE, 34); /* Checks the measured ADC data conversion */ // while (ADC_TOLERANCE(data, ADC_BANDGAP)); } void Pit0ch0Notification(void) { toggleLed = 1U; Siul2_Dio_Ip_TogglePins(LED_Q172_PORT, (1<<LED_Q172_PIN)); } int main(void) { StatusType status; uint8 Index; Clock_Ip_StatusType clockStatus; /* Initialize and configure drivers */ clockStatus = Clock_Ip_Init(&Clock_Ip_aClockConfig[0]); while (clockStatus != CLOCK_IP_SUCCESS) { clockStatus = Clock_Ip_Init(&Clock_Ip_aClockConfig[0]); } Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals, g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals); /* set PIT 0 interrupt */ IntCtrl_Ip_Init(&IntCtrlConfig_0); IntCtrl_Ip_EnableIrq(PIT0_IRQn); status = (StatusType) Adc_Sar_Ip_Init(ADCHWUNIT_1_BOARD_INITPERIPHERALS_INSTANCE, &AdcHwUnit_1_BOARD_InitPeripherals); while (status != E_OK); IntCtrl_Ip_InstallHandler(ADC1_IRQn, Adc_Sar_1_Isr, NULL_PTR); IntCtrl_Ip_EnableIrq(ADC1_IRQn); for(Index = 0; Index <= 5; Index++) { status = (StatusType) Adc_Sar_Ip_DoCalibration(ADCHWUNIT_1_BOARD_INITPERIPHERALS_INSTANCE); if(status == E_OK) { break; } } Adc_Sar_Ip_EnableNotifications(ADCHWUNIT_1_BOARD_INITPERIPHERALS_INSTANCE, ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN | ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN); /* Initialize PIT instance 0 - Channel 0 */ Pit_Ip_Init(PIT_INST_0, &PIT_0_InitConfig_PB_BOARD_InitPeripherals); /* Initialize channel 0 */ Pit_Ip_InitChannel(PIT_INST_0, PIT_0_CH_0); /* Enable channel interrupt PIT_0 - CH_0 */ Pit_Ip_EnableChannelInterrupt(PIT_INST_0, CH_0); /* Start channel CH_0 */ Pit_Ip_StartChannel(PIT_INST_0, CH_0, PIT_PERIOD); Lpuart_Uart_Ip_Init(UART_LPUART_INTERNAL_CHANNEL, &Lpuart_Uart_Ip_xHwConfigPB_6_BOARD_INITPERIPHERALS); printf("S32K344 PIT TRIGMUX ADC demo RTD400.\r\n"); while(1) { #if 1 if( toggleLed == 1) { toggleLed = 0; /* Start a SW triggered normal conversion on ADC_SAR */ Adc_Sar_Ip_StartConversion(ADCHWUNIT_1_BOARD_INITPERIPHERALS_INSTANCE, ADC_SAR_IP_CONV_CHAIN_NORMAL); /* Wait for the notification to be triggered and read the data */ while (notif_triggered1 != TRUE); notif_triggered1 = FALSE; printf("ADC1_s10 ch34 data = %d .\r\n", data1); } #endif } } The test results are printed as follows:   Fig 12 This section content supporting code: S32K344_PIT_SW_ADC_RTD400.zip   2.3 SW+BCTU+ADC Software trigger BCTU Based on SW+ADC trigger, add BCTU, and use BCTU software trigger to complete ADC sampling. The block diagram structure is as follows:   Fig 13 This section uses BCTU software to trigger ADC0 sampling. The sampling channel does not actually use external pin input, but collects the bandgap value of ADC0. The software trigger calls the software trigger function through the PIT 1S cycle, and prints the ADC sampling conversion value to UART after completion. In the CT tool, the main modification points are peripherals, adding ADC0 in adc_sar_lp, and configuring it as BCTU trigger.   Fig 14                                                        Fig 15 Here we can see that in Figure 14, the adc ctu mode is: trigger mode. Add the Bctu_Ip module and configure it as follows:   Fig 16 The corresponding selected BCTU channel is 48, which corresponds to the internal bandgap module.   Fig 17 The typical value is 1.2V, so the reference voltage is 5V, and the corresponding 14-bit ADC bandgap expected value is: (2^14)*1.2/5=3932 around. After completing the CT configuration code generation, add the following code in main.c: void AdcEndOfChainNotif(void) { notif_triggered = TRUE; data = Adc_Sar_Ip_GetConvData(ADCHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, ADC_SAR_USED_CH); } void Pit0ch0Notification(void) { toggleLed = 1U; Siul2_Dio_Ip_TogglePins(LED_Q172_PORT, (1<<LED_Q172_PIN)); } void BctuWatermarkNotif(void) { uint8 idx; notif_triggered = TRUE; for (idx = 0u; idx < BCTU_FIFO_WATERMARK; idx++) { data_bctu = Bctu_Ip_GetFifoData(BCTUHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, BCTU_USED_FIFO_IDX); } } int main(void) { StatusType status; uint8 Index; Clock_Ip_StatusType clockStatus; /* Initialize and configure drivers */ clockStatus = Clock_Ip_Init(&Clock_Ip_aClockConfig[0]); while (clockStatus != CLOCK_IP_SUCCESS) { clockStatus = Clock_Ip_Init(&Clock_Ip_aClockConfig[0]); } Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals, g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals); Bctu_Ip_Init(BCTUHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, &BctuHwUnit_0_BOARD_INITPERIPHERALS); status = (StatusType) Adc_Sar_Ip_Init(ADCHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, &AdcHwUnit_0_BOARD_InitPeripherals); while (status != E_OK); /* set PIT 0 interrupt */ IntCtrl_Ip_Init(&IntCtrlConfig_0); IntCtrl_Ip_EnableIrq(PIT0_IRQn); /* Install and enable interrupt handlers */ IntCtrl_Ip_InstallHandler(ADC0_IRQn, Adc_Sar_0_Isr, NULL_PTR); IntCtrl_Ip_InstallHandler(BCTU_IRQn, Bctu_0_Isr, NULL_PTR); IntCtrl_Ip_EnableIrq(ADC0_IRQn); IntCtrl_Ip_EnableIrq(BCTU_IRQn); /* Call Calibration function multiple times, to mitigate instability of board source */ for(Index = 0; Index <= 5; Index++) { status = (StatusType) Adc_Sar_Ip_DoCalibration(ADCHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE); if(status == E_OK) { break; } } Adc_Sar_Ip_EnableNotifications(ADCHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN | ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN); /* Start a SW triggered conversion on BCTU using a single trigger */ Bctu_Ip_SetGlobalTriggerEn(BCTUHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, TRUE); Bctu_Ip_EnableNotifications(BCTUHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, BCTU_IP_NOTIF_FIFO1); /* Initialize PIT instance 0 - Channel 0 */ Pit_Ip_Init(PIT_INST_0, &PIT_0_InitConfig_PB_BOARD_InitPeripherals); /* Initialize channel 0 */ Pit_Ip_InitChannel(PIT_INST_0, PIT_0_CH_0); /* Enable channel interrupt PIT_0 - CH_0 */ Pit_Ip_EnableChannelInterrupt(PIT_INST_0, CH_0); /* Start channel CH_0 */ Pit_Ip_StartChannel(PIT_INST_0, CH_0, PIT_PERIOD); Trgmux_Ip_Init(&Trgmux_Ip_xTrgmuxInitPB);// Lpuart_Uart_Ip_Init(UART_LPUART_INTERNAL_CHANNEL, &Lpuart_Uart_Ip_xHwConfigPB_6_BOARD_INITPERIPHERALS); printf("S32K344 PIT TRIGMUX ADC demo RTD400.\r\n"); while(1) { if( toggleLed == 1) { toggleLed = 0; Bctu_Ip_SwTriggerConversion(BCTUHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, BCTU_USED_SINGLE_TRIG_IDX); while (notif_triggered != TRUE); notif_triggered = FALSE; printf("ADC0_bandgap ch48 data_bctu = %d .\r\n", data_bctu); } } } Test result: Fig 18 It is close to the typical expected value, indicating that it has been successfully run. Used demo code:S32K344_PIT_TRIGMUX_BCTUSW_ADC_printf_RTD400.zip   2.4 PIT+TRIGMUX+ADC hardware PIT TRIGUMX trigger This section is about hardware triggering. PIT is used in combination with TRIGMUX to directly trigger ADC1 channel 34, i.e. ADC1_S10 sampling. The trigger structure diagram is as follows:   Fig 19 Also based on the previous code, you need to add an additional module Trgmux_Ip in the CT peripherals, and the rest of the configuration remains unchanged.   Fig 20 Here, the input of Trigmux is selected as PIT0_CH0 and the output is ADC1. The code is also much simpler. Add the following code in main: Trgmux_Ip_Init(&Trgmux_Ip_xTrgmuxInitPB);// while(1) { if(notif_triggered1 == TRUE) { notif_triggered1 = FALSE; printf("ADC1_s10 ch34 data = %d .\r\n", data1); } } In While(1), we can see that there is no software-triggered call. We can directly check the ADC1 conversion completion flag and then print the data. The test results are as follows: Fig 21 It can be seen that as the external potentiometer changes, the sampled value of ADC1_S10 also changes. Used demo:S32K344_PIT_TRIGMUX_ADC_printf_RTD400.zip   2.5 EMIOS+BCTUHW+ADC hardware EMIOS BCTU trigger The block diagram structure of this section is as follows:   Fig 22 Use eMIOS0_CH0 to generate a 10Khz clock to trigger BCTU to complete the sampling of ADC0_48 channel, that is, bandgap. In the CT tool, add Emios_Mcal_Ip and configure it as follows:       Fig 23 Change the BCTU configuration to enable HW triggering. The configuration is as follows:   Fig 24 Main code related codes are as follows: Emios_Mcl_Ip_Init(EMIOS_INST0, &Emios_Mcl_Ip_0_Config_BOARD_INITPERIPHERALS); while(1) { if( toggleLed == 1) { toggleLed = 0; printf("ADC0_bandgap ch48 data_bctu = %d .\r\n", data_bctu); } } Since the sampling rate is triggered at a frequency of 10Khz, the frequency is relatively fast, so the printing here is still based on 1s. The printing results are as follows:   Fig 25 As you can see, the result is also a variable bandgap value. Used demo:S32K344_PIT_TRIGMUX_BCTUHW_EMIOS_ADC_printf_RTD400.zip   2.6 EMIOS+BCTUHW LIST+ADC hardware EMIOS BCTU trigger LIST This section is similar to the EMIOS BCTU hardware trigger above, except that the BCTU is configured in the form of LIST, which can trigger the conversion of multiple channels at once. The main modifications are in the BCTU module:   Fig 26 Add the corresponding main code as follows: #define BCTU_FIFO_WATERMARK 3U void BctuWatermarkNotif(void) { uint8 idx; notif_triggered = TRUE; for (idx = 0u; idx < BCTU_FIFO_WATERMARK; idx++) { data_bctu[idx] = Bctu_Ip_GetFifoData(BCTUHWUNIT_0_BOARD_INITPERIPHERALS_INSTANCE, BCTU_USED_FIFO_IDX); } } while(1) { if( toggleLed == 1) { toggleLed = 0; printf("ADC0_bandgap ch48 data_bctu = %d .\r\n", data_bctu[0]); printf("ADC0_vrefl ch54 data_bctu = %d .\r\n", data_bctu[1]); printf("ADC0_vrefh ch55 data_bctu = %d .\r\n", data_bctu[2]); } } Test result is: Fig 27 It can be seen that the results are consistent with the collected bandgap, VREFL, and VREFH, indicating that the code function is running normally. Code in this section:S32K344_PIT_TRIGMUX_BCTUHWLIST_EMIOS_ADC_printf_RTD400.zip  
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********************************************************************************  Detailed Description:  Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN  module to wake up MCU from STOP mode using SDK.  Wake up by Timeout and wake up by Match events are enabled.  Also pin interrupt can be used to exit STOP mode.  So MCU enters STOP mode by pressing SW3 button.  MCU exits STOP mode when one of following happens:  - no CAN message comes in 8sec (CAN PN timeout event)  - message with standard ID 0x554 or 0x555 comes (CAN PN match event)  - SW2 button is pressed (PTC12 interrupt)  In run mode blue LED is dimming and the rate is different for each wakeup event  ------------------------------------------------------------------------------  Test HW: S32K116EVB-Q48  MCU: PS32K116LAM 0N96V  Compiler: S32DS.ARM.2.2  SDK release: S32SDK_S32K1xx_RTM_3.0.0  Debugger: Lauterbach, OpenSDA  Target: internal_FLASH ********************************************************************************
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*******************************************************************************  The purpose of this demo application is to present a usage of the  LPSPI IP Driver for the S32K3xx MCU.  The example uses LPSPI2 for transmit & receive Twelve bytes using the DMA. MOSI MISO connected on Hardware in loopback.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    
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Often we need to implement a SENT receiver in order to read the information sent by some sensors. It is useful to have the possibility of transmitting different message patterns in order to test your implementation. With this project you can transmit via a computer terminal a group of messages (up to 64). The project runs on a S32K144 EVB board, the output signal goes through J206 pin.
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Some customers inquire about the FreeMASTER JumpStart Project mentioned in the Get Started with the S32K1xxEVB. So here to talk about the problems you may encounter and how to solve them. Where to download FreeMASTER JumpStart Project Customers may not find where to download FreeMASTER JumpStart Project at the moment. It should be downloaded from the Embedded Software under Design Resources of the development board. But the download link of S32K142EVB \ S32K144EVB \ S32K146EVB is missing. We can search the keywords “* JumpStart” at www.nxp.com download embedded application software and PC host application software that you need. Which version of S32 Design Studio should be used The readme file will tell us which version of S32 Design Studio the project was created. For example: the readme in the S32K144_EVB_JumpStart_Firmware package shows that the project for S32K14x EVB JumpStart SW was created in S32 Design Studio for ARM v2.0. Which version of SDK should be used You may get the Validation of S32K144_EVB_JumpStart_Firmware Kinetis SDK project when import the project : The project S32K144_EVB_JumpStart_Firmware was created for Kinetis SDK SDK_S32K14x_08 which is not installed in this product (repository SDK_S32K14x_08 not found).  The chapter Version Tracking of S32SDK_for_S32K1xx_RTM_3.0.3_ReleaseNotes shows that the SDK_S32K14x_08 means EAR 0.8.5. By default only S32 SDK EAR 0.8.4 is installed in S32DS for ARM 2.0, so we need to update the S32 Design Studio for Arm® v2.0 Update 2 – S32 SDK 0.8.5 EAR & MQX by refer S32 Design Studio for Arm v2.0 - Update 2 available Incorrect UART baud rate setting The baud rate selected for LPUART in Processor Expert is 600 by default, which does not match the description in the readme file. 600 is not in the FreeMASTER serial port baud rate support list, so let us reconfigure the baud rate to 115200 and then click Generate Processor Expert Code. When connect S32K144EVB with FreeMASTER by UART, you can see that the Baud rate 300 is not in the support list. This is the reason why using the default configuration of S32K144_EVB_JumpStart_Firmware is not able to connect with FreeMASTER.       
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