********************************************************************************
* Detailed Description:
* The purpose of this example is show how to keep data in SRAM memory over SW
* reset. SW reset is triggered by pressing the SW3 button on the S32K118EVB.
* Reset is delayed for 514 LPO cycles. In the RCM interrupt, SRAMU_RETEN is
* cleared allowing to retain SRAM data during the reset. After SW reset,
* SRAMU_RETEN is set to allow accesses to SRAM.
* File startup_S32K116.S in modified to skip ECC RAM initialization for SW reset
* source. To check whether stored data stayed unmodified in the SRAM, specified
* address is read and the LED lights up.
* ------------------------------------------------------------------------------
* Test HW: S32K118EVB-Q064
* MCU: S32K118 LAMLH 0N97V QTZE1802B
* Fsys: fsys = 48MHz
* Debugger: Lauterbach Trace32
* Target: Debug
* Terminal: 19200-8-no parity-1 stop bit-no flow control
* EVB connection: default
********************************************************************************
Revision History:
Ver Date Author Description of Changes
0.0 May-17-2023 David Tosenovjan Initial version
*******************************************************************************/
