Example S32K312 placing variables in DCTM & code in ICTM DS3.5 RTD300

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Example S32K312 placing variables in DCTM & code in ICTM DS3.5 RTD300

Example S32K312 placing variables in DCTM & code in ICTM DS3.5 RTD300

*******************************************************************************

The purpose of this demo application is to place variables in DTCM memory for the S32K3xx MCU.

 ------------------------------------------------------------------------------
* Test HW: S32K3X4EVB-Q172
* MCU: S32K312
* Compiler: S32DS3.5
* SDK release: RTD 3.0.0
* Debugger: PE Micro
* Target: internal_FLASH
********************************************************************************

ZERO table : is for bss segment variables :  contains RAM start & end address of BSS section which need to be initialized with ZER).

Init_table : is for DATA segment variables : contains RAM start address of DATA section & START & end address of ROM address where the initialization values of the variables are stored.

 

Startup file startup_cm7.s call function init_data_bss() . Inside this function uses these section :--

Dinesh_Guleria_0-1705479264979.png


Variables declared :--

Dinesh_Guleria_1-1705479293837.png


Linker file changes :--

Dinesh_Guleria_3-1705486935533.png

 

Dinesh_Guleria_2-1705479316994.png


startup_cm7.s file changes :--

Dinesh_Guleria_3-1705479347509.png
Dinesh_Guleria_4-1705487006718.png

 



MAP file :--

Dinesh_Guleria_4-1705479364855.png

 

Dinesh_Guleria_0-1705486825279.png

 



Debug window results :--

Dinesh_Guleria_5-1705479384543.png

 

Dinesh_Guleria_6-1705479395572.png

 

Dinesh_Guleria_1-1705486885096.pngDinesh_Guleria_2-1705486897441.png

 

 

https://www.kernel.org/doc/html/v5.9/arm/tcm.html

 

Due to being embedded inside the CPU, the TCM has a Harvard-architecture, so there is an ITCM (instruction TCM) and a DTCM (data TCM). 

The DTCM can not contain any instructions, but the ITCM can actually contain data.

 

TCM is used for a few things:

  • FIQ and other interrupt handlers that need deterministic timing and cannot wait for cache misses.
  • Idle loops where all external RAM is set to self-refresh retention mode, so only on-chip RAM is accessible by the CPU and then we hang inside ITCM waiting for an interrupt.
  • Other operations which implies shutting off or reconfiguring the external RAM controller.

 

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Last update:
‎01-17-2024 03:46 AM
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