********************************************************************************
* Detailed Description:
*
* Example shows possible setting for PWM duty cycle update using DMA.
* FTM0 ch0 is set to Edge aligned mode with 20KHz period.
* Initialization trigger is routed back to HW trigger 1 using TRGMUX, so this HW
* trigger can be used for CnV synchronization.
* DMA on FTM0 ch0 is enabled (on ch0 CHF flag) and DMA ch0 configured to update C0V
* from duty cycle variable.
* NOte CHF is not set for 0% and 100% duty cycle, thus no DMA trigger is generated.
*
* Green LED is dimming as duty is changing.
*
* ------------------------------------------------------------------------------
* Test HW: S32K118EVB-Q64
* MCU: PS32K118LAMLH 0N97V
* Compiler: S32DS.ARM.2.2
* SDK release: S32SDK_S32K1xx_RTM_3.0.3
* Debugger: Lauterbach, OpenSDA
* Target: internal_FLASH
*
********************************************************************************
Revision History:
1.0 Sep-16-2021 Petr Stancik Initial Version
*******************************************************************************/
