Due to K3 hasn't been mass-produced yet, this content is moved to S32K3 Internal forum: https://community.nxp.com/t5/S32K3-Internal-Community/S32K3-Low-power-lab/ta-p/1280219 Any question, pls contact [email protected].

*******************************************************************************  The purpose of this demo application is to present a usage of the  UART IP Driver for the S32K3xx MCU.  The example uses LPUART6 for transmit & receive five bytes using the DMA.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    

******************************************************************************** * Detailed Description: * RAM self-test is performed after reset in startup_S32K144.s file. * The RAM self-test should be executed right after reset, so it does not destroy * data loaded to RAM by init functions. The code is inserted after * initialization of core registers. RAM initialization is commented out because * the same operation is done by the self-test. * The test flow is: * 1. Write pattern 0x55AA55AA to first word in RAM * 2. Read the data back * 3. Compare the data and increment error counter if not equal * 4. Write inverse pattern 0xAA55AA55 to first word in RAM * 5. Read the data back * 6. Compare the data and increment error counter if not equal * 7. Clear the first word in RAM to leave whole RAM erased to ‘0’ at the end of test * This procedure is repeated for whole RAM. * If the error counter is different from zero at the end, the program stays in * endless loop until watchdog reset. * * ------------------------------------------------------------------------------ * Test HW:         S32K144EVB-Q100 * MCU:             FS32K144UAVLL 0N57U * Fsys:            Default * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

Hi,    Firstly, you should get the flash block size of your S32K3xx. Table in RM could be the reference.    Secondly, you should know that there are super sector and sector in S32K3xx.   Sector                    Subdivision of the Flash Block that is independently erasable. Sector Size is always 8 KB. Super sector          Subdivision of the flash block that includes a group of sectors. Super Sector Size is always 64 KB, and consists of 8 sectors.    Thirdly, based on the information of PFCBLKx_SSPELOCK in RM, you can calculate the numbers of super sector and sector in each flash block.   For example in S32K312, it has 2MB flash totally and each block is 1MB. So, in each 1MB, its first 768KB is with super sector granularity. The numbers of super sector is 768/64=12; the followed sector number is 256/8=32. Cheers! Oliver

******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************

Hello,      NXP does a big change on document structure.     Generally, you can find pin assignment table, interrupt mapping and memory map table in RM. But now, these information change to Excel files and attached in RM.   For example on S32K.    You will find the words in RM, like 'For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual.'    Then, please go to attachment tab of your PDF file viewer, like Adobe Acrobat Reader DC.     These steps are also fit for MPC57xx , S32R family. Cheers! Oliver

Due to K3 hasn't been mass-produced yet, this content is moved to S32K3 Internal forum: https://community.nxp.com/t5/S32K3-Internal-Community/S32K3-Low-power-lab/ta-p/1280219 Any question, pls contact [email protected].

Hi,     I would like to share with you the follow solution for S32K14x which could be attached while couldn't be re-programmed and stopped at RAM initializing.     If you met the issue as title, please check the SIM_CHIPCTL's value in IDE with attach function. Maybe you can find that the value is 0x0, which is not as default value after reset which is 0x0030_0000.     If you check the meaning on SIM_CHIPCTL, you can find that SRAMU and SRAML are retained across resets.  To solute the issue, you should add 'WRITE_LONG=00300000/40048004/ ;' in front of it the algorithm (it's better after reset) of freescale_s32k144f512m15_pflash_dflash_eeprom.arp which is at  'C:\NXP\S32DS_ARM_v20\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_3.3.3.201712132114\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx' After that, you can download your project as normal. Cheers! Oliver

You can find here a reference code for a march c software test in order to test RAM memories

S32K344 - FOC with dual shunt current measurement These examples demonstrate a 3-phase Permanent Magnet Synchronous Motor (PMSM) vector control (Field Oriented Control - FOC) drive with 2- shunt current sensing with and without position sensor. This design serves as an example of motor control design using NXP S32K3 automotive family.   Examples were designed on S32K344 Brushless Direct Current and Permanent Magnet Synchronous Motor Control Development Kit.  C-project based examples are part of MCSPTE1AK344 Development Kit Application Software. An innovative drivers set, Real-Time Drivers (RTD),are used to configure and control the MCU. It complies with Automotive-SPICE, ISO 26262, ISO 9001 and IATF 16949. Production-ready Automotive Math and Motor Control Library set provides essential building blocks for algorithm. FreeMASTER is used as useful run-time debugging tool. Application software contains:  MCSPTE1AK344_PMSM_FOC_2Sh_ll - Low-level drivers of RTD and S32 Design Studio Configuration Tools (S32CT) are used to demonstrate non-AUTOSAR approach. Detailed description of the example can be found in application note AN13767. MCSPTE1AK344_PMSM_FOC_2Sh_as_tr - RTD, EB (Elektrobit) tresos Studio and S32 Design Studio are used to demonstrate AUTOSAR (AUTomotive Open System ARchitecture) approach. Detailed description of the example can be found in application note AN13884.   MATLAB Simulink based project (Motor Control PMSM Example - s32k344_mc_pmsm_ebt) is build using Model-Based Design Toolbox (MBDT) and can be downloaded from NXP Model-Based Design Toolbox for S32K3xx - version 1.4.0 or newer releases. Example is described in article  3-Phase Sensorless PMSM Motor Control Kit with S32K344 using MBDT blocks. 

*******************************************************************************  The purpose of this demo application is to present a usage of the LPI2C-0 as MASTER and LPI2C-1 SLave, using DMA for TX & RX for the S32K3xx MCU.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************

Hello everyone, SEGGER's Real Time Transfer (RTT) is the new technology for interactive user I/O in embedded applications. It combines the advantages of SWO and semihosting at very high performance. Bi-directional communication with the target application Very high transfer speed without affecting real-time behavior Uses debug channel for communication No additional hardware or pin on target required Supported by any J-Link model Supported by ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 and Renesas RX100/200/600 Complete implementation code providing functionality and freedom Here, I'd like to share you the SEGGER RTT porting project on S32K144 as attached. SW requirements: S32DS for ARM v2.2 IDE + S32K1xx SDK RTM 3.0 HW requirements: S32K144-EVB  + J-LINK debugger   For SEGGER RTT, you can refer to: About Real-Time Transfer: https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/   RTT SEGGER Wiki： https://wiki.segger.com/RTT#SEGGER_RTT_TerminalOut.28.29；   Using Segger Real Time Terminal (RTT) with Eclipse： https://mcuoneclipse.com/2015/07/07/using-segger-real-time-terminal-rtt-with-eclipse/   Hope this project can help you, and enjoy the RTT! Best regard, Enwei Hu.

******************************************************************************* The purpose of this demo application is to place variables in DTCM memory for the S32K3xx MCU.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** ZERO table : is for bss segment variables :  contains RAM start & end address of BSS section which need to be initialized with ZER). Init_table : is for DATA segment variables : contains RAM start address of DATA section & START & end address of ROM address where the initialization values of the variables are stored.   Startup file startup_cm7.s call function init_data_bss() . Inside this function uses these section :-- Variables declared :-- Linker file changes :--   startup_cm7.s file changes :--   MAP file :--     Debug window results :--         https://www.kernel.org/doc/html/v5.9/arm/tcm.html   Due to being embedded inside the CPU, the TCM has a Harvard-architecture, so there is an ITCM (instruction TCM) and a DTCM (data TCM).  The DTCM can not contain any instructions, but the ITCM can actually contain data.   TCM is used for a few things: FIQ and other interrupt handlers that need deterministic timing and cannot wait for cache misses. Idle loops where all external RAM is set to self-refresh retention mode, so only on-chip RAM is accessible by the CPU and then we hang inside ITCM waiting for an interrupt. Other operations which implies shutting off or reconfiguring the external RAM controller.  

S32K344 - FOC integrated with FreeRTOS This example demonstrates a 3-phase Permanent Magnet Synchronous Motor (PMSM) vector control (Field Oriented Control - FOC) drive with 2- shunt current sensing with and without position sensor integrated in FreeRTOS environment. This design serves as an example of motor control design using NXP S32K3 automotive family. Example was designed on S32K344 Brushless Direct Current and Permanent Magnet Synchronous Motor Control Development Kit.  C-project based examples are part of MCSPTE1AK344 Development Kit Application Software. An innovative drivers set, Real-Time Drivers (RTD),are used to configure and control the MCU. It complies with Automotive-SPICE, ISO 26262, ISO 9001 and IATF 16949. Production-ready Automotive Math and Motor Control Library set provides essential building blocks for algorithm. FreeMASTER is used as useful run-time debugging tool. Application software contains:  MCSPTE1AK344_PMSM_FOC_2Sh_ll_FreeRTOS - Low-level drivers of RTD and S32 Design Studio Configuration Tools (S32CT) are used to demonstrate non-AUTOSAR approach. Since the motor control structure of the example is similar to dual shunt example, detailed description of the example can be found in application note AN13767 and FreeRTOS related part in AN12881 .

I write a doc and a demo about LPUART hardware flow control, runs on s32k144 evb board with RTM 3.0.0, the flow control function work normally. If you have any question please contact me. 

S32K344 + MC33664 + MC33774 : RTD 3.0.0 : BMS SDK 1.0.2 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K344-MC33664-MC33774-RTD-3-0-0-BMS-SDK-1-0-2/ta-p/2028783 S32K344 + MC33665 + MC33774 : RTD 3.0.0 : BMS SDK 1.0.2 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K344-MC33665-MC33774-RTD-3-0-0-BMS-SDK-1-0-2/ta-p/2127108 S32K344 + MC33664 + MC33775 : RTD 3.0.0 : BMS SDK 1.0.2 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K344-MC33664-MC33775-RTD-3-0-0-BMS-SDK-1-0-2/ta-p/2127049 S32K344 + MC33665 + MC33775 : RTD 3.0.0 : BMS SDK 1.0.2 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K344-MC33665-MC33775-RTD-3-0-0-BMS-SDK-1-0-2/ta-p/2127140 S32K144 : RTD-1.0.1 porting for : BCC_S32K144_FreeMASTER :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K144-RTD-1-0-1-porting-for-BCC-S32K144-FreeMASTER/ta-p/2130167

*******************************************************************************  The purpose of this demo application is to present a usage of the  LPSPI IP Driver for the S32K3xx MCU.  The example uses LPSPI2 for transmit & receive Twelve bytes using the DMA. MOSI MISO connected on Hardware in loopback.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    

Greetings, if you want to use the open source EmbSysRegView plugin in your Eclipse environment: this article describes how to add the S32K CMSIS-SVD files to it: Adding CMSIS-SVD Files to EmbSysRegView 0.2.6.r192 and Eclipse Happy SVDing 🙂 Erich

Audio Video Bridging(AVB) is a protocol for the transport of audio and video streams over Ethernet-based networks, which makes it possible to deliver high volumes of data in real-time to multiple destinations with very low latency. This reference design board demonstrates the usage for AVB over S32K148. Alternatively, it can be an S32K148 evaluation board of 100pin version besides S32K148EVB-Q144 and S32K148EVB-Q176. Below shows the board layout, diagram, and main features. Figure 1. S32K148AVB-RDB Layout   S32K148AVB-RDB Diagram(Rev B) Figure 2. S32K148AVB-RDB Diagram S32K148AVB-RDB Features Figure 3. S32K148AVB-RDB Features In terms of the software, we provide several examples to show the AVB/TSN usages and other applications. The avb_listener_talker project is the main example which implements most features and demonstrates by connecting 2 AVB boards by Ethernet cable.   Figure 4. S32K148AVB-RDB Code Examples Below software stack and middleware are implemented. ✓ RTOS: FreeRTOS ✓ Peripherial Driver: SDK RTM 3.0 (Work with Processer Expert) ✓ AVB Stream: RTM 1.0 ✓ AVB AudioIf: RTM 1.0 ✓ gPTP Stack Version: 1.3.4 ✓ Lwip Stack Version: 2.1.2 •Note: Even though we did a lot of tests, it’s still the customer’s responsibility to ensure the total quality by themselves when it’s integrated into a real application project, all the sample codes and user guide documentation are just reference for the customer. •Note: We do not have an FCC or CE certificate for this board.   Now we have 50 pcs boards available in Chongqing, China. For applying for the board, please contact NXP sales or GPIS marketing.  Since the AVB stack is not free of use, for accessing the code please contact NXP sales or GPIS marketing. For technical discussion, please contact [email protected] or [email protected].  

           The hardware of this routine is based on S32K142EVB, the IDE is S32_Design_Studio for ARM 2018.R1, SDK version is S32K1xx_RTM_3.0.0, PTB12 is used to simulate Hall pulse output,PTC12 and PTC13 are buttons to change the flip frequency of PTB12 port, and PTB13 is used as the input capture port. When using the demo program in this article, you need to connect PTB12 and PTB13 ports.   Here we assume that we are using a brushed DC motor!   1.The Hall sensor       The Hall sensor is a magnetic induction sensor. The magnetic ring and the Hall element form an induction combination. The magnetic ring rotates with the rotor. The Hall induction magnetic ring rotates with the rotor. , 3-pole pairs, 4-pole pairs, etc., each pair of poles is divided into two levels of N.S. A pair of magnetic poles outputs one pulse signal, and multiple magnetic poles output multiple pulse signals. The number of magnetic pole stages determines the number of pulse signals. , the higher the accuracy.   Hall sensor 2.The relationship between the motor magnetic ring series and the output Hall waveform 5 pole pairs 3.Determination of motor rotation direction         The direction of the motor is judged by the phase difference of the two Hall signals. As shown in the figure below, the phase of Sensor A is ahead of Sensor B, so it can be considered that the current rotation direction of the motor is clockwise.   4.Calculation of motor speed         The speed of the motor can be calculated by the pulse width of the pulse, and the number of revolutions of the motor can be calculated by the number of pulses. Assuming that the Hall magnetic ring of the motor has 5 pairs of poles, it means that there are five pulses in one revolution of the motor, and the speed of the motor = 60 / (t1 * 5) rev/min. The number of pulses can be obtained by the edge capture function of the FTM. Motor speed and stroke         Assuming that the clock of the FTM is 2MHz, then it takes 1/2000000 seconds for the counter to add 1. Since the unit of the motor speed is rpm, the calculation formula of the motor speed is : -> Motor Speed = 60 / (5 * a* (1 / 2000000))         In this formula, '5' is the number of pole pairs of the magnetic ring, and 'a' is the difference of the counter corresponding to the falling edge of two consecutive pules.         Let’s do a test, the square wave in the below figure is the outputs of PTB12, and the output pulse period is 32.1ms. Then the time required for the motor to rotate once should be:32.1ms *5 = 160.5ms, then the speed of the motor should be: 60 * 1000 / 160.5 = 373.83rpm.   PTB2 output square wave          The below picture is directly obtained by the debugger. It can be seen that the speed of the motor at this time is 373, which is not much different from the value measured by the oscilloscope, which is 373.83. This is because I did not use the floating-point calculation result in the program. In summary, we use the input capture function of the FTM module completes the calculation of the motor speed.   debuger monitor results 5.How to calculate the direction of rotation of the motor         Above we calculated the speed of the motor, but did not make judgement on the direction of the rotation of the motor. As mentioned above, the rotation direction of the motor is judged by the phase difference of the two Hall pulse waveforms. Usually, we think of using the timestamp to judge the current state of the phase, so we will enable the two input captures, and then calculate the two Halls timestamp of the falling edge of the pulse.         In fact, there is a simpler method, it only needs to read the high and low state of the other Hall pulse level when the falling edge of one hall pulse is interrupted. In short, we only need to enable one input capture, and the other to be used as a GPIO port.