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The purpose of this demo application is to place variables in DTCM memory for the S32K3xx MCU.
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* Test HW: S32K3X4EVB-Q172
* MCU: S32K312
* Compiler: S32DS3.5
* SDK release: RTD 3.0.0
* Debugger: PE Micro
* Target: internal_FLASH
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ZERO table : is for bss segment variables : contains RAM start & end address of BSS section which need to be initialized with ZER).
Init_table : is for DATA segment variables : contains RAM start address of DATA section & START & end address of ROM address where the initialization values of the variables are stored.
Startup file startup_cm7.s call function init_data_bss() . Inside this function uses these section :--
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Variables declared :--
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Linker file changes :--
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startup_cm7.s file changes :--
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MAP file :--
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Debug window results :--
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https://www.kernel.org/doc/html/v5.9/arm/tcm.html
Due to being embedded inside the CPU, the TCM has a Harvard-architecture, so there is an ITCM (instruction TCM) and a DTCM (data TCM).
The DTCM can not contain any instructions, but the ITCM can actually contain data.
TCM is used for a few things:
- FIQ and other interrupt handlers that need deterministic timing and cannot wait for cache misses.
- Idle loops where all external RAM is set to self-refresh retention mode, so only on-chip RAM is accessible by the CPU and then we hang inside ITCM waiting for an interrupt.
- Other operations which implies shutting off or reconfiguring the external RAM controller.