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******************************************************************************************** * Detailed Description: * LPIT_ch0 triggers DMA_ch0 periodically (1ms). * Every trigger starts a minor DMA loop (8 bytes) transfer to the LPSPI1 TX FIFO. * There are 8 minor loops per one major loop (64 bytes in 8ms). * LPSPI1 sends two 32bit frames every 1ms. * LPSPI1 RX data are masked, they are not stored in the RX FIFO. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144 0N57U * Debugger: S32DS 2.2, OpenSDA * Target: internal_FLASH ********************************************************************************************
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******************************************************************************* The purpose of this demo application is to use pad keeping for  PINS and enter the standby mode & before entering the standby mode update variables in Standby RAM memory with pin state. Once wake up from the standby mode update the pins values from the STANDBY RAM variables.  S32K3xx MCU.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** =============== How this DEMO works ========== Before entring standby :-- Before entering standby mode, i make BLUE LED high SW6 on board pressed to enter the standby mode. Wakeup from Standby :-- SW5 on board pressed to wakeup from standby After wakeup from Stand by:-- I glow Green LED Unglow the BLUE LED Wait for SW6 on board to be pressed to enter the standby mode. ===============  Stand by RAM location =============== As noted, the Standby SRAM is allocated at the first 32 KB of the SRAM Memory. https://www.mouser.com/pdfDocs/S32K3MemoriesGuide.pdf =============== Pins used for PAD keeping =============== PTA30, PTA31, PTD14     =============== Switches used ===============   Enter Standby mode, by pressing SW6 on Board EXIT Standby mode, by pressing SW5 on Board =============== Wakeup source, SW5 PTB26 =============== =============== WKPU[41]  ---> WKPU_CH_45=============== Because First 4 WKPU are timers, so 41 + 4 = 45   =============== Linker file changed =============== Added Standby RAM memory & sections for standby RAM memory. Changes can be seen by comparing the original linker file      =============== Startup file changed , startup_cm7.s =============== Added call to Initialise the Standby RAM Changes can be seen by comparing the original startup_cm7.s file     ======================= How to verify if Standby RAM is working =============== 1> Declare two variables in file Wkup.c :-- __attribute__ ((section (".standby_ram_data"))) volatile int test_0_value ; __attribute__ ((section (".standby_ram_data"))) volatile int test_1_value ;   2> function set_pin_value() will be called before entering the standby mode. Initialise the values to these two variables inside function set_pin_value() in file Wkup.c.   3> Now burn the code inside the MCU using the PE micro debugger.     Once code is burned do not run the code & disconnect the debugger. 4> Power OFF and power ON the S32K312 board. Now code is waiting to enter standby mode. Press switch SW6 MCU will enter standby mode & Blue LED glowing. Press switch SW5 MCU will wakeup from the standby mode. Code will Now code is waiting to enter standby mode 5> Now open your debugger configuration, and attach to running target.   6> Once connected click on the ELF file & press pause button.   7> In Debug window you can see the value of variables test_0_value & test_1_value same as initialised before entering the standby mode.      
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Hi all,   Many customers complained about the K3 FlexIO I2S can not support continuous transferring because there is a gap time between 2 times of invoking SendData. This gap time will break the audio continuity and bring jitters. It is gapped by the transfer API closing and re-entry time cost.   To avoid this gap and implement a real continuous transferring, we made some changes with eDMA configurations. Finally, it works!   Besides, we also enabled eDMA half-complete interrupt to support double-buffer (ping-pong buffer) operation for user's further development.   Attachments are the example projects and corresponding introduction slides, please kindly check if you are interested in. Any problem, just let me know. Welcome your comments here.   Best Regards, Shuailin Li NXP GPIS, AE
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************************************************************************************************************************** * Detailed Description: * * Connect PTC24 (PWM) to PTC25 (IC) * * PWM signal generated by EMIOS_1_ch0 (in OPWFMB mode) is measured by EMIOS_1_ch_1 (IPWM mode). * * EMIOS_1 global global clock (core clock = 48MHz) prescaled in EMIOS_Mcl driver (/48) = 1MHz. * * BUS_A generated by EMIOS_1_ch_23 * Tick = 10us (1MHz global clock prescaled by 10 = 100kHz) * * PWM (OPWFMB), EMIOS_1_ch_0, PTC24 * Tick = 10us (1MHz global clock prescaled by 10 = 100kHz) * * IC (IPWM), EMIOS_1_ch_1, PTC25 * Clocked by BUS_A * Tick = 10us * * ------------------------------------------------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Debugger: S32DS 3.4, PEMicro Multilink rev.C * Target: internal_FLASH **************************************************************************************************************************
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This article is written in Chinese. It is mainly for the disty and mass market customers in local China. It is useful for the the developers who is newly in touch with S32K1, and will help them install several software of S32K1, otherwise it may waste a lot of time.     S32DS中快速搭建S32K1的开发环境 一.背景 我最近换装了新电脑,需要重新安装S32DS,发现存在很多问题。尤其是对比之前的安装过程,发现官网的很多链接已经失效,甚至有一定的迷惑性。 最新的S32K1安装包比较隐蔽,而且安装存在前后依赖,对于刚接触NXP S32系列的新手非常不友好,所以写这篇文档总结一下典型的问题和解决方法。 同时也希望提供一个check的思路和步骤,在后续新版本发布时,升级IDE的时候更方便找到合适的安装包。 二.S32DS中各个包依赖关系解析 在S32DS中,每一个系列的MCU,总共需要安装两个插件包,一个是基础依赖包,一个是SDK(也叫RTD,同一个意思)。 1.基础依赖包 这个包对应S32DS版本,比如当前的3.4.3,官网可以下载离线版,一般大小在3GB左右,会更新S32DS中的很多组件,如下图1所示:            图1 尤其需要关注图1中红框的内容,没有这个development package的话,是无法进行对应MCU的debug。 图1中安装的包,对应到S32DS中安装的内容如图2所示:            图2 2.RTD安装包(与SDK同义) 这个包对应于RTD版本,也会标识AutoSAR的版本,比如最新的2.0.0,AutoSar 4.4,如图3所示:           图3 基础依赖包与RTD安装包存在前后依赖关系,如果不安装基础依赖包直接安装RTD,在安装时会报错。另外,我们下载的RTD包,即使写明是K3,里面也会包含K1的RTD,这点需要注意。如果此时还没有装K1的development package,就会出错。 三.S32K1开发环境搭建 官网对于S32K3的软件划分为standard software和reference software,其中S32DS和基础依赖包在standard software中,可以很方便的找到。 但S32K1的官网却仅有一个reference software,页面也只能找到几个RTD(或SDK)链接:                                                                             图4 这里面所有的链接都不是我们需要的,全是RTD。问题就出在这里,K1的网页中没有K1的基础依赖包!而前面讲过,缺基础依赖包会导致RTD也无法安装。经过我研究,K1的基础依赖包隐藏的非常深,可以通过两个方法找到: 从S32K1的reference software进去,然后重新点击product list,如下图5所              图5         进入如下页面,如图6所示,这里最能看出来,针对K1的界面很不友好,需要点最底下的NXP Software.              图6 在NXP.com官网首页搜索栏直接搜S32DS,找到S32 Design Studio for S32 Platform(注意不要选成for ARM或或者for PowerPC),从S32DS的主界面进入,然后一直下拉,找到S32DS service pack 1,这个才是K1的,如图7所示:                 图7 这个链接更加隐蔽,要在40多个选项里挨个找。   经过上面两个方法,都可以进入图8所示的界面,然后再按图8所示操作:              图8   这回终于到了最终可以下载S32K1基础依赖包的地方,如图9所示。我们需要重点关注一下命名,SW32开头的,会包含所有S32的development package,包括K1,K3,G;SW32K1开头的,仅有K1,同理如果你在K3的界面中,可以看到SW32K3开头的。            图9 下载最新版本的S32K1基础依赖包,然后再安装RTD,大功告成。
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******************************************************************************** * Detailed Description: * Example is based on Siul2_Port_Ip_Example_S32K344 and its purpose it to show * how to integrate ITCM and DTCM memories to the project. * * Modification has been done in following files: * - main.c * - startup_cm7.s * - linker_flash_s32k344.ld * * In the main function, function is placed to ITCM memory and executed. Also * data field in placed to DCTM and accessed. * ******************************************************************************** * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.4 * SDK release: PlatformSDK_S32K3_3_0_0 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 David Tosenovjan Initial version *******************************************************************************/
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*******************************************************************************  The purpose of this demo application is to present a usage of the  ADC_SAR and BCTU IP Driver for the S32K3xx MCU.  The example uses the PIT0 trigger to trigger BCTU conversion list to  perform  conversions on ADC1.  ADC channels  are selected to be converted on  ADC-1:  ADC1: P0, p1, p2, p3, p4, p5, p6, S10  Converted results from  BCTU_ADC_DATA_REG are moved by DMA into result array.  ADC channel S10 is connected to board's potentiometer.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Set PIT Freeze Enable :--- All channels are for ADC-1 , in BCTU list :--     "NEW DATA DMA enable mask" :-- controls These bit field in MCR register     "ADC target mask" :-- It controls "ADC_SEL " bit field in "Trigger Configuration (TRGCFG_0 - TRGCFG_71)" for single conversions you can enable only one instance so the possible values for target mask: 1 (0b001) ADC0 2 (0b010) ADC1 3 (0b100) ADC2| for list of conversions we can enable also parallel con version for example 3 (0b011) parallel conversion of ADC0 and ADC1 The trigger is configured as a list of parallel conversions ADC0, ADC1 in “Adc Target Mask”. List of ADC channels is defined in “BCTU List Items” while order is given by the “Adc Target Mask”: BctuListItems_0 is ADC0, BctuListItems_1 is ADC1 etc.      
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Hi everyone, Welcome to the NXP Tech Days 2024 training session AUT-T4977: Hands - On Workshop: S32K3 Ethernet- How to Configure Hardware and Software. This session was initially planned for 15 attendees. But due to the popularity of the lecture, we have increased the number of available seats . Therefore, we will work in pairs during the Hands-On. My name is Alejandro Flores Triana (Alex) and I will be your guide during this conference. I am an Automotive Applications Engineer supporting different OEMs, Tier1s, Partners and other internal NXP teams on topics related to communication protocols (e.g. CAN, LIN, SPI, I2C, Ethernet, etc.). The idea of this session is for you to understand how to program the S32K3 Ethernet interface using NXP Real-Time Drivers (RTDs) – Autosar MCAL Layer. We will use a base project and together modify it to create a simple Ethernet application. Therefore, to be ready follow the steps below to get your environment up and running before the session. On your laptop, install the NXP Software environment described in the attached presentation: Hands - On Workshop: S32K3 Ethernet Prerequisites.   Once you have the NXP software environment installed, download the attached project: S32K344_ETH_MCAL_TechDays.exe   Run the .exe project with administrator rights. Accept the license and install in the desired folder         Open the NXP Design Studio. Click File -> Import -> Existing Projects into Workspace   Select root directory and browse the folder where you downloaded the project   Select Copy projects into workspace   Click Finish. Select the project. Click on the arrow next to the hammer. Click on Debug_FLASH. Then you are ready for the session! See you soon. Best Regards, Alejandro Flores Triana
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Some customers inquire how to use FreeMASTER with S32K3. But there is no exists example projects which demonstrate usage of the FreeMASTER serial communication driver in S32K3 Real Time Drivers at the moment. So this article will introduce how to use FreeMaster SDKs in S32K3 RTD 0.9.0. Download S32DS \ S32K3 Development Package \ RTD (SDK) \ FreeMASTER Driver Login your account on NXP website, and download the S32K3 Standard software from TOOLS &SOFTWARE of S32K3 webpage. If you have already installed the S32DS3.4 \ S32K3 Development Package 3.4.0 \ RTD 0.9.0, then you can skip the following part and start directly from 4.Install FreeMASTER Driver 3.0 for S32K3 Install S32K3 Development Package 3.4.0 After install the S32 Design Studio v3.4, we should install S32K3 Development Package 3.4.0(SW32K3_S32DS_3.4.0_D2012.zip): go to menu "Help" -> "Install New Software" and click on "Add..." button Here we uncheck S32 Design Studio S32K3 SDK (RTD S32K3 0.8.1), because we will install the newer version S32K3 RTD 0.9.0 later. Install S32K3 Real Time Drivers Version 0.9.0 S32K3 Real Time Drivers Version 0.9.0 can be installed by refer the Offline Package Installation Setup of S32DS Extensions & Updates: Explanation and How To Use. Install FreeMASTER Driver 3.0 for S32K3 Attach FreeMASTER_S32K3 to S32K344_UART_Printf_Sample_090_34 The reason for choosing the S32K344_UART_Printf_Sample_090_34 project to demonstrate the combination of FreeMaster SDKs is that the project has already configured the LPUART of the S32K3X4EVB-Q257 development board. Select LPUART peripheral as host communication Through the description in the Requirements and Release Description chapter of FreeMASTER Driver Release Notes(FMSTRS32K3RN), we can see that currently only UART interface is supported. The S32K3 FreeMASTER 3.0 version 1.0.0 only support NXP GCC 6.3 or 9.2 for ARM at the moment, but the latest S32K3 Real Time Drivers Version 1.0.0 is based on NXP GCC 10.2.0. This is the reason why RTD 0.9.0 is selected in this article.  The README.txt also shows that: Current package provides FreeMASTER Communication Driver support for S32K344 over LPUART module   LPUART13 is selected in this project for S32K3X4EVB-Q257, so we need to define the base address for FreeMASTER: #define FMSTR_LPUART_BASE           0x404A0000 Modify the main function according to the README.txt: Connect FreeMASTER3.1 to S32K3X4EVB-Q257 board Here we can see that the FreeMASTER3.1 is connected to S32K3X4EVB-Q257 board.  
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********************************************************************************  Detailed Description:  Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN  module to wake up MCU from STOP mode.  Wake up by Timeout and wake up by Match events are enabled.  Also pin interrupt can be used to exit STOP mode.  So MCU enters STOP mode by pressing SW3 button.  MCU exits STOP mode when one of following happens:  - no CAN message comes in 8sec (CAN PN timeout event)  - message with standard ID 0x554 or 0x555 comes (CAN PN match event)  - SW2 button is pressed (PTC12 interrupt)  In run mode blue LED is dimming and the rate is different for each wakeup event  ------------------------------------------------------------------------------  Test HW: S32K144 EVB-Q100  MCU: FS32K144UAVLL 0N57U  Fsys: 160MHz  Debugger: Lauterbach, OpenSDA  Target: internal_FLASH ********************************************************************************
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【RTD400 MCAL 3】 K312 MCU clock system configuration 1. Abstract This document is talking about how to configure the clock system in the MCU of the K3 chip MCAL. This topic was always disdainful to talk about when I was doing LLD before, because the clock system of K3 is too simple, with internal fast and slow clock sources, external fast and slow clock sources, a PLL multiplier, and then various core peripherals to share. K3's RM even made a few options to frame the rules. From the perspective of LLD, especially the perspective of S32DS CT configuration, it is even more concise and clear. Here is a CT picture to show it:   Fig 1     Fig 2 With such a clock system, you can generate code with just a few taps and pokes. However, LLD is too free, and MCAL often encounters problems. Therefore, I decided to spend some time to understand the entire clock system of this MCAL MCU. This article takes K312 as an example to explain. Other K3 series are similar. 2. Clock system theory and configuration 2.1 K312 clock system From the clock chapter of RM, you can see the whole system block diagram:     Fig 3 This block diagram clearly shows the situation of each part. There are four clock sources: Internal fast clock FIRC: 48MHz, +/-5% error, maximum startup time 25us Internal slow clock SIRC: 32KHz, +/-10% error, maximum startup time 3ms External fast clock FXOSC: 8-40MHz, startup stabilization time FXOSC_CTRL[EOCV] × 128 External slow clock SXOSC: 32.768KHz, startup stabilization time SXOSC_CTRL[EOCV] x 128 One PLL: input 8-40MHZ, VOC output 640M-1280Mhz, PLL_PHIn_CLK output 25-480MHz. MUX_0: Output CORE_CLK, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE_CLK, DCM_CLK MUX_1: Output system timer STM0_CLK MUX_3: Output FLEXCAN0-2 clock MUX_4: Output FLEXCAN3-5 clock MUX_5: Output CLKOUT_STANDBY MUX_6: Output CLKOUT_RUN MUX_11: Output TRACE_CLK RTC_CLK: RTC clock 2.1.1 PLL From the PLL perspective, we need to know which values ​​the frequency multiplier is related to, which can be calculated using the following formula:     Fig 4 If it is an integer, the red box in the above figure is the common method, and this article will also use the above method to configure. PLL_PHI is the clock output by the final PLL, which is provided to the MC corresponding to other MUXs for selection. 2.1.2 MUX_0 System The MUX_0 system with details can be seen from RM:     Fig 5 As you can see, the clock source of MUX_0 can be two types: PLL or internal FIRC. Then the core clock can be generated later, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE_CLK, DCM_CLK. So what is the specific frequency of the generated clock? In principle, it can meet the maximum clock corresponding to each module, but the K3 series also makes some option recommendations. For example, K312 recommends using option B mode when RUN, especially the HSE clock, which usually needs to strictly meet the option recommendation. 2.1.3 MUX_6 Clock output In order to check the corresponding clock situation in the chip, the corresponding clock can be output through the CLKOUT pin. The CLKOUT pin can correspond to the selection of multiple clock sources. The specific situation is as follows:     Fig 6 The yellow content in the figure is what K312's CLKOUT_RUN can support. After the clock is configured, the corresponding clock will be selected to test whether the output is consistent with the configuration. 2.1.4 option B Recommended Solution In this article, K312 will configure the clock of option B in EB.     Fig 7 2.2 EB configuration        First, create a new K312 EB project. For the specific creation method, please refer to the previous article: [S32K3 Tools Part] How to port RTD's existing MCAL demo to other K3 chips This article will focus on the clock configuration corresponding to the MCU module based on RTD400 MCAL. For MCU configuration, two documents need to be consulted as reference books: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Mcu_TS_T40D34M40I0R0\doc: RTD_MCU_UM.pdf and RTD_MCU_IM.pdf If you don’t know how to configure, just follow the default values ​​recommended by the document. The following figure is an overview of the MCU. The main configured modules have the following three components: General, McuClockSettingConfig, McuModeSettingConf     Fig 8 2.2.1 General configuration In addition to Figure 8, you need to turn on the internal and external fast and slow clock control and PLL control, and add the corresponding API, as well as the crystal oscillator frequency. If this is not turned on, the corresponding configuration later will not be able to be configured.     Fig 9 2.2.2 McuClockSettingConfig configuration        This is the core area of ​​MCU clock configuration, which includes clock source, PLL, and various MUX conditions. First, you need to add a clock configuration:     Fig 10 Click in and there will be detailed configuration:     Fig 11 There are 17 items in total. You can keep the default configuration for options 1 and 6. Since the board does not connect to the external slow crystal oscillator 5, it is not configured. The rest should be configured according to the actual situation. The following explains them one by one: 2.2.2.1 McuFIRC configuration    Internal fast clock, 48MHz:     Fig 12 2.2.2.2 McuSIRC configuration Internal slow clock 32Khz     Fig 13 2.2.2.3 McuFXOSC configuration External crystal oscillator 16MHZ, fill in according to the actual connection situation.     Fig 14 2.2.2.4 McuCgm0ClockMux0 configuration Mux0 configuration, here are configured core clock, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE, DCM_CLK, is to meet the optionB requirements, and the clock comes from PLL_PHI0_CLK. When actually configuring, first configure the PLL clock to output the correct PLL_PHI0_CLK, PLL_PHI1_CLK clock.     Fig 15 2.2.2.5 McuCgm0ClockMux1 configuration     Fig 16 It can be configured according to the clock source required by the actual module. 2.2.2.6 McuCgm0ClockMux3 configuration Configure the clock source of the FLEXCAN0-2 module:     Fig 17 2.2.2.7 McuCgm0ClockMux4 configuration Configure the clock source of the FLEXCAN3-5 module:     Fig 18 2.2.2.8 McuCgm0ClockMux5 configuration Configure the clock source of the CLKOUT_STANBY module:     Fig 19 2.2.2.9 McuCgm0ClockMux6 configuration Configure the clock source of the CLKOUT_RUN module     Fig 20 2.2.2.10 McuCgm0ClockMux11 configuration Configure the clock source of the TRACE_CLK module     Fig 21 2.2.2.11 McuRtcClockSelect configuration Configure the clock source of the RTC module     Fig 22 2.2.2.12 McuPLL configuration Configure the clock source of the PLL module     Fig 23 2.2.2.13 McuClockReferencePoint configuration Configure the reference clock and the clock source selection interface of the peripheral modules.     Fig 24 At this point, the clock configuration is complete. For verification, you can use the CLKOUT_RUN output to output the corresponding clock to pin PTD10 for viewing. 2.2.3 McuModeSettingConf  configuration In Mcu's McuModeSettingConf->McuPeripheral, you need to turn on the peripherals you want to use:     Fig 25 2.2.4 PORT  configuration Because the internal clock needs to be output to CLKOUT_RUN, K312's PTD10 MSCR106 is checked, so the PORT pin is added as follows:     Fig 26 3. Test Result Next, on the S32K312-EVB board, we modify the clock source of EB's CLKOUT_RUN to test whether the clock matches the configuration. Commonly used MCU-related drivers are as follows:     Fig 27 The calling sequence of system startup MCU initialization is as follows: 1). Mcu_Init() 2). Mcu_InitClock() 3). Mcu_GetPllStatus() - Till PLL is locked. 4). Mcu_DistributePllClock() 5). Mcu_SetMode() 6). Mcu_InitRamSection() - If required The corresponding main code is as follows: #include "Mcu.h" #include "Mcu_Cfg.h" #include "Port.h" #include "Dio.h" #include "Port_Cfg.h" #include "Platform.h" void TestDelay(uint32 delay); void TestDelay(uint32 delay) { static volatile uint32 DelayTimer = 0; while(DelayTimer < delay) { DelayTimer++; } DelayTimer = 0; } /** * @brief Main function of the example * @details Initialize the used drivers and uses the Icu * and Dio drivers to toggle a LED on a push button */ int main(void) { uint8 count = 0U; uint8 u8TimeOut = 100U; /* Initialize the Mcu driver */ #if (MCU_PRECOMPILE_SUPPORT == STD_ON) Mcu_Init(NULL_PTR); #elif (MCU_PRECOMPILE_SUPPORT == STD_OFF) Mcu_Init(&Mcu_Config_VS_0); #endif /* (MCU_PRECOMPILE_SUPPORT == STD_ON) */ /* Initialize the clock tree and apply PLL as system clock */ Mcu_InitClock(McuClockSettingConfig_0); #if (MCU_NO_PLL == STD_OFF) while ( MCU_PLL_LOCKED != Mcu_GetPllStatus() ) { } Mcu_DistributePllClock(); #endif /* Apply a mode configuration */ Mcu_SetMode(McuModeSettingConf_0); /* Initialize all pins using the Port driver */ Port_Init(NULL_PTR); /* Initialize Platform driver */ Platform_Init(NULL_PTR); while (count++ < 10) { Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q172, STD_HIGH); Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q257, STD_HIGH); TestDelay(5000000); Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q172, STD_LOW); Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q257, STD_LOW); TestDelay(5000000); } // Exit_Example(TRUE); return (0U); } #ifdef __cplusplus } #endif 3.1 CLKOUT FIRC_CLK DIV2     Fig 28 It can be seen that the original 48Mhz clock of FIRC is divided by 2 and the clock waveform of 24Mhz is obtained, which is correct! 3.2 CLKOUT SIRC_CLK DIV2     Fig 29 It can be seen that the original 32Khz clock of SIRC is divided by 2 and the clock waveform of 16khz is obtained, which is correct! 3.3 CLKOUT FXOSC_CLK DIV10     Fig 30 It can be seen that the original 16Mhz clock of FXOSC is divided by 10 and the clock waveform of 1.6Mhz is obtained. 3.4 CLKOUT PLLPH0 CLK DIV10     Fig 31 It can be seen that the original 120Mhz clock of PLLPH0 is divided by 10 and the 12Mhz clock waveform is obtained, which is correct. 3.5 CLKOUT CORE CLK DIV10     Fig 32 It can be seen that the original 120Mhz clock of CORE is divided by 10 and the 12Mhz clock waveform is obtained, which is correct. 3.6 CLKOUT PLLPH1 CLK DIV4     Fig 33 It can be seen that the original 48Mhz clock of PLLPH1 is divided by 4 and the 12Mhz clock waveform is obtained. 3.7 CLKOUT HSE CLK DIV10     Fig 34 It can be seen that the original 60Mhz clock of HSE is divided by 10 and the clock waveform of 6Mhz is obtained, which is correct. 3.8 CLKOUT AIPS_PLAT CLK DIV10     Fig 35 It can be seen that the original 60Mhz clock of AIPS_PLAT_CLK is divided by 10 and the clock waveform of 6Mhz is obtained, which is correct. 3.9 CLKOUT AIPS_SLOW CLK DIV10     Fig 36 It can be seen that the original 30Mhz clock of AIPS_SLOW_CLK is divided by 10 and the clock waveform of 3Mhz is obtained, which is correct.  
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Due to K3 hasn't been mass-produced yet, this content is moved to S32K3 Internal forum: https://community.nxp.com/t5/S32K3-Internal-Community/S32K3-Low-power-lab/ta-p/1280219 Any question, pls contact Jeremy.he@nxp.com.
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*******************************************************************************  The purpose of this demo application is to present a usage of the Bootloader Jump to Application.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************   Jump is decided based on the boot_header, size we use to jump to the RESET handler:--   Cortex M-7 Interrupt vector table, RESET handler is 4 byte offset from starting of vector table :--   // Reset_Handler+1  --> required in IVT, to avoid hard fault As per Arm®v7-M Architecture Reference Manual  --> DDI0403E_e_armv7m_arm.pdf         How to burn elf file of both application & bootloader code :--  
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1 Abstract After learning S32K3 PWM and have written some MCAL codes, this is the first MCAL article record starts with the combination of K344 EMIOS+ICU+TRIMUX+LCU, which can involve comprehensive configurations such as PORT, DIO, EMIOS, interrupt ICU, TRIGMUX, LCU, etc. The board platform is still based on NXP official S32K344EVB, RTD400, and the function is: use two channels of EMIOS0 and one channel of EMIOS1. After one channel of EMIOS 0 outputs PWM, it connects LCU through TRIGUMX to generate a set of complementary PWM, and the other channel can realize hardware interrupt control of PWM duty cycle through SW5 PT26 button. One channel of EMIOS1 is directly connected to the PTA29 onboard red light, and the brightness is gradually changed by changing the PWM duty cycle, and then the breathing light effect is realized by directly changing the on and off cycle. At the same time, when the PWM turns off the red light, the onboard green light is turned on through DIO, and when the PWM turns on the red light, the DIO turns off the onboard green light. Text description is always less intuitive than graphic description, so here is the picture:      Fig 1 2. Function realization This article is based on porting the MCAL code to the S32DS demo. Then, on the S32DS platform, MCAL related modules are configured through EB, and then compiled and downloaded for simulation through S32DS. Of course, if you like the command line mode, you can directly use the xmd file configured by EB, and then compile with VScode. The process is also very simple. This article will not go into details about the command line method.     2.1 Hardware and software platform Board:S32K344EVB,also can use other K3 boards. IDE:S32DS3.5 RTD: K344 RTD 400 MCAL tool: EBtresos Studio 29.0 2.2 Software control process Before talking about the specific MCAL configuration, here is the software flow chart of the functions in this article:                                                                             Fig 2 Here you can see that the default situation is the one configured through MCAL, and then the PWM frequency is also modified in the code, and the PWM duty cycle is modified by keystrokes and loop delays. 2.3 Resource Allocation Overview The hardware resources and functions used in this article are listed as follows: Fig 3 The configuration of emios related buses is as follows: Fig 4 It should be noted here that for the master bus and bus mode in MCL emios, it is necessary to select the appropriate PWM mode and counter bus in the PWM module, otherwise either the configuration will be wrong or the correct PWM waveform cannot be generated. From the official S32K3 RM, you can check the clock channel and bus type: Fig 5 For example, if EMIOS_CH23 is selected in PWM0, then this bus corresponds to bus A, and this clock can be used for all channels, so PWM0 is CH12 and can use Bus A. CH22 corresponds to bus F, and this clock can also be used for all channels, so it is no problem to select Bus F for PWM1 CH4. CH0 corresponds to bus B, and this clock corresponds to channels 0-7, so it can also be used for PWM2 is CH2. When selecting the counter bus clock source for your EMIOS channel, you must consider the channel coverage of the counter bus. In addition to the selection of the counter bus, there is also the PWM mode selection, which is easier to handle. For clock counting up, select OPWMB, and for clock counting up and down, select OPWMCB center-aligned PWM.      In actual use, the mode selection is usually determined based on one's own PWM requirements, and then based on the following RM table: Fig 6 You can find the channel types that the corresponding mode can support, and then select the corresponding channel, counter bus, etc. according to the channel type in Figure 5. With these basic knowledge, we can directly enter the EB configuration. 2.4 EB configuration    Here we list all the modules used in EB tresos related to this article, and focus on the modules that require specific configuration. Fig 7 2.4.1 Dio module The DioPort interface needs to be configured. The main purpose is to configure PTA30, onboard green light, select DioPort Id=1, Dio Channel Id=14. The rules for DioPortId and Dio Channel Id are as follows:     Channel = DioChannelId + DioPortId∗16 For S32K3X4 derivatives – Port AL=0 – Port AH=1 – Port BL=2 – Port BH=3 – Port CL=4 – Port CH=5 – Port DL=6 – Port DH=7 – Port EL=8 – Port EH=9 – Port FL=10 – Port FH=11 – Port GL=12 – Port GH=13 PTA30=>30=DioChannelId(14)+DioPortId*16 2.4.2 Icu module First, configure IcuSiul2, the goal is to enable the input interrupt of onboard SW5, PTB26. PTB26 corresponds to EIRQ[13], Then, the corresponding interrupt situation is as follows: Fig 8 Fig 9 (1) Icu->IcuSiul2->IcuSiul2Channels:13 (2) Icu->IcuChannel configuration is: Fig 10 Select IcuChannelRef as the previously configured IcuSiul2Channels, and add the interrupt notification function: User_EdgeDetect, note that this function is the name of the user interrupt processing function that needs to be added in the code.    (3)Icu->IcuHwInterruptConfigList-> ICU Peripheral ISR Name: SIUL2_0_IRQ_CH_13,IcuIsrEnable enable 2.4.3 Mcl module This module is mainly used to configure emios counting clock, trgmux, and LCU configuration. (1)Mcl->Trgmux Logic Instance->Hardware Instance: TRGMUX_IP_HW_INST_0   (2) Mcl->Trgmux Logic Group: Fig 11 The main purpose is to connect PWM1 Emios0_ch4 to LCU0_IN0 through Trigmux. (3)Mcl->LCU Configuration Here is the configuration of the LCU module. The main function is to configure the logic input and logic output. There is one input IN0 and two outputs OUT0 and OUT1. Fig 12 Fig 13 Fig 14 OUTPUT0  value is 0XAAAA=43690, OUTPUT1 value is 0X5555=21845 The purpose of this is to generate a pair of complementary PWMs from the input PWM. Fig 15 (4)Mcl->Emios Common Add two Emios, EMIOS_0 and EMIOS_1, which means two EMIOS are used. EMIOS0 is configured with two master bus channels: CH_22 and CH_0, and has different mode types, counting up and down and counting up. EMIOS1 is configured with one master bus channel: CH_23, counting up Corresponding to Figure 4. Fig 16 Fig 17 Note that the channel here is not the actual PWM output channel, but the counter bus channel of the PWM channel, which has the ability to provide clocks. 2.4.4 Mcu module   This module is the basis for the entire MCU to configure the clock. When using the default setting of the original RTD PWM demo, there is only one point that needs attention Mcu->McuClockSettingConfig_0->McuClockReferencePoint->McuClockReferencePoint_0->core clock 48MHZ. This clock is the source of the EMIOS clock. With the clock source, it is not difficult to calculate the actual PWM frequency according to the set period. For example, if a 1Khz PWM is required, you can configure period=48M/1K=48000 2.4.5 Platform module Platform->Interrupt Controller->IntCtrlConfig0, enable SIUL_1_IRQn, and add Handler as: SIUL2_EXT_IRQ_8_15_ISR Note that this SIUL2_EXT_IRQ_8_15_ISR is not written randomly, but must correspond to the one in Siul2_Icu_Ip_Irq.c, otherwise an error will be reported. Fig18 Different interrupts have different interrupt service functions. You need to find the function name defined in the code and fill it into EB. EB configuration is as follows: Fig 19 2.4.6 Port module The configuration of 8 pins is as follows: Fig 20 As you can see, there are 3 main EMIOS PWMs, one input interrupt, one output GPIO, and two output LCU complementary PWMs. 2.4.7 Pwm module Mcl configures the counter clock channel of EMIOS. The PWM channels to be output need to be configured in the Pwm module and linked to the MCU clock source and the emios counter bus source in Mcl. (1) Pwm->PwmEmios Add two groups for the corresponding EMIOS modules. For example, this article uses EMIOS0 and EMIOS1, so two need to be added: Fig 21 For PwmEmios_1, there is one channel, and the configuration is as follows: Fig 22 PwmEmiosBusRef: /Mcl/Mcl/MclConfig/EmiosCommon_1/EmiosMclMasterBus_0 Fig 23 As you can see, the busRef of PwmEmios_1 here is Emios_ch_23 in Mcl, that is, BusA. That is to say, the bus reference clock used by EMIOS1_CH12 comes from EMIOS1_CH23, that is, Bus A. There are two channels configured in PwmEmios_0, and the configuration is as follows: Fig 24 Fig 25 The bus reference clock used by EMIOS0_CH4 comes from EMIOS0_CH22, which is Bus F. Another EMIOS0 channel: Fig 26 Fig 27 The bus reference clock used by EMIOS0_CH2 comes from EMIOS0_CH0, that is, Bus B, so select Bus BCDE. At this point, we can clearly understand the relationship between the real PWM output channel and the internal MCL Emios counter bus channel. (2)Pwm->PwmEmios With the specific information of PWM configured above, we can directly configure the PWM channels. There are three channels in total: PWM0, PWM1, PWM2, which are also the flags needed in the code. Fig 28 2.5 main code   #include "Pwm.h" #include "Mcu.h" #include "Port.h" #include "Mcl.h" #include "Platform.h" #include "Dio.h" #include "Icu.h" //#include "check_example.h" #define NUM_BLINK_LED (uint32)10U #define DELAY_TIMER (uint32)5000000U #define MCL_EMIOS_1_CH_23 (uint16)279U #define MCL_EMIOS_0_CH_22 (uint16)22U Mcl_LcuSyncOutputValueType PWM_OutputList[2]; volatile uint8 UserCountIrqCH0; void TestDelay(uint32 delay); void TestDelay(uint32 delay) { static volatile uint32 DelayTimer = 0; while(DelayTimer<delay) { DelayTimer++; } DelayTimer=0; } void User_EdgeDetect(void) { /* increment IRQ counter */ UserCountIrqCH0++; if(UserCountIrqCH0 % 2 == 0) { Pwm_SetDutyCycle(PwmChannel_2, 0X6000); } else { Pwm_SetDutyCycle(PwmChannel_2, 0X2000); } } int main(void) { uint8 num_blink = 0U, i = 0; uint16 duty_cnt = 0; UserCountIrqCH0 = 0U; /* Initialize the Mcu driver */ Mcu_Init(&Mcu_Config_VS_0); /* Initialize the clock tree */ Mcu_InitClock(McuClockSettingConfig_0); /* Apply a mode configuration */ Mcu_SetMode(McuModeSettingConf_0); Platform_Init(NULL_PTR); /* Initialize all pins using the Port driver */ Port_Init(&Port_Config_VS_0); /* Initialize Mcl driver */ Mcl_Init(&Mcl_Config_VS_0); /* Initialize the Icu driver */ Icu_Init(NULL_PTR); Icu_EnableEdgeDetection(IcuChannel_0); Icu_EnableNotification(IcuChannel_0); /* Initialize Pwm driver , after that Led on*/ Pwm_Init(&Pwm_Config_VS_0); /* PTA29 duty cycle is 50% */ Pwm_SetDutyCycle(PwmChannel_0, 0X4000); // PTB16,pwm1 , emios0_ch4, use trigmux LCU output 2 Complementarity PWM Mcl_LcuSyncOutputValueType lcuEnable[2U]; lcuEnable[0].LogicOutputId = 0; lcuEnable[0].Value = 1U; lcuEnable[1].LogicOutputId = 1; lcuEnable[1].Value = 1U; Mcl_SetLcuSyncOutputEnable(lcuEnable, 2U); TestDelay(DELAY_TIMER); /* Set new period for all channels used external counter bus */ Mcl_Emios_SetCounterBusPeriod(MCL_EMIOS_1_CH_23, 4800, FALSE); // pwmchannel_0 10Khz Mcl_Emios_SetCounterBusPeriod(MCL_EMIOS_0_CH_22, 1200, FALSE);// for PwmChannel_1, 20Khz // PWM0: 10kHZ //PWM1: 20KHZ //PWM2:1KHZ // PTA29 10kHZ /* PTA29 duty cycle is 50% */ Pwm_SetDutyCycle(PwmChannel_0, 0X4000); /* Setup new duty cycle to the pin*/ Pwm_SetDutyCycle(PwmChannel_1, 0x4000); for(i=0; i <= 10; i++) { duty_cnt = i * 0x800; Pwm_SetDutyCycle(PwmChannel_0, duty_cnt); TestDelay(DELAY_TIMER); } /* Using duty cycle 0% and 100% to Blink LED */ while(1) { /* pwm1 when duty cycle is 75% */ Pwm_SetDutyCycle(PwmChannel_1, 0X6000); //Led off Pwm_SetDutyCycle(PwmChannel_0, 0X0000); //red off Dio_WriteChannel(DioConf_DioChannel_Digital_ledgreenPTA30, STD_HIGH); //green on TestDelay(DELAY_TIMER); /* pwm 1 when duty cycle is 25% */ Pwm_SetDutyCycle(PwmChannel_1, 0X2000); //Led ON Dio_WriteChannel(DioConf_DioChannel_Digital_ledgreenPTA30, STD_LOW); //Green OFF Pwm_SetDutyCycle(PwmChannel_0, 0X8000); //RED ON TestDelay(DELAY_TIMER); num_blink++; } /* De-Initialize Pwm driver */ Pwm_DeInit(); //Exit_Example(TRUE); return 0U; }   3. Test Result After power-on, the onboard red light flashes, then gradually turns bright from off, and flashes alternately with the green light. Test PWM1 PTB16: EMIOS0_CH4, the waveform is 20Khz after stabilization, and the duty cycle changes alternately between 25% and 75%. PWM2 PTB14: EMIOS0_CH2, after stabilization, the frequency is 1KHZ, and as the onboard SW5 is pressed, the duty cycle changes alternately between 25% and 75%. Test PTD3, PTD2, it can be seen that it is a pair of complementary waveforms, and the frequency is the same as PTB16, and the duty cycle change rule is also the same. It can be seen that the key interrupt, 3 main PWM, and 2 LCU PWM in this article are already working. Fig 29 Fig 30  
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******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************
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Due to K3 hasn't been mass-produced yet, this content is moved to S32K3 Internal forum: https://community.nxp.com/t5/S32K3-Internal-Community/S32K3-Low-power-lab/ta-p/1280219 Any question, pls contact Jeremy.he@nxp.com.
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Hi,    Firstly, you should get the flash block size of your S32K3xx. Table in RM could be the reference.    Secondly, you should know that there are super sector and sector in S32K3xx.   Sector                    Subdivision of the Flash Block that is independently erasable. Sector Size is always 8 KB. Super sector          Subdivision of the flash block that includes a group of sectors. Super Sector Size is always 64 KB, and consists of 8 sectors.    Thirdly, based on the information of PFCBLKx_SSPELOCK in RM, you can calculate the numbers of super sector and sector in each flash block.   For example in S32K312, it has 2MB flash totally and each block is 1MB. So, in each 1MB, its first 768KB is with super sector granularity. The numbers of super sector is 768/64=12; the followed sector number is 256/8=32. Cheers! Oliver
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Hi,     I would like to share with you the follow solution for S32K14x which could be attached while couldn't be re-programmed and stopped at RAM initializing.     If you met the issue as title, please check the SIM_CHIPCTL's value in IDE with attach function. Maybe you can find that the value is 0x0, which is not as default value after reset which is 0x0030_0000.     If you check the meaning on SIM_CHIPCTL, you can find that SRAMU and SRAML are retained across resets.  To solute the issue, you should add 'WRITE_LONG=00300000/40048004/ ;' in front of it the algorithm (it's better after reset) of freescale_s32k144f512m15_pflash_dflash_eeprom.arp which is at  'C:\NXP\S32DS_ARM_v20\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_3.3.3.201712132114\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx' After that, you can download your project as normal. Cheers! Oliver
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