PN5190-NTAG X DNA High Speed Communication Demo: This article describes important feature of these two chips when interacting with each other at contactless interface: Passthrough demonstrator at high bit rates for ISO/IEC14443-A between PN5190 and NTAG X DNA Scope of demonstrator: ▪ Demonstrating a unique feature of NXP Semiconductors. High bit rates for ISO14443 communication (up to 848 kbps) between a PN5190 reader IC and an NTAG X DNA when connected to MCXA153 host MCU, when simulating the transmission of a dummy file as big as 101 kbytes. ▪ Through MCUXpresso console, the user can configure the contactless bit rate: 106 kbps 212 kbps 424 kbps or 848 kbps The amount of data is fixed in this demo. ▪ transmission mode is implemented from NFC reader library at K82 MCU built in the PNEV5190BP evaluation kit. On the other side, NTAG X DNA + Level shifter (represented by evaluation kit NTAG-X-DNA-EVAL) is connected to a Freedom Board, equipped with MCXA153 - FRDM-MCXA153). ▪ The PN5190 prints on the MCUXpresso console (debug mode) the outcome of the transaction and average baud rate achieved. ▪ In order to handle full file transmission from K82 to MCXA153 (MCU <-> MCU communication), we are using NTAG X DNA GPIO wires as well as proper settings on the NTAG X DNA <-> MCXA153 side and hard coded timeout on the PN5190 + MCU side. For more details, please open attached file PN5190_NTAGXDNA_MCXA153_DualInterface_HBR_Demo_SetupInstructions_Q32025.pdf. Required hardware and software enablement: Hardware ▪ PNEV5190BP Development Board ▪ FRDM-MCXA153 Development Board ▪ NTAG X DNA Development Board ▪ 2 x USB micro cables (for PNEV5190BP dev. br., one for DC power, other for Jlink debug on MCUxpresso IDE) ▪ 1 x USB-C cable (for FRDM-MCXA153 dev. br., only for DC power) Software ▪ MCUxpresso project (firmware Source Code) for PNEV5190BP is attached to this article, containing keywork pn5190: pn5190-ntagxdna-highspeed-demo1.zip. Instructions will be given in from future release of NFC Reader Library public v07.14.00 (NxpNfcRdLib_PN5190_v07.14.00_Pub.zip). ▪ SDK_2.x_FRDM-K82F is already included in bundle mentioned above. ▪ Firmware Source Code for FRDM-MCXA153 is attached to this article, containing keyword MCXA153: MCXA153.zip ▪ MCUXpresso IDE recent version, for instance v24.12.148 or above. Demonstrator bring up: Hardware assembly for FRDM-MCXA153: • Connect NTAG X DNA to level shifter (see Fig. 1) • Connect bundle NTAG X DNA+ level shifter bundle to flat cable (contained in demokit box) to FRDM-MCXA153 according to Fig. 2. • Make sure each wire is connected to proper position in Arduino socket: - black wire IO2 goes to J1-14 - white wire IO1 goes to J1-16 - gray wire SCL goes to J2-20 - violet wire SDA goes to J2-18 - blue wire GND goes to J3-14 - green wire VCC goes to J3-8 • Connect FRDM-MCXA153 via J15 (MCU-Link) to your computer (Debug Link Input), for the first time that you have to flash binary in it. Then after storing binary, you may just connect USB-C cable from a power supply to J6 port (named Ext-debugger). • No additional power source is needed. Hardware assembly for PNEV5190B: • Connect two USB micro cables to PNEV5190B board for power, flashing firmware and UART connection (see Fig. 3): • microUSB on J7 is necessary for DC power. Check that jumper J9 is in the position USB dc supply • microUSB on J20 is the Jlink debug port, and it will be connected to your Windows computer, where MCUxpresso has been installed. • Red LED indicates power is enabled • Green LED debugging/UART status Alternatively, if you have a DC power supply (voltage above 7 V), you may change Jumper J9 to Ext power supply, and avoid using second microUSB cable. Software loading on FRDM-MCXA153: 1. Create a new workspace for MCXA153 MCUxpresso example: 2. Make sure you have installed MCXA153 SDK: - install MCXA153 SDK which can be downloaded from: https://mcuxpresso.nxp.com/  3. Unzip "MCXA153.zip" file in local C: directory, with reasonable path length. 4. Import existing projects from file system, into MCUXpresso IDE: 5. Select proper root directory (keyword is MCXA153): 6. Click "Finish" 7. If you get this warning, simply click "OK": 8. Highlight project, click "build", and check that there are no errors: Finished building target: MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf Performing post-build steps arm-none-eabi-size "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf"; # arm-none-eabi-objcopy -v -O binary "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf" "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin" ; # checksum -p MCXA153 -d "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin";    text        data         bss         dec         hex     filename   23524          20        3684       27228        6a5c      MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf 16:27:26 Build Finished. 0 errors, 0 warnings. (took 5s.787ms) 9. Now, flash the binary into MCXA153 MCU using GUI Flash tool; select suitable  MCUxpresso probe (CMSIS-DAP). Make sure USB-c cable is connected to J15 in Freedom board (MCU-link port for flashing FW). 10. Select binary file *.axf as indicated below: It may happen that your MCXA153 has outdated FW on CMSIS-DAP, but you can continue, it will make no harm; click then Ok to flash. 11. After flashing, reboot your board. Following LEDs should be on: - D15 RGB led should be "white" lit. - D7 should be blinking "red" - D8 and D4 should be "green" lit. D15 will blink "white" only during file transmission. You may disconnect USB-c from J15 (the one used with MCUxpresso for flah and connect it to J8. Then, plug the other cable tip to any USB  5 volt battery charger. Now your Freedom board FRDM-MCXA153 is ready to receive data from PNEV5190 board, once project will be imported too in MCUxpresso. Software loading on PNEV5190BP: 1. Unzip *.zip file in directory with reasonable path length. 2. Import existing projects from file system 3. Select Example 12 "NfcrdlibEx12_NTAGXDNA" 4. Uncheck the choice "copy projects into workspace" 5. Install SDK_2.x_FRDM-K82F if not yet done. Such SDK is included in project file tree: • ...Examples\Platform\SDK_2.x_FRDM-K82F • This specific SDK can be obtained from https://mcuxpresso.nxp.com/ by selecting following K82F tab related "PN5180" : • FRDM-K82F-PN5180 (MK82FN256xxx15) • SDK 2.0 is no longer officially available, but SDK 2.2 and newer are backward compatible and recommended by NXP • Build project and check that there are no errors ("warnings" are allowed). • Start Debug session to see available bitrate options on the console. Hardware combination of PNEV5190B and NTAG X DNA connected to FRDM-MCXA153: Under MCUXpresso: 1. Click "Debug" icon on quick access left panel. Accept agreement in case of J-Link tool: 2. Click on icon "Run" on top side of MCUxpresso, and observe the following on "Console" tab: [MCUXpresso Semihosting Telnet console for 'NfcrdlibEx12_NTAGXDNA_mcux JLink DebugFRDMK82F' started on port 59973 @ 127.0.0.1] SEGGER J-Link GDB Server V8.12a - Terminal output channel *** NTAG X DNA Example *** Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : Menu options when two boards have NFC antennas facing each other: There are 5 options in console menu as soon as you "Run" the debug. 1 - options from 1 until and including 3 are related to crypto functionality (symmetric and asymmetric) and are out of the scope of this article. 2 - Then option 5 is used for the first time that you are configuring your NTAG X DNA product. It will set registers and GPIO properly for High bit rate transfer. Once you have run option 5, then go to option 4: 3 - Four options of bitrate are available for transfer a fixed amount of data from host (K82) to NTAG X DNA MCU (MCXA153) using PN5190 as tunnel: Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : Demonstration flow: Once one of these option is selected, reader is ready to detect a tag. ▪ When tag is detected, reader configures selected bitrate and starts data exchange. ▪ Blinking RGB LED D15 indicates transfer ongoing and the console shows a progress. Here are some results of transaction at the different bit rates and data sizes offered by this demonstrator: 1 - 106 Kbps - Baud rate 7.6 kBytes/s - elapsed time: 13.99 s Type A Tag is discovered. ***** Perform Transfer sequence ******* Select Application Successful Select File Successful Data transferring NFC -> NTAG X DNA -> Microcontroller... Amount of data exchanged 101200 Bytes, Baudrate (total) = 7.6 kB/s, Time = 13.99 s Please Remove the Card   After removing the card, K82 firmware starts again prompting for a new selection, in the previous menu. First select 4 again and then chose again another new baud rate: 2 - 212 Kbps - Baud rate 10.51 kBytes/s - elapsed time: 9.39 s 3 - 424 Kbps - Baud rate 13.92 kBytes/s - elapsed time: 7.90 s 4 - 848 Kbps - Baud rate 16.60 kBytes/s - elapse time: 5.95 s   Using Example 12 of NFC Reader Library v.07.14.00 to prepare High Speed demo on PNEV5190BP and NTAG X DNA: 1. Go to https://nxp.com web site and type "NFC Reader Library" in Search tab. Follow the instructions until you get to this screenshot: 2. Start by downloading NFC Reader library V.07.14.00 from NXP website; agree with Terms and Conditions. Then download the bundle to your local C: drive: 3. Click on “down arrow” to download version 07.14.00. Once zip file is received, unzip previous bundle to a local drive directory.   4. Start a new workspace, then choose "Import from Existing Projects into Workspace": 5. De-select all useless Examples and keep only example 12; please including all other essential items; click "Finish": 6. If you find this error, it means you need to install K82F SDK: 7. Click install, then MCUxpresso SDKs pages will open. Select K82F from Processor tab: Click “Install” button; after installation is completed, you will get a screen showing all installed sdk's. Afterwards you may get the prompt "Make SDK persistent"; just click ok. 8. Highlight project NfcrdlibEx12_NTAGXDNA_mcux and click build; check if there are errors: Finished building target: NfcrdlibEx12_NTAGXDNA_mcux.axf Performing post-build steps arm-none-eabi-size "NfcrdlibEx12_NTAGXDNA_mcux.axf" ; arm-none-eabi-objcopy -O binary "NfcrdlibEx12_NTAGXDNA_mcux.axf" "NfcrdlibEx12_NTAGXDNA_mcux.bin" ; #checksum -p MK82FN256xxx15 -d "NfcrdlibEx12_NTAGXDNA_mcux.bin"    text        data         bss         dec         hex     filename  222400          92       86816     309308       4b83c      NfcrdlibEx12_NTAGXDNA_mcux.axf 17:32:59 Build Finished. 0 errors, 3 warnings. (took 33s.718ms) 9. Now, check in MCUxpresso the tab Windows > Preferences > Run/Debug. Untick the box related to General Options Build (if required) before launching; it will save you much time! Then, click button “Apply and Close”. 10. Using this Example 12 as it is given by NXP in this library, when you will debug it, you will realize that there are only 3 Menu options related to NTAG X DNA cryptography (and no high speed options). In order to “unlock” the high-speed demo option, please do the following. 11. Go to Quick Settings → Defined Symbols and open it in a new window: Now add after last symbol, the following line: "PH_EX12_ENABLE_DUALINTERFACE_HBR", by clicking on “add button” ("+" shown in green) on top right side of above window; add it manually then click OK two times. Now, build Ex12 again and check that there are no errors. 12. Debug Example 12, then press Run button and check if Console has 5 options in its Menu: Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator     with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder     with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 13. Let's focus on the last two options: 4 – perform HBR (high bit rate) transfer, and 5 – Configure your NTAG X DNA for HBR. 14. If this is the first time you are using this NTAG X DNA connected to MCXA153, then choose option 5 so that PN5190 will write proper configuration data to NTAG X DNA next to it. For this reason, turn on NTAG X DNA connected to FRDM-MCXA153 board (after powering it up with a simple 5V-USB source), and place NTAG X DNA antenna over PNEV5190BP board antenna (connected to MCUxpresso), as in picture shown above. Enter your option : 5 Ready to detect Type A Tag is discovered.       Select NDEF Application Successful       Authenticate Application Successful       SetConfig Successful       StdDataFile with File ID 0xE106 already exists. Please Remove the Card 15. Remove NTAG X DNA antenna from PN5190 antenna, until you get back to initial menu. Then, choose option 4 on previous menu: 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 4  Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : 16. Now, choose the lowest speed "1"; check final result: Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 5.72 kB/s, Time = 17.25 s Please Remove the Card 17. Separate both antennas, and then, choose option "2"; check final result: Enter your option : 2 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller… Amount of data exchanged 101200 Bytes, Baudrate (total) = 10.49 kB/s, Time = 9.41 s 18. Separate both antennas, and then, choose option "3"; check final result: Enter your option : 3 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 13.89 kB/s, Time = 7.11 s Please Remove the Card 19. Separate both antennas, and then, choose option "4"; check final result:  Enter your option : 4 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 16.57 kB/s, Time = 5.96 s Please Remove the Card Conclusions: This demonstrator HW & SW can show that high speed interaction can be achieved between PN5190 (NFC Front end) and NTAG X DNA (NFC connected tag), making use of available commands described in its product support package (https://www.nxp.com/products/NTAG-X-DNA). Disclaimer:All SW available here is aimed only for evaluation purposes and NXP disclaims any direct or indirect liability damages, since referred SW bundles are not yet official part of PN5190/NTAG X DNA standard product support packages currently available at nxp.com.  

Step 1:  Disable the DCDC in settings (Valid for PNEV5190B and OM27642EVK) Write 0x21 into EEPROM PWR_CONFIG (address: 0x0000) This disables the DCDC. & selects that the VUP must be supplied with the same supply voltage as VBAT = VBATPWR. Do not enable RF afterwards, before the hardware is modified properly! Enabling the RF without supplying the VUP might kill the PN5190/PN7642! Step 2: Supply VUP = VBATPWR  Connect jumper J13 positions: 1-2: This supplies the VUP with VBATPWR = 3.3V PN5190 EVK: Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.    PN7642 EVK:  The OM27642EVK does not require any jumper settings (DC-DC is not used by default), the User must only disable DC-DC in EEPROM (address 0x0000, value 0x21) Then you can turn-on RF and perform ULPCD   Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.  Also, R8 shall be placed   

LPCD (Low Power Card Detection) works on the principle that the I and Q values are extracted from the RF signal captured on the RX pins. These values are then compared with the I and Q data obtained using LPCD calibration. If the difference is greater than the chosen I and Q threshold, the load is detected and the IC wakes up.  1// LPCD Way of working  Run LPCD Calibration  It is recommended to use an external power supply to supply the EVK board. If the USB supply is used, the value can fluctuate because of the transition effects.  Run "Single LPCD" and check the performance  Adjust the I and Q thresholds  Low value -> Better detection range, more false wake-ups  High value -> Worse detection range, fewer false wake-ups  The number of samples, RSSI, and VDDPA parameters typically remain at their default values.  2// Auto LPCD  When the "Auto LPCD" is used, the LPCD algorithm always performs LPCD Calibration before entering the LPCD. 3//Semi-autonomous LPCD mode (PN5190 only)   The user can evaluate the I and Q values behaviour under loaded/unloaded conditions. Based on that, the LPCD threshold can be properly selected.  Use the same "Register" RSSI Target and Hysteresis as for "EEPROM" Calibrate LPCD Run "Endless I/Q read"  Check how the I and Q values change With no card/object in the antenna proximity  with a NFC card/object in the antenna proximity

  Some customers are trying to update the user firmware on PN7642 through host interface and using “DownloadLibEx1” demo,  and they are using SFWUMaker to create .esfwu file from .bin followed the readme file but failed to do a firmware update. Here is a step-by-step guide to do it. I will use the SDK led blinky demo,  and generate an Esfwu file , and program it into PN7642 board with LPC5516 host.  Led blinky demo is in PN7642_MCUXpresso_SDK_02-15-00_PUB.  You can download it from PN7642 product page.  Single-Chip Solution with High-Performance NFC Reader, Customizable MCU and Security Toolbox | NXP Semiconductors Step 1: compile pnev7642fama_led_blinky demo Please make sure the flash size is 180KB.  By default,  the output flash size is 180KB with MCUXpresso IDE.     Step 2: Bin file generation The binary (.bin) file is not generated by default, we can do it manually by doing following: Build your target application Open the debug/release folder in MCUXpresso Right-click on the *.axf file Choose 'Binary Utilities' → 'Create binary' in the menu The .bin should appear   Step 3: Make an ESFWU file To convert a bin file to an ESFWU file, we can use the ESFWU Maker Utility (sw810311). It can be downloaded from PN7642 product page. It is a secure file, and you need to have an active NDA to get it.  To run this utility, the toml file is very important.  You need to change the output name and binary name according to your project ,  and  you need to use the correct aes_root_key. For other parameters, we left them unchanged.   3.1   change the output name and binary name   3.2 set the correct aes_root_key The application flashed via SWD is a bin file and NOT encrypted neither is it flashed with our bootloader. The .esfwu file via host interface is encrypted and flashed by our own bootloader.  The keys have to be valid, else the bootloader will not be able to decrypt the received file. Please make sure we are using the right keys to create the user application firmware.  This is crucial and without it, it won’t work anyways. The default keys are mentioned in the datasheet as transport keys. See below picture.  But it is highly recommended to provision your own keys!  Please have a look at the secure key mode application note for further information on that.        If you are not sure whether you have provisioned the root key or not, you can check the SKM state by running SKM demo. if the root key is provisioned, please use the provisioned root key.  From below picture, I can see that the app_root_key is  not provisioned, so I use the default transport key.     3.3  use the EsfwuMaker command to generate the Esfwu file.     After this command, we can get the esfwu file.       Step 4: Secure firmware download   We use the firmware download example to update the PN7642 firmware.  It is in the host software package, it  holds examples to be used with LPC55S16 and MCUXpresso, to interact with the PN7642. The LPC55S16 Host Software can be download from PN7642 product page. LPC55S16 Host Software Version 02.01.00 (nxp.com) To run the demo, we need to edit the firmware location.  In file DownloadLibEx1.c,  about line 60.       Please set the correct hardware settings as below.  we have to stack the PNEV7642A Rev-B development board on top of the LPC55S16-EVK board. Align Pin.1 of J36 of the PNEV7642A Rev-B development board with Pin.1 of J9 of the LPC55 board. The last 4 pins, 17 - 20, of J12 of the LPC board are not connected. As well as pin 1-4 of J10 stay unconnected, as below picture shows.       Run the firmware download Demo with LPC55s16,  see the log output below.  Choose option “6” to update your application firmware. The update may take a while.  At the end, a successful update is indicated by the prompt of “Successful firmware upload ”.         To verify it is successful, we can run this demo, please keep J65 open.  you will see the D7 (RED LED) blinky (0.5 HZ rate). If you need the pnev7642fama_led_blinky.esfwu, please let me know.    

Extended NFC Factory Test Application includes:  Get Current value (current measurement in mA) DPC Check (Available from FW. Version 12.50.06) Get AGC Value  Get AGC Value NFCLD (AGC value reading with fixed NFC Level Detector level) Dump EEPROM settings    How to get it:  Just download the app from Github. Replace the "NfcFactoryTestApp.c" with the file which is here in the attachment.  Run the application as described in ->AN13287.   Tomas Parizek  Customer Application Support 

  NXP offers FW update code as part of the SW6705.   All PN7160 FW versions including ".c" files are available on PN7160 Github.    PN7160 is typically delivered with the initial FW 12.50.05. To ensure full reliable functionality, it is highly recommended to update the FW on 12.50.09 (or latest). The FW update might be also helpful if you need to restore the default EEPROM settings.  The FW source data are inside the sFWudpate folder.  phDnldNfc_UpdateSeq.c -> FW Version 12.50.05 phDnldNfc_UpdateSeq_12_50_09.c -> FW Version 12.50.09 The phDnldNfc_UpdateSeq.c is executed, which means what is inside of this "C" file is pushed to the PN7160 EEPROM.  So, if you want to update from 12.50.05 to 12.50.09. You need to copy content from phDnldNfc_UpdateSeq_12_50_09.c to The phDnldNfc_UpdateSeq.c.  Also, make sure that the content in phDnldNfc_UpdateSeq_12_50_09.c is commended.   Once that's done, you can debug the code.  Then you can check the progress in "Terminal"    Tomas Parizek  Customer Application Support 

There is a basic GUI for PN7160 RF Settings available.

In the case, the Reader output power cannot be further reduced with the help of the tuning and TXLDO settings (e.g. EMI reasons)  Then further reduction can be done using DPC settings. The idea is to use just one DPC entry and adjust the GSN value as shown below: DPC Settings:    The DPC Entries (1-19) have been deactivated (Index Activate ->0), and only Entry 00 stays active.    An example (RF Field measured using a scope probe): No DPC, TXLDO 5V    NO DPC, TXLDO 2.7V   DPC Activated, One Entry, GSN-> 0x05   DPC Activated, One Entry, GSN-> 0x01   Please consider that the reading performance will be impacted. 

How to set the RF Settings can be found in -> https://www.nxp.com/docs/en/application-note/AN13218.pdf The list of the default values + values which shall not be changed is available in the attachment.  Tomas Parizek  Customer Application Support 

The PN5180 offers a low-power card detection (LPCD) feature, which allows to power down the reader for a certain period of time to safe the energy. After this time the reader must become active again to poll for the cards. If no card has been detected, the reader can go back to the power down state. PN5180 LPCD cycle time includes standby time and VBAT time. In a normal case, standby time is 200ms (user can define it),   standby current is 15uA, VBATON current is 7500uA, FieldON current: 200mA.  Average current is about 200uA, it depends on your settings and application.   This article describes how to configure PN5180 LPCD using NXP Cockpit Tool and using NXP NFC Reader library.   1  PN5190 LPCD Overview PN5180 LPCD operates in two modes: auto calibration mode and self-calibration mode. Auto calibration mode:  everything done automatically Self-calibration mode:   calibration must be done manually before starting the LPCD.   1.1  Auto Calibration Mode ( 00b) The LPCD calibration is done automatically when the LPCD is started, using the gear and threshold as defined in the EEPROM. This mode always uses the same gear for the LPCD, and is the fast and easiest way to start the LPCD.  It is recommended to choose a gear, which always keeps the ITVDD and field strength limits, so normally, the highest gear number. Auto calibration mode is most commonly used, it is a standard use case. Below parameters need to be configured correctly in EEPROM   LPCD_REFERENCE_VALUE       LPCD_REFVAL_GPO_CONTROL      LPCD_THRESHHOLD  ( 0x37) LPCD wakes up, if current AGC during “ping” > AGC Reference + LPCD_THRESHOLD or< AGC Reference -LPCD_THRESHOLD Minimum LPCD_THRESHOLD = 03…08 (very sensitive) Maximum LPCD_THRESHOLD = 40 … 50 (very robust)    LPCD_FIELD_ON_TIME  (0x36) RF on time in 8µs, excluding the fix time .   Fix time = 62µs 01 => RF on = 70µs 02 => RF on = 78µs 03 => RF on = 86µs 10 => RF on = 190µs   1.2  Self Calibration Mode (01b) The LPCD calibration must be manually triggered, with reading or writing into the AGCREF_CONFIG register.   Reading from this register - without prior writing - starts an LPCD calibration. The calibration is executed using the gear which is resulting from the actual DPC setting under the actual antenna detuning condition. AGC_GEAR is used in the LPCD self-calibration.   Reading from this register - without prior writing - delivers in addition to the AGC_GEAR value the AGC_VALUE. The AGC_VALUE is used in the LPCD self-calibration. Writing to this register: Writing data to this register is required before starting the LPCD in Self-calibration mode. Either the previously read AGC_GEAR or a user-defined gear can be chosen. The previously read AGC_VALUE has to be written in any case. Writing data to this register defines the values for AGC_GEAR without taking the actual detuning condition into account. The value of AGC_GEAR to perform an LPCD calibration which derives the AGC_VALUE. This AGC_VALUE and the AGC_GEAR are used in the LPCD self-calibration.   Self-calibration mode always requires a Read AGC_REF_CONFIG, followed by a write AGC_REF_CONFIG, using the previously read AGC_VALUE.   The LPCD calibration can be done in two different options: Option 1:  Read AGC_REF_CONFIG register:  This command executes a standard RF Field on. So depending on the load condition the DPC adjusts the output power. The final gear is take as gear for the LPCD.  This option guarantees that the maximum output power is taken for the LPCD.   Option 2: Write AGC_REF_CONFIG register: This command executes a LPCD calibration ping with the gear number, as defined in the AGC_REF_CONFIG, bit 10:13. This option allows a flexible use of any of the defined gears for the LPCD.   PN5180 LPCD self-calibrate is executed, using Gear -> AGC_REF_CONFIG (Register) Threshold -> LPCD_THRESHOLD (EEPROM) RF on time-> LPCD_FIELD_ON_TIME (EEPROM)   2  How to configure PN5180 LPCD with Cockpit The NFC Cockpit allows the configuration and test of the low power card detection of the PN5180 as shown in below picture. The LPCD parameter, which are stored in the EEPROM, can be changed and the LPCD can be started. The LPCD tab allows to directly define and write the related EEPROM addresses:   LPCD Gear #: Defines the gear number, which is used for the LPCD in auto calibration mode, stored in addr. 0x34, bit 0:3 Threshold Value: Defines the threshold window, As soon as the AGC value during the LPCD ping exceeds the AGC reference value + threshold window, the IRQ will be raised and the PN5180 wakes up. Field On Time:  Defines the ping length Standby time :  This value defines the time between two pings in ms. FieldOn Current: This value is ITVDD under the loading condition, when RF field is on with the used gear. This value does not have any influence on the LPCD execution, but simply is used to estimate the overall  average current consumption. This current estimation is calculated, when the LPCD is started.         3   How to configure PN5180 LPCD with NXP NFC reader library. The LPCD works in two phases: First the standby phase is controlled by the wake-up counter (timing defined in the instruction), which defines the duration of the standby of the PN5180. Second phase is the detection-phase. The RF field is switched on for a defined time (EEPROM configuration) and then the AGC value is compared to a reference value.   Below is the flow chart for PN5180 LPCD          

This document provides a step by step guide of how to use the CLRC663 plus with i.MX RT1050. For this purpose, we need to port the NFC Reader Library to i.MX RT1050.  There are two zip files attached to this document: 1. "NFCReaderLibrary_IMXRT1050_Porting Guide +DAL_IMXRT1050_BLE-NFC-V2.zip" : This folder is pre-configured for those who want to use BLE-NFC-v2 board with i.MX RT1050. 2. "NFCReaderLibrary_IMXRT1050_Porting Guide +DAL_IMXRT1050_CLEV6630B.zip" : This folder is pre-configured for those who want to use CLEV6630B board with i.MX RT1050. A video describing how to use i.MX RT1050 with CLRC663 Plus Family is available by clicking this link (Using i.MX RT 1050 with CLRC663 plus family |NXP ) as well. 

As NFC reader library 5.12 also supports PN5180, switching the NFC frontend from CLRC663 to PN5180 is quite easy based on previous porting. The porting also includes the hardware settings and software modification. Hardware Setup for porting: a) Remove resistors on PNEV5180B to disconnect the onboard lpc1769 from PN5180, following steps on page 16 of https://www.nxp.com/docs/en/application-note/AN11908.pdf  b) Connect LPCXpresso board for LPC11U37 with PNEV5180 as below: Software Modification for porting: 1. Make a copy of Board_Lpc11u37Rc663.h , and change its name to "Board_Lpc11u37Pn5180.h", and import it into the DAL/boards folder. 2.Change the source code in the header file as below: 3. Add two more pins' definition and configuration for BUSY and DWL pins of PN5180, and new configuration for reset pin. and modify the reset logic: 4.Change the IRQ interrupt trigger type to rising edge. 5.Include this header file in BoardSelection.h 6.Add this new configuration in ph_NxpBuild_App.h 7.Add this new configuration in phApp_Init.h 8.Add this new configuration in ph_NxpBuild_Platform.h 9.Add this new configuration in Settings. 10.Building result: Testing result:

Based on NFC reader library porting guide for LPC11u37h(Ver 5.12) ,We have a partial ported NFC reader library like below: Now, it is time to port other demos in this project. You may choose any demo, but here NfcrdlibEx2_AdvancedDiscoveryLoop is selected. and similar with before, the first step is creating a new build configuration: then in the project references, choose the LPCopen library for LPC11u37 instead. Change the MCU settings: Change the build settings: Change FreeRTOS portable to cortex M0: Search "PHDRIVER_LPC1769RC663_BOARD" in the source code of "NfcrdlibEx2_AdvancedDiscoveryLoop" project, and you may simply replace it with "PHDRIVER_LPC11U37RC663_BOARD", and there are only two places needs to be fixed. Search "PHDRIVER_LPC1769" in the source code of "NfcrdlibEx2_AdvancedDiscoveryLoop" project, and you may simply replace it with "PHDRIVER_LPC11U37". Most changes are in phApp_Init.c. Also please don't forget to enable optimization for size. Building result: Demo testing result:

The latest NFC reader library supports lpc1769 which is a cortex M3 controller with LPCopen lib supports, so in theory , it should supports other controllers supported by LPCopen, but we have to test this, so we choose , for example, lpc11u37, a cortex M0 based controller for this porting. Platform for this porting: LPC11u37h-Xpresso Rev A: CLRC663 plus based CLEV663B Blueboard 3.0. Please refer to Prepare CLEV663B board for NFC reader library porting  for details. They are connected via LPCXpresso ports. Now we may start the porting, the IDE we use in this porting is MCUXpresso 10.1.1 1. Download and import the latest NFC reader library for CLEV6630B, as it supports CLRC663 plus. For how to import the project, please refer to https://www.nxp.com/docs/en/application-note/AN11211.pdf . 2. Download LPCopen for LPC11u37h and import it as well. 3. Now we may choose some demo in the NFC reader library, for example, the NfcrdlibEx1_BasicDiscoveryLoop, and create new build configuration for lpc11u37h. 4.Select the correct MCU 5.Modify build settings Here we find LPC1769RC663 is defined, so we have to find what is related with this definition in the code and change it/them. Fortunately they are not too many. you may find they are just related with board header file including or something like that, so it is not difficult to modify them. 6. Add new header file for the new board definition 7. add the new board definition 8. As we now use LPCopen lib for LPC11u37h instead, so we have to change the including path. As LPC11u37h is cortex M3 based, so we have to setup FreeRTOS for M0 support: and add the source code for building: 9.Change the link libraries and including path 10.Set the correct ref projects to use LPCopen for LPC11u37h. 11. Some changes in LPCopen library: 1)enable semihosting debug 2) add startup source code for the demo, this C file can be reused/imported from the some lpcopen project. 12. After the above steps, we still have to change the source code in DAL: You know , due to different version of LPCopen library,  some function definition might be changed, and different LPCXpresso boards has different pin connection to the LPCXpresso ports, so it is recommended checking the board schematics and the examples in lpcopen project , find the proper function calls to implement the source codes in the DAL folder. When you finished , the porting is done. 13. As the final image size is greater than 128K, we have enable optimization for size. 14.Demo test ok. Now , we know lpc11u37 can be supported by the latest NFC reader library, so the porting should also be applied for other Cortex M0 controllers, and it is recommended the controller with large internal flash size, better greater than 128K, but anyway, in this porting, I didn't enable the size optimization for LPCopen library, so there might be possibility to have a smaller size image at last...

The latest NFC reader library for CLRC663 just supports LPCXpresso1769 and FRDM-K82 boards, so when customers want to porting the library to other host controller, they have to make a custom board at first, or use OM26630FDK and make a little hardware modification by following the steps described in https://www.nxp.com/docs/en/training-reference-material/NFC-READER-K64F.pdf?fsrch=1&sr=3&pageNum=1 to connect the frontend board with host controller board, but today we will discuss an alternative way. The CLEV663B Blueboard is a pure NFC frontend board, and it supports connecting with LPCXpresso board not limited with LPC1769, the main difference with OM26630FDK is the reader IC, which is CLRC663 not CLRC663 plus, but fortunately they are pin to pin compatible, so we may replace it with CLRC663 plus, and use that board for porting purpose. Before: After: please forgive my poor soldering skill... With this new board and LPC1769 Xpresso board, you may run the latest 5.12 NFC reader library, for example, the NfcrdlibEx1_BasicDiscoveryLoop demo. but you might have the following issue: This is due to ver 5.12 use another set of IO pins to connect with the reader IC, modify pin definitions in Board_Lpc1769Rc663.h can fix this issue. The final result is as below: Please note, it is recommended using NFC reader library ver 4.03 to test the hardware including CLEV663B and LPC1769Xpresso before replacing with CLRC663 plus, and you know, CLEV663B Blueboard is just optimized for CLRC663 , so the matching circuit is not the best for CLRC663 plus, it is just good enough to run the demo, so that we may know if the porting is successful, but if you want to have the best performance with CLRC663 plus, you have to redo the antenna tuning, and you may refer to https://community.nxp.com/docs/DOC-335545 for more details on that topic.

The NFC reader library is supporting multiple frontends. For a customer this might become a more difficult to use, if only the part for one of the frontend chips is needed. To enhance the readability and usability, you can remove the support for not used reader ICs by simply removing the folders below NxpRdLib/comps/phhalHw/src. For instance: if you only want to use the RC663, you could simply delete the folders Pn5180, Rc523. The result would be a library that only supports RC663. This short screen recording shows the steps to reduce the number of supported Frontends.

This page contains information about the supported NXP MCU/MPU and NXP NFC product combinations which have ready to use packages. These can be used as a reference. The table below contains link to where you can find the projects as well.    MCU ↓   NFC IC →  NTAG I²C  plus NTAG 5 PN7150 CLRC663 plus family* PN5180 i.MX RT1050 i.MX RT1050 + NTAG I²C plus i.MX RT1050 + CLRC663 plus   Video: Using i.MX RT1050 with CLRC663 plus family and the NFC Reader Library | NXP  i.MX RT1060 i.MX RT1060 + NTAG I²C plus  i.MX RT1060 + PN7150 i.MX 8M Mini i.MX 8M Mini + PN7150 (Andriod) i.MX 8M Mini + PN7150 (linux-yocto) i.MX 7 Dual Sabre i.MX7 Dual Sabre + PN5180 LPC1769 LPC1769 + CLRC663 plus LPC1769 + PN5180 LPC55S69 LPC55S69 + NTAG I²C plus LPC55S69 + NTAG 5 LPC55S69 + PN7150 LPC55S69 + CLRC663 plus LPC55S69 + CLRC663 plus + SE050 (smart lock) LPC11u37h LPC11u37 + PN7150 LPC11u37h + CLRC663 plus LPC11u68 LPC11u68 + PN7150 LPC82X LPC82X + PN7150 LPC845 LPC845 + CLRC663 plus Kinetis K82F K82F + CLRC663 plus K82F + PN5180 Kinetis K64F K64F + PN7150 K64F + CLRC663 plus Kinetis K63 K63 + PN7150 Kinetis K24 K24 + PN7150 KW41Z KW41Z + NTAG I²C plus KW41Z + NTAG 5 KW41Z + PN7150 *CLRC663 plus family: CLRC663 plus, MFRC630 plus, MFRC631 plus, SLRC610 plus For more information on the NFC products, please visit https://www.nxp.com/nfc