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SPIM module is one of the master interfaces provided by PN7462 , which is a 32-bit ARM Cortex-M0-based NFC microcontroller, and users may use this interface to connect with up to two SPI slave devices. The NFC reader library provides SPIM driver code in phHal/phhalSPIM, and users may directly use the following APIs in their application to implement simple SPI transaction, just like what is done  in the demo of "PN7462AU_ex_phExHif". While this demo has limitation with some SPI nor flash devices, which need a write-read operation in one NSS session, for example, the SPI nor flash device on OM27462 as below: Please note to solder R202 and connect it to 3V3 to make sure nHold pin has pull-up out of POR. The following is one of the command sets this device supports: This command contains 1 write(9F) followed by 3 read operations in one NSS session, but if you implement it with phhalSPIM_Transmit() and phhalSPIM_Receive() as below: status = phhalSPIM_Transmit(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_APPEND_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 2, cmd_buf, PH_EXHIF_HW_SPIM_CRC_OFFSET);    status = phhalSPIM_Receive(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, data_length, dst, PH_EXHIF_HW_SPIM_CRC_OFFSET);" You will have the following result: expected: NSS   \__________________________/ MOSI     CMD A7-A0 MISO                            DATA       actual:                         NSS   \____________||______________/ MOSI     CMD A7-A0 MISO                           DATA so the pulse between the write and read is the problem, and here we have to handle the NSS line manually, with the help of NSS_VAL and NSS_CONTROL bits in SPIM_CONFIG_REG. so the code should be like this:   Assert NSS   status = phhalSPIM_Transmit(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_APPEND_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 2, cmd_buf, PH_EXHIF_HW_SPIM_CRC_OFFSET);    status = phhalSPIM_Receive(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, data_length, dst, PH_EXHIF_HW_SPIM_CRC_OFFSET);"   De-assert NSS The NSS line assert and de-assert function can be implemented with register bit level APIs, just like below:             PH_REG_SET_BIT(SPIM_CONFIG_REG, NSS_VAL);//de-assert NSS             PH_REG_SET_BIT(SPIM_CONFIG_REG, NSS_CTRL);             PH_REG_CLEAR_BIT(SPIM_CONFIG_REG, NSS_VAL);//assert NSS Please also include the following header files in your application code. #include "ph_Reg.h" #include "PN7462AU/PN7462AU_spim.h" Please notice that phhalSPIM_Transmit() and phhalSPIM_Receive() are Rom based function, which clear NSS_CTRL bit by default. We can not change ROM API's behave but fortunately we have phhalSPIM_TransmitContinue() and phhalSPIM_ReceiveContinue() instead. so the final solution will be like below: Assert NSS   status = phhalSPIM_TransmitContinue(1, cmd_buf);    status = phhalSPIM_ReceiveContinue(3, dst);   De-assert NSS This doesn't mean phhalSPIM_Transmit() and phhalSPIM_Receive() are useless, because they can also help up to configure the SPI master interface, if you don't want to use register bit level API to initial the SPIM module manually. Please note to use 1 byte for write/read length to make these two functions work properly. so the whole pseudo code is like below: phhalSPIM_Init(PH_HW_SPIM_TIMEOUT) ; phhalSPIM_Configure(PH_HW_SPIM_SLAVE, PH_HW_SPIM_MSB_FIRST,                 \                                     PH_HW_SPIM_MODE, PH_HW_SPIM_BAUDRATE,  \                                     PH_HW_SPIM_NSSPULSE, PH_HW_SPIM_NSSPOL) ; status = phhalSPIM_Transmit(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_APPEND_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 1, cmd_buf, PH_EXHIF_HW_SPIM_CRC_OFFSET);    status = phhalSPIM_Receive(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 1, dst, PH_EXHIF_HW_SPIM_CRC_OFFSET);" Assert NSS   status = phhalSPIM_TransmitContinue(1, cmd_buf);    status = phhalSPIM_ReceiveContinue(3, dst);   De-assert NSS The following steps show how to create a new project based on NFC reader library, please refer to https://www.nxp.com/docs/en/user-guide/UM10883.pdf  on how to import the NFC reader library. 1. Create a new project after importing the NFC reader library. 2. if you installed PN7462 support package, you will see this: 3. add a link to NFC reader lib: 4. add path and enable NFC reader lib in the project: 5. delete cr_startup.c and create the main code as well as the header file: 6. Build result: 7.Debug result: To fetch the ready demo, please submit a private ticket via the guide of https://community.nxp.com/docs/DOC-329745 . Hope that helps, Best regards, Kan
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This document provides a step by step guide of how to use the CLRC663 plus with i.MX RT1050. For this purpose, we need to port the NFC Reader Library to i.MX RT1050.  There are two zip files attached to this document: 1. "NFCReaderLibrary_IMXRT1050_Porting Guide +DAL_IMXRT1050_BLE-NFC-V2.zip" : This folder is pre-configured for those who want to use BLE-NFC-v2 board with i.MX RT1050. 2.  "NFCReaderLibrary_IMXRT1050_Porting Guide +DAL_IMXRT1050_CLEV6630B.zip" : This folder is pre-configured for those who want to use CLEV6630B board with i.MX RT1050. A video describing how to use i.MX RT1050 with CLRC663 Plus Family is available by clicking this link (Using i.MX RT 1050 with CLRC663 plus family |NXP ) as well. 
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Hello NFC Community! This document demonstrates that multiple records can be also read from a Tag with TagXplorer. Please follow the steps below. Let's begin... Please make sure that you have written more than on record with NXP TagWriter app. For a more detailed explanation on this, please refer to the following document: Writing multiple NDEF text records with TagWrite app  The app can be found and downloaded from the Play Store: NFC TagWriter by NXP - Apps on Google Play  -> Connect the reader in TagXplorer -> Place the card on the reader and press Connect Tag -> Check for NDEF (1) and then, read NDEF (2). The Text Records can be visualized in the NDEF Payload Info below: I hope this is of great help! Ivan R.
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