SW : uboot-imx lf_v2025.04
HW : i.MX 8MP EVK board, Oscilloscope
1. Introduction
This guide explains the concept of DDR clock spread spectrum on the i.MX 8MP EVK platform. Note that the official NXP BSP does not enable this feature by default. Additionally, this guide provides an example code patch and verification steps to enable the LPDDR4 clock spread spectrum feature on the NXP i.MX 8MP EVK board.
2. What is Spread Spectrum?
Spread Spectrum (SS) is a technique used to reduce electromagnetic interference (EMI) by slightly modulating the clock frequency around its nominal value. Instead of operating at a fixed frequency (e.g., 800 MHz), the clock signal is varied within a small range (e.g., ±0.5%). This modulation spreads the energy of the clock signal over a wider frequency band, reducing the peak energy at any single frequency.
In other words, SS does not change the average clock speed significantly, but it helps to distribute the spectral energy, making the system less likely to violate EMI regulations.
3. Why Enable Spread Spectrum on DDR Clock?
Enabling Spread Spectrum on the DDR clock helps reduce electromagnetic interference (EMI) by slightly modulating the clock frequency, lowering peak emissions and making it easier to meet regulatory standards such as FCC and CE. This approach improves system reliability by minimizing interference with other components, offers a cost-effective alternative to hardware changes like shielding or PCB redesign, and is widely adopted in high-speed interfaces such as DDR, PCIe, and SATA to ensure compliance without additional hardware complexity.
4. Related registers
CCM_ANALOG_DRAM_PLL_SSCG_CTRL
Note :
PLL_MFREQ_CTL[19 : 12] : Value of modulation frequency control
The larger the mfr value, the lower the MF value (the slower the modulation); the smaller the mfr value, the higher the MF value.
MF : The frequency of spread spectrum modulation is the speed at which the triangular/sawtooth modulated wave travels back and forth once per second, measured in Hz (commonly in the tens of kHz range). The speed of the spread spectrum "jitter" is determined. Usually, around 20–50 kHz is chosen to make the energy "swipe evenly" within the bandwidth of the EMI test receiver, thereby reducing the peak radiation at a certain frequency point.
PLL_MRAT_CTL[9 : 4] : Value of modulation rate control
The larger mrr is, the larger MR is (the wider the range); similarly, MR is also directly proportional to mfr and inversely proportional to m.
MR : Peak-to-peak percentage of spread spectrum (the percentage of the total range of the clock frequency swinging around the center value). For example, MR = 0.5% means that the frequency swings around the center value by a total of 0.5% (if it is center-spread spectrum, it is usually ±0.25%).The MR determines the depth (width) of the spread spectrum. The larger the MR, the wider the spectral energy distribution and the lower the peak value, but it comes at the cost of jitter/timing margin (timing should be carefully selected for DDR, SerDes, etc.).
5. About Uboot code patch. Please refer the attachment patch file.
At high DRAM frequency, Enable SS may cause not stable problem. So, in this case, I will choose 2400Mbps data clock run the test.
Firstly, we should make sure that our code include the 2400Mbps PLL setting. DRAM data speed is 2400Mbps, the DRAM clock is 1200MHz. So the DDRC PLL clock should set up with 600MHz.
For example, refer the below code.
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), PLL_1443X_RATE(900000000U, 300, 2, 2, 0), PLL_1443X_RATE(800000000U, 200, 3, 1, 0), PLL_1443X_RATE(750000000U, 250, 2, 2, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(600000000U, 300, 3, 2, 0), // 2400Mbps PLL_1443X_RATE(594000000U, 99, 1, 2, 0), PLL_1443X_RATE(400000000U, 400, 3, 3, 0), PLL_1443X_RATE(266000000U, 266, 3, 3, 0), PLL_1443X_RATE(167000000U, 334, 3, 4, 0), PLL_1443X_RATE(100000000U, 200, 3, 4, 0), };
PLL output calculator formula is :
PLL_out = 24MHz*mdiv/pdiv/(2^sdiv)
So, 2400MHz * 300 / 3 / 2^2 = 600MHz
6. Test result
Non Enable SS
Enable SS with 1% MR and Down spread
Enable SS with 2% MR and Down spread
Enable SS with 2% MR and Center spread
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