Issue: During DDR3 Burst Write, the DQS strobe signal must be driven low for a minimum of 0.3 x cycle period on the last data clock cycle before it is released. This ensures sufficient time for the write to be strobed correctly. When measuring this timing parameter, it has often been found to be too short. This may be contributing to write errors on customer boards, depending on the signal layout used by the board. Root Cause: The internal DQS strobe enable signal is controlled by the MMDC, which is tied to the SDCLK clock signal. But the DQS strobe signal can be delayed in the MMDC to match different SDCLK trace lengths by using Write Leveling parameters to ensure the the DQS strobe edge reaches the DDR3 device at the same time the SDCLK edges reaches the device. If the write level delay is too long, the MMDC can crop the end of the DQS strobe signal too short, causing a violation of the Write Post Amble Delay timing specification and potentially leading to  write errors. How much delay in the Write Leveling parameter would cause this problem? The Reference Manual states that a delay around half a cycle may cause problems, but testing on some boards indicates that delays even as short as 1/4 a cycle could cause violations of the Write Post Amble Delay. Solution: The MMDC was designed with the ability to add extra time to the strobe enable period during write procedures. This parameter is referred to as Write Additional Latency. It is found in the MMDCx_MDMISC register and the field is labeled as WALAT. Incrementing the value of this register field by one adds a full clock cycle delay to the Write Post Amble period, and ensures enough time at the end of a burst write to guarantee a correct write. There is no maximum value to Write Post Amble Delay. Setting WALAT = 1 (or larger if WL parameters are larger) will cause a small hit in overall performance, but will add to the reliability of write operations, particularly on boards that require larger WL parameter settings.

i.MX 51 EVK Board Bootloader i.MX 51 EVK Board Flashing i.MX 51 EVK U-boot i.MX 51 EVK Compiling U-boot i.MX 51 EVK Changing Env Linux i.MX 51 Flashing Linux Application Only with SD Card Reader Multimedia i.MX 51 EVK Board USB Camera i.MX 51 EVK Board OpenCV Android All Board Android Without Ramdisk All Board install TTS Library Manually i.MX 51 Android ADB over USB Ubuntu i.MX 51 Ubuntu USB TS i.MX 51 Ubuntu TS Lucid

  Some our customers want to use the mfgtool to download the images to QSPI and boot up. When download the demo images on our website (Linux 4.1.15) to the QSPI-NOR on IMX7D SABRE-SDB. The error occurred as follows: Is it able to program the QSPI-NOR on i.MX7D SABRE-SDB by using MFG-Tool? Answer is yes. In the above error message we can see that the system can not find and detect the qspi, so it can not excute the following code,<CMD state="body="$ flash_erase /dev/mtd0 0 20">Erasing Boot partition</CMD>Updater" type="push" when use the mfgtool to download the images to the QSPI-NOR . The board i.MX7D SABRE-SDB and default BSP are boot up from EPDC.  Here customer want to boot up from QSPI, When using QSPI, you need to de-populate R388-R391, R396-R399 and populate R392-R395, R299, R300 in your hardware. QSPI signals are muxed with EPDC_D[7:0]. You can see the schematic, details you can see as follow. After hardware modify, you can use the mfgtool2-yocto-mx-sabresd-qspi-nor-mx25l51245g.vbs to download. And then boot up from qspi, boot mode you can refer to the schematic boot up setting. Both software and mfgtool you can download here http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-software-and-tools:IMXSW_HOME. Demo images can documents you can also get.    

Atlas PMIC i.MX Platforms uses Freescale Atlas chipset as power management IC (PMIC). PMIC is connected with i.MX processor through SPI port. Reading and Changing PMIC Registers pmic_reg is a simple program that allows to read and change PMIC registers through SPI. Click here to download the binary Click here to download the source package Click here to download the spec file pmic_reg Installation To use pmic_reg, you can simply download the binary file and move it to your system. To build the source code, download and mv the source package (in this case "pmic_reg-1.0.tar.gz") to /opt/freescale/pkgs: sudo mv pmic_reg-1.0.tar.gz /opt/freescale/pkgs Download the spec file to spec directory: mkdir <ltib directory>/dist/lfs-5.1/pmic_reg cp pmic_reg.spec <ltib directory>/dist/lfs-5.1/pmic_reg On <ltib directory>, extract, build and deploy pmic_reg: ./ltib -p pmic_reg.spec -m prep ./ltib -p pmic_reg.spec -m scbuild ./ltib -p pmic_reg.spec -m scdeploy Source files will be located at <ltib directory>/rpm/BUILD/pmic_reg-1.0 and binary will be located at /usr/bin on your i.MX system rootfs. pmic_reg Usage To get pmic_reg help, just type pmic_reg: PMIC_REG v1.0 (2009.12.15) Usage To read all PMIC registers: pmic_reg r To write to a specific register: pmic_reg w <register address> <register value>

Features Additional Information Detailed Features List of i.MX31ADS board This is a development tool which is designed to run software applications designed for i.MX31 (MCIMX31) microprocessor unit (MPU). The MCIMX31ADS includes a baseboard, a CPU board, a power management board, an LCD display panel, a keypad, a NAND Flash card, an image sensor, etc. It supports application software, target-board debugging, or optional extra memory. Features Three board system Base board with display and interface connectors CPU board with i.MX31 ARM-11 MCU Power management board with MC13783 Atlas chip +5.0 VDC, 2.4 A universal power supply QVGA LCD display panel with touchscreen capability and LED backlight Keypad with 64 push button keys Image sensor camera Configurable intelligent management of system power Separate selectable voltage regulators for running the CPU board in stand-alone mode Two selectable system clock sources, 32.768 kHz and 26 MHz Onboard CPLD that manages memory-mapped expansion I/O, interrupts, and general-purpose I/O Multi-ICE debug support 32 MB of 16-bit NOR burst flash memory 16 MB of 16-bit PSRAM 128 MB of 32-bit DDR SDRAM memory Two sets of two memory card connectors, selectable as SD/MMC (on Base board) or MS (on CPU board), with card-sense functionality 1G-bit x8 data NOR Flash on a removable card SIMM card connector PCMCIA connector NAND Flash card connector Three RS-232 interfaces with DB-9 connectors driven by UART channels internal to the MX31. Each interface has two UART options and power up enable DIP switches. One supports DCE with optional full modem controls, another is DTE with optional full modem controls, and the third is DTE with RTS/CTS controls only. An external DUART configured as two RS-232 DCE channels (one DB9 connector, one 10-pin header) Two USB host transceivers, one full-speed and one high-speed, with standard USB host connectors Three USB OTG transceivers, one full-speed and one high-speed on the Base board, one full-speed on the Atlas board, with mini AB connectors 10 Base-T Ethernet controller with RJ-45 connector with built-in data flow LED indicators IrDA Specification 1.4 transceiver supports fast, medium, and slow operating modes ATA5 controller with 44-position dual row, 2 mm header for small form-factor disk drives I2C interface with one of two selectable MCU interfaces CSPI connector Two CSI connectors, with different image sensor orientations Smart serial LCD display connector QVGA LCD display connector with touch screen interface plus companion connector with additional control signals Two smart parallel LCD display connectors TV encoder connector Keypad connector Interface connector to baseband processor Audio synthesizer chip with microphone and line inputs (3.5 mm jacks); line, voice, and headphone outputs (3.5 mm jacks); and speaker output (screw terminals) Eight DIP configuration switches with user-definable functions Software-readable CPU and Base board versions LED indicators for +5V IN, 3.3V, vibrator output, and synthesizer output. Two LED indicators for user-defined function Piezoelectric audible alert and vibratory alert Three RGB funlight indicators and funlight connector Push button Reset (on CPU) or reset control from Atlas 1-wire EPROM • Push button interrupt source Two Mictor LA/SW Analysis Connectors (Base board) Four Samtec LA Connectors (CPU) Three Extension connectors, two are compatible with the MX21 ADS Extension connectors Special Atlas board features Stereo microphone jack, normal microphone jack, external TXIN jack, headphone jack, low level stereo input and output jacks, stereo and mono (ear piece) speaker terminals Main battery emulation from +5V Main battery connection terminals Back up battery emulation (super cap) Coin cell (backup) battery connection terminals Battery charger input terminals Backlight LED indicators Three Push button switches to act as power on/off switches DIP switches to select default power up power and power sequencing. USB mode, USB enable, and WDI disable DIP Switches. Audio clock source selection DIP Switches. Individual test point and LED indicator for each Atlas voltage USB cables, RS-232 serial cable, and two RJ-45 Ethernet cables, network, and crossover Additional Resources Booting Linux From NAND Flash on the i.MX 31 ADS IMX31ADS Compiling Linux kernel mainline

On L4.1.15 BSP, PWM output clock may be not stable, for example, it may switch between 200KHz and 50KHz. PWM clock source is perclk, in running mode, perclk is 24MHz, while in low power idle mode, perclk is reduced to 6MHz, so PWM output clock is reduced to 1/4. To keep PWM output stable clock, we should let perclk stay in 24MHz in low power idle mode. Attached is the patch for 6UL and 6ULL.

If you are a Windows user and don't want to install Linux on your machine, VMware is a virtual machine used to install Linux under Windows. It's a good way to start with Linux (if you're unfamiliar with it) and also start your i.MX development. Installing VMWare - VMWare Workstation [VMWare Workstation (Click here to go to Download page)] VMWare Workstation is available in commercial and trial versions. With Workstation is possible to create your own installation image—installing a new operating system as you would install it in a new machine. - VMWare Player [VMWare Player (Click here to go to Download page)] VMWare Player is available in a free version. With Player is only possible to run images previously made. - VMWare Images at ThoughtPolice site [ThoughtPolice site (Click here to go to Download page)] This site has many ready VMWare images from many Linux distributions. It just needs to be downloaded, unziped and it's ready to be used with VMware. Workstation or Player.

Quick guide on how to get started with Linux on i.MX 6UL EVK board using MfgTool from L3.14.52 release: Download MfgTool from here (Version is IMX6_L3.14.52_MFG_TOOL (REV L3.14.52_1.1.0) under “Programmers (Flash, etc.)”): http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/i.mx6qp/i.mx-6ultralite-processor-low-power-secure-arm-cortex-a7-core:i.MX6UL?fpsp=1&tab=Design_Tools_Tab Unpack the archive and unpack mfgtools-with-rootfs.tar.gz edit cfg.ini and change following entries: mmc needs to be set to 1 6uluboot needs to be set to evk 6uldtb needs to be set to 14x14-evk Connect USB cable, USB debug cable to your PC.Open terminal to serial port (115200, 8N1). Insert uSD card to the slot on i.MX 6UL CPU module Set boot switches on SW602 [2:1] to on:off Power on the board Start MfgTool2.exe. HID device should be detected. Press "Start" button. Downloading should start. Executed steps are visible in the debug terminal. When you see "Done" printed, downloading has succeeded. Set boot switches on SW602 [2:1] to off:on, SW601[4:1] TO off:on:off:on Reset i.MX 6UL EVK (or power off then on), and boot to Linux. In case of any error, inspect serial output on debug terminal to see what has gone wrong. This document was generated from the following discussion: Getting started with i.MX6UL EVK and MfgTool L3.14.52

Q: Can OpenGL/OpenVG work on any of our boards with a 16-bit DDR bus? Here is GPU state dump when run some of the GPU SDK tutorials on their imx6 solo board with a 16-bit DDR bus: Mounting rootfs VFS: Mounted root (nfs filesystem) readonly on device 0:12. Freeing init memory: 156K Starting init GPU[0]: ************************** ***   GPU STATE DUMP   *** **************************   axi      = 0x000000B1   idle     = 0x7FFFFF86     FE not idle     SH not idle     PA not idle     SE not idle     RA not idle   DMA appears to be stuck at this address:     0x1882F230   dmaLow   = 0x08010583   dmaHigh  = 0x80003400   dmaState = 0x00000904     command state       = 4 (PAR_ADR1_ST)     command DMA state   = 1 (CMD_START_ST)     command fetch state = 2 (FET_VALID_ST)     DMA request state   = 0 (REQ_IDLE_ST)     cal state           = 0 (CAL_IDLE_ST)     VE request state    = 0 (VER_IDLE_ST)   RA debug registers:     [0x00] 0x0108C378     [0x01] 0x0042FB12     [0x02] 0x0042FB11     [0x03] 0x0000022C     [0x04] 0x10220033     [0x05] 0x0885C800     [0x06] 0xC054CBFE     [0x07] 0x68100000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x12344321     [0x0D] 0x12344321     [0x0E] 0x12344321     [0x0F] 0x12344321     signature = 0x12344321 (1 read attempt(s))   TX debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   FE debug registers:     [0x00] 0x1882F450     [0x01] 0x08010594     [0x02] 0x00000001     [0x03] 0x00000256     [0x04] 0x00080049     [0x05] 0x0000000D     [0x06] 0x00009571     [0x07] 0x00007445     [0x08] 0x00000004     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0xA3105D67     [0x0E] 0x000000D0     [0x0F] 0xBABEF00D     signature = 0xBABEF00D (1 read attempt(s))   PE debug registers:     [0x00] 0x0108C369     [0x01] 0x00000000     [0x02] 0x0108C369     [0x03] 0x00000000     [0x04] 0xA0000000     [0x05] 0xABC00000     [0x06] 0xBC000000     [0x07] 0xCDE00000     [0x08] 0xD04045C0     [0x09] 0x204045C0     [0x0A] 0x0D863084     [0x0B] 0x00000000     [0x0C] 0xBABEF00D     [0x0D] 0xBABEF00D     [0x0E] 0xBABEF00D     [0x0F] 0xBABEF00D     signature = 0xBABEF00D (1 read attempt(s))   DE debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   SH debug registers:     [0x00] 0x0049AB4C     [0x01] 0x0000000B     [0x02] 0x00000411     [0x03] 0x00020A95     [0x04] 0x00000000     [0x05] 0x000F024E     [0x06] 0x000F424C     [0x07] 0x010BEC30     [0x08] 0x0108C368     [0x09] 0x000020DF     [0x0A] 0x00000693     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0xDEADBEEF     signature = 0xDEADBEEF (1 read attempt(s))   PA debug registers:     [0x00] 0x640006FE     [0x01] 0x64000000     [0x02] 0x00000810     [0x03] 0x00000690     [0x04] 0x00000230     [0x05] 0x0000022D     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000003     [0x09] 0x0000AAAA     [0x0A] 0x0000AAAA     [0x0B] 0x0000AAAA     [0x0C] 0x0000AAAA     [0x0D] 0x0000AAAA     [0x0E] 0x0000AAAA     [0x0F] 0x0000AAAA     signature = 0x0000AAAA (1 read attempt(s))   SE debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   MC debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x12345678     [0x05] 0x12345678     [0x06] 0x12345678     [0x07] 0x12345678     [0x08] 0x12345678     [0x09] 0x12345678     [0x0A] 0x12345678     [0x0B] 0x12345678     [0x0C] 0x12345678     [0x0D] 0x12345678     [0x0E] 0x12345678     [0x0F] 0x12345678     signature = 0x12345678 (1 read attempt(s))   HI debug registers:     [0x00] 0x0000F719     [0x01] 0x19C020C8     [0x02] 0x1EBC2426     [0x03] 0xAAAAAAAA     [0x04] 0xAAAAAAAA     [0x05] 0xAAAAAAAA     [0x06] 0xAAAAAAAA     [0x07] 0xAAAAAAAA     [0x08] 0xAAAAAAAA     [0x09] 0xAAAAAAAA     [0x0A] 0xAAAAAAAA     [0x0B] 0xAAAAAAAA     [0x0C] 0xAAAAAAAA     [0x0D] 0xAAAAAAAA     [0x0E] 0xAAAAAAAA     [0x0F] 0xAAAAAAAA     signature = 0xAAAAAAAA (1 read attempt(s))   Other Registers:     [0x0040] 0x00924A66     [0x0044] 0x06F47370     [0x004C] 0x06F47370     [0x0050] 0x00DE8E6E     [0x0054] 0x00DE8E6E     [0x0058] 0x00924A66     [0x005C] 0x001254D6     [0x0060] 0x001254D6     [0x043C] 0x00000000     [0x0440] 0x00000000     [0x0444] 0x00000000     [0x0414] 0x3C000000 [<8003b21c>] (unwind_backtrace+0x0/0xfc) from [<80308114>] (_DumpGPUState+0x4ec/0x6b4) [<80308114>] (_DumpGPUState+0x4ec/0x6b4) from [<80308324>] (gckOS_Broadcast+0x38/0xe8) [<80308324>] (gckOS_Broadcast+0x38/0xe8) from [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) from [<80311294>] (gckEVENT_Submit+0x8c/0x328) [<80311294>] (gckEVENT_Submit+0x8c/0x328) from [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) from [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) from [<80306580>] (drv_ioctl+0x108/0x250) [<80306580>] (drv_ioctl+0x108/0x250) from [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) from [<800edc9c>] (sys_ioctl+0x38/0x60) [<800edc9c>] (sys_ioctl+0x38/0x60) from [<80035580>] (ret_fast_syscall+0x0/0x30) A: This GPU driver stack dump indicates GPU stuck when VDDPU_CAP was under spec values (1.2V) so GPU was not correctly powered. Was fixed by adjusting PMU_REG_CORE[REG1_TARG]. AFAIK, GPU drivers have some DDR bank configuration, so you may see a different problem though.

Hardware : i.MX8MNLPDDR4EVK Build Yocto Image [Linux 4.14.98_2.3.1] Yocto Project Setup          $: mkdir imx-yocto-bsp          $: cd imx-yocto-bsp                $: repo init -u https://source.codeaurora.org/external/imx/imx-manifest -b imx-linux-sumo -m imx-4.14.98-2.3.1.xml          $: repo sync  copy marvell bb.file into yocto source         $: cp  0001-Porting-mrvl-8987-wifi.patch   imx-yocto-bsp/sources/meta-fsl-bsp-release/imx/meta-bsp         $: git apply 0001-Porting-mrvl-8987-wifi.patch Image Build         $: DISTRO=fsl-imx-xwayland MACHINE=imx8mnlpddr4evk source fsl-setup-release.sh -b build-xwayland         $:bitbake fsl-image-qt5-validation-imx Enable wifi and BT (These operations is on EVK) WiFi $:insmod /lib/modules/4.14.98-2.3.1+g860ec89/extra/sd8xxx.ko fw_name=/mrvl/sduart8987_combo.bin cal_data_cfg=none cfg80211_wext=0xf BT $:hciattach /dev/ttymxc0 any -s 115200 115200 flow dtron $:hciconfig hci0 reset $:hcitool -ihci0 cmd 0x3f 0x0009 0xc0 0xc6 0x2d 0x00 & $:killall hcitool $:killall hciattach $:hciattach /dev/ttymxc0 any -s 3000000 3000000 flow dtron Build  Android Image[Android P9_2.3.4] These patches in  Android-2.3.4-patch. Getting i.MX Android release source code        $: cd ~ (or any other directory you like)        $: tar xzvf imx-p9.0.0_2.3.4.tar.gz        $: mkdir ~/bin        $: curl https://storage.googleapis.com/git-repo-downloads/repo > ~/bin/repo        $: chmod a+x ~/bin/repo        $: export PATH=${PATH}:~/bin        $: source ~/imx-p9.0.0_2.3.0/imx_android_setup.sh        # By default, the imx_android_setup.sh script will create the source code build environemnt        in the folder ~/android_build        # ${MY_ANDROID} will be refered as the i.MX Android source code root directory in all i.MX        Andorid release documentation.        $ : export MY_ANDROID=~/android_build Copy 88W8987 firmware and driver into  Android release code        $:copy -r Android-2.3.4-patch/mrvl    android_build/vendor/nxp/fsl-proprietary  Apply these patches.The name of these patches is the patche installation path.            example:  0001-android_build-hardware-marvell-wlan.patch         $: cp 0001-android_build-hardware-marvell-wlan.patch   android_build/hardware/marvell/wlan            (if not exist android_build/hardware/marvell/wlan, mkdir -p android_build/hardware/marvell/wlan)         $: git apply 0001-android_build-hardware-marvell-wlan.patch  Building Android images          $: cd  android_build          $: source build/envsetup.sh          $: lunch evk_8mn-userdebug          $: make 

$ git log --pretty=oneline --abbrev-commit 6f0c058 Linux 3.7-rc2 198190a Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 aeed41a arm64: fix alignment padding in assembly code 31fd84b use clamp_t in UNAME26 fix 8c1bee6 Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 45bff41 perf python: Properly link with libtraceevent

You can use TV Out on i.MX27ADS board by following these steps: Remove the R71 and solder it on R69 place; See the image before of this process: And after this process: Set SWITCH S15: 1 = on; [2-5] = off. See the image for more details: Add to your Linux command line (in Redboot) the following parameter: video=mxcfb:TV-NTSC After this modification, the video signal will operate at 27MHz, that are applicable just with TV-OUT card. The LCD card will not work at this frequency.

The miscellaneous service is in charge of providing access to all features not handled by the other services some examples include the following features: Subsystems controls - Some subsystems have settings that can be configured through the SCFW. For instance it is possible to set thresholds for a temperature alarm and get the temperature value of the sensor in different resources. For a complete list of resources and its controls please refer to the sc_fw_api document Chapter 5 Control List. DMA configurations - The SCFW provides access to DMA grouping and priority functions. Security functions - The SCFW provides some security functions such as: Image loading and authentication Fuse writing Life cycle management. Debug features - The SCFW provides some debug functionality through its miscellaneous service, some examples include:  Output a character through the SCU UART port Obtain SCFW build information (SCFW version) Obtain device Unique ID For a complete list of functions supported by your device please refer to the (SVC) Miscellaneous Service chapter of the sc_fw_api document.  This guide will cover the most common functions,  Getting and setting a control The process to get and set a control on a resource is the same for all available controls. Refer to the Control list chapter of your SoC SCFW API document for a complete list of the available controls. The following example will be based on an i.MX8QM.  The control list looks as follows: The table lists the controls available per resource as well as the width of the data to get/set, the 'Set' column describes whether a control is 'settable' or not, for instance the temperature sensor on the A53 resource can only be read/retrieved it cannot be 'written' (set) therefore the 'Y' (yes) in this column is missing, a brief description of the control is also provided. To get a control sc_misc_get_control must be called: uint32_t val; sc_misc_get_control(ipc, SC_R_A53, SC_C_TEMP, &val)‍;‍‍‍‍‍‍ By default all calls to get_control need a pointer to a 32 bit unsigned integer, the width field on the control list table defines the span of meaningful data. In the example above the data from the temperature sensor in the A53 resource is retrieved. This call returns SC_ERR_NONE whenever it succeeds. If the parameters are invalid it returns SC_PARM and if the caller does not have access to that resource it returns SC_ERR_NOACCESS. To set a control sc_misc_set_control must be called: uint32_t val = high_alarm_temperature_value; sc_misc_set_control(ipc, SC_R_A53, SC_C_TEMP_HI, val);‍‍‍‍‍‍‍‍ As in the get example sc_misc_set_control expects a 32 bit unsigned integer, it is the responsibility of the user to pass a value within the width limits defined in the control list table. In the example above the upper threshold for the A53 resource is being set/configured. The return values are the same as in sc_misc_get_control. Other functions There is a different method for getting/setting temperatures in a friendly human readable format, the method above uses a 'raw' format to interact with the temperature sensors in the resources, an easier way is to use the sc_misc_get_temp and sc_misc_set_temp functions. This functions return the temperature value in degrees Celsius as well as it's fractional part. To define whether to get/set the value for the temperature sensor itself or one of it's alarm the sc_misc_temp_t has been defined. SC_MISC_TEMP      -> Temperature sensor SC_MISC_TEMP_HIGH -> Upper threshold temperature sensor alarm SC_MISC_TEMP_LOW  -> Lower threshold temperature sensor alarm‍‍‍‍‍‍‍‍‍ For instance to get the temperature reading from the A53 resource the following call can be made: int16_t celsius; int8_t tenths; sc_misc_get_temp(ipc, SC_R_A53, SC_MISC_TEMP, &celsius, &tenths);‍‍‍‍‍‍‍‍‍ And to set the upper threshold alarm: int16_t celsius = 80; int8_t tenths = 0; /* Set High temperature alarm to 80 degrees Celsius */ sc_misc_set_temp(ipc, SC_R_A53, SC_MISC_TEMP_HIGH, celsius, tenths);‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Unique ID of the chip as well as the build info of the SCFW can also be obtained through the miscellaneous service, the following example queries for this information: /* Getting SCFW version information */ uint32_t build_version; uint32_t commit_hash; sc_misc_build_info(ipc, &build_version, &commit_hash);‍‍‍ /* Getting Device Unique ID */ uint32_t ID_L; uint32_t ID_H; /* The ID is a 64-bit number ID_L stores the lower 32-bit portion and ID_H the 32-bit upper portion */ sc_misc_unique_id(ipc, &ID_L, &ID_H);‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Refer to the sc_fw_api document for a definition of the remaining miscellaneous functions. https://community.nxp.com/docs/DOC-342654 

Attached you can find a document that explains how to add Wi-Fi support in the iMX28evk using Yocto.

1 How to build out userdata.img and cache.img The default fsl android  bsp don't support userdata.img and cache.img. You need add the below patch to build  out these images. The hardware for below patch is imx7D. You can adjust your patch according your hardware. diff --git a/imx7/BoardConfigCommon.mk b/imx7/BoardConfigCommon.mk index 14e4881..c207727 100644 --- a/imx7/BoardConfigCommon.mk +++ b/imx7/BoardConfigCommon.mk @@ -61,7 +61,11 @@ BOARD_BOOTIMAGE_PARTITION_SIZE :=  16777216 BOARD_RECOVERYIMAGE_PARTITION_SIZE := 16777216 BOARD_SYSTEMIMAGE_PARTITION_SIZE := 377487360 +BOARD_USERDATAIMAGE_PARTITION_SIZE := 576716800 +TARGET_USERIMAGES_USE_EXT4 := true +BOARD_CACHEIMAGE_PARTITION_SIZE := 69206016 +BOARD_CACHEIMAGE_FILE_SYSTEM_TYPE := ext4 BOARD_FLASH_BLOCK_SIZE := 4096 TARGET_RECOVERY_UI_LIB := librecovery_ui_imx - +TARGET_USERIMAGES_SPARSE_EXT_DISABLED := true 2  How to add  pre-install apk. I add a content pre-app in device/fsl/imx7. helloworld.apk is the added pre-install apk. diff --git a/imx7/pre-app/AnTutuV2.4.apk b/imx7/pre-app/helloworld.apk new file mode 100755 index 0000000..a96003a Binary files /dev/null and b/imx7/pre-app/AnTutuV2.4.apk differ diff --git a/imx7/sabresd_7d.mk b/imx7/sabresd_7d.mk index d7c5c76..11be86c 100644 --- a/imx7/sabresd_7d.mk +++ b/imx7/sabresd_7d.mk @@ -27,7 +27,8 @@ PRODUCT_COPY_FILES += \         device/fsl/common/input/20b8000_kpp.idc:system/usr/idc/20b8000_kpp.idc \         device/fsl/common/input/20b8000_kpp.kl:system/usr/keylayout/20b8000_kpp.kl \         device/fsl/sabresd_7d/audio_policy.conf:system/etc/audio_policy.conf \ -       device/fsl/sabresd_7d/audio_effects.conf:system/vendor/etc/audio_effects.conf +       device/fsl/sabresd_7d/audio_effects.conf:system/vendor/etc/audio_effects.conf \ +       device/fsl/imx7/pre-app/*:data/. 3 What are userdata.img and cache.img for? userdata.img: we need to integrate some customized APKs which should be preinstalled but should be able removed/updated by end user after product delivery. Which means they cannot be installed as system APPs in /system/app folder but User APPs in /data/app folder. At this point, we need compile userimage by ourself. Cache.img: /cache include the content when apk start running. You may storage some special content which app need. I have not find any advantage to pre-build cache.img. Note:      a. The  userdata.img and cache.img's format is sparse ext4 image. You need convert it through simg2img.           The  tool simg2img located at lp5.1_sabresd_7d_4_20/out/host/linux-x86/bin/simg2img           You can use below command to get raw ext4 userdata.img which can be burned into emmc/sd.           out/host/linux-x86/bin/simg2img userdata.img userdata_raw.img     b. BOARD_USERDATAIMAGE_PARTITION_SIZE BOARD_CACHEIMAGE_PARTITION_SIZE define the size of data and cache partition Reference: https://community.freescale.com/docs/DOC-105215

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343777 

MX6X_eMMC_turning_2014.11.11_V2.doc

The i.MX6 DL/S L3.035_3.0.4 patch release is now available onwww.freescale.com ·         Files available # Name Description 1 L3.0.35_3.0.4_TEMP_PATCH This patch release is based on the i.MX 6DualLite/6Solo   Linux L3.0.35_3.0.0 release. The purpose of this patch release is fix the   miscalibration issue for the thermal sensor.