The purpose of this document is to provide extended guidance for selection of compatible LPDDR5 and LPDDR4x memory devices that are supported by the i.MX 95 and i.MX 952 processors. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs. Please note that some of the LPDDR4x devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low speed operation is planned in the use case, please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured. LPDDR5 - maximum supported densities SoC Max Data bus width Maximum density Assumed memory organization Notes i.MX 95 32-bit 128Gb/16GB dual rank, dual channel device with 17-row addresses and x8 (byte mode) organization 1, 3, 7 i.MX 952 32-bit 128Gb/16GB dual rank, dual channel device with 17-row addresses and x8 (byte mode) organization 1, 3, 7, 9   LPDDR5 - list of validated memories Note: The memory vendors often list their devices as LPDDR5x in their high-level product information while in fact, they are in most cases backward compatible with the LPDDR5 mode. This may lead to the false impression that there are not so many LPDDR5 devices on the market. In such cases, it is strongly recommended to check the full datasheet to confirm if the device is in fact LPDDR5/LPDDR5x or LPDDR5x only. The SoC cannot be used with devices that only support the LPDDR5X mode. The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Memory Vendor  Validated Memory Part#  Notes i.MX 95 128Gb/16GB Micron MT62F4G32D8DV-023 FAAT:C - 64Gb/8GB  Samsung K3KL9L90QM-MHCT - 32Gb/4GB  Samsung K3KL8L80QM-MHCT 2 32Gb/4GB  Samsung K3KL8L80EM-MUCV 2        64Gb/8GB  SK HYNIX H58G66DK9VX067N 2 64Gb/8GB Micron MT62F2G32D4DS-023 FAAT:C 2, 6 32Gb/4GB Micron MT62F1G32D2DS-020 WT:D 2 16Gb/2GB Micron MT62F1G16D1DS-023 IT:B 2 64Gb / 8GB Rayson RS2G32LO5D24DB-31BT 2 64Gb / 8GB CXMT CXDB6CCBM-MA-A 2 i.MX 952 128Gb/16GB Micron MT62F4G32D8DV-023 FAAT:C 9 32Gb/4GB Micron MT62F1G32D2DS-020 WT:D 2   LPDDR5 - list of incompatible devices The SoC cannot be used with memory devices that only support the LPDDR5x mode. LPDDR4x - maximum supported densities SoC Max Data bus width Maximum density Assumed memory organization Notes i.MX 95 32-bit 128Gb/16GB dual rank, dual channel device with 17-row addresses 1 i.MX 952 32-bit 128Gb/16GB dual rank, dual channel device with 17-row addresses 1, 9   LPDDR4x - list of validated memories   The validation process is an ongoing effort - regular updates of the table are expected. SoC Density Memory Vendor Validated Memory Part# Notes i.MX 95 64Gb/8GB Micron   MT53E2G32D4DE-046 AUT:C  5 8Gb/1GB Micron MT53E256M32D1KS-046 IT:L 2 128Gb/16GB Micron MT53E4G32D8GS-046 2 64Gb/8GB SK Hynix H54G66BYYVPX104 2 32Gb/4GB Intelligent Memory IMBG32L4KBB_V10 2 48Gb/6GB Micron MT53E1536M32D4DT-046 WT:A 3, 8 24Gb/3GB Micron MT53E768M32D4DT-053 AIT:E 3, 8 8Gb/1GB Samsung K4U8E3S4ADGHCL  2 32Gb/4GB Intelligent Memory IMBG32LK4BBG-046I 2 32Gb/4GB Alliance Memory AS4C1G32MD4V-046BIN 2 64Gb/8GB Rayson ATL4X8G32M2D-46IT 2 64Gb/8GB Rayson ATL4X8G32M2D-46AIT 2 64Gb/8GB DW DWCTB36HLC0 2 i.MX 952 64Gb/8GB Micron   MT53E2G32D4DE-046 AUT:C  9   LPDDR4/4X - list of incompatible devices Note: This SoC supports LPDDR4x memory devices. This SoC is not compatible with memories that only support LPDDR4. Combo Devices that support both LPDDR4x and LPDDR4 are compatible with the SoC. Note 1: The numbers are based purely on the IP documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, SoC reference manual and on the JEDEC standards JESD209-5 (LPDDR5) and JESD209-4C/JESD209-4-1 (LPDDR4/4X). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 2: The memory part number did not undergo full JEDEC verification however, it passed all functional testing items. Note 3: Memory devices with binary densities (e.g., 1 GB, 2 GB, 4 GB) are preferred because they simplify memory management by aligning with system addressing schemes and reducing software complexity. Note 4: All memory parts are available at vendors unless stated otherwise. Checked Q2 2026 Note 5: Memory device supports both LPDDR4x and LPDDR4, however can only be used in LPDDR4x mode Note 6: Not validated by NXP but confirmed working on a non NXP Board Note 7: The maximum density supported may change in the future when DRAM vendors make higher density options available Note 8: This DRAM part number is not recommended for new designs Note 9: This SoC is in Pre-Production

The purpose of this document is to provide supportive information for selection of suitable LPDDR4, DDR4 and DDR3L devices that are supported by i.MX 8M family of processors to aid project feasibility assessment capabilities of customers that are evaluating the SoCs for usage in their products.  It is strongly recommended to consult with NXP and the memory vendor the final choice of the memory part number to ensure that the device meets all the compatibility, availability, longevity and pricing requirements. Please note that some of the LPDDR4 devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low speed operation is planned in the use case, please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the NXP Hardware Developer's Guides for the specific SoCs available on NXP.com Memory devices with binary densities (e.g., 1 GB, 2 GB, 4 GB) are preferred because they simplify memory management by aligning with system addressing schemes and reducing software complexity. For any questions related to specific DRAM part numbers please contact the respective DRAM vendor. For any questions regarding the i.MX SoC please contact your support representative or enter a support ticket.  LPDDR4 - maximum supported densities Please note that the SoCs only support memory devices that support either the LPDDR4 mode or support both LPDDR4 and LPDDR4X modes. Memory devices that support only the LPDDR4X mode are not supported. SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8M Quad 32-bit 32Gb/4GB dual rank, dual-channel  device with 16-row addresses (R0-R15) 1, 2, 4 i.MX 8M Mini  32-bit 64Gb/8GB dual rank, dual-channel  device with 17-row addresses (R0-R16) 1, 2 i.MX 8M Nano  16-bit 32Gb/4GB dual rank, single-channel  device with 17-row addresses (R0-R16) 1, 2, 3, 12 i.MX 8M Plus  32-bit 64Gb/8GB dual rank, dual-channel  device with 17-row addresses (R0-R16)  1, 2   LPDDR4 - list of validated memories Please note that the validation process is an ongoing effort - regular updates of the table are expected. Please contact NXP if a specific vendor or configuration is required. SoC Density Memory Vendor Validated Memory Part#  Notes i.MX 8M Quad  24Gb/3GB    Micron MT53B768M32D4NQ-062 WT:B  15 32Gb/4GB Micron MT53D1024M32D4DT-046 AAT:D  14 4Gb/512MB ISSI IS43LQ16256B-062BLI  5, 14 8Gb/1GB ISSI IS43LQ32256B-062BLI  5, 14 i.MX 8M Mini 16Gb/2GB Micron MT53D512M32D2DS-053 WT:D  15 16Gb/2GB    ESMT M56Z16G32512A-SMBIG 5, 14 32Gb/4GB Micron MT53E1G32D2FW-046 WT:A  5, 14 64Gb/8GB Micron MT53E2G32D4DT-046 AIT:A  5, 14 64Gb/8GB Micron MT53E2G32D4DE-046 AUT:C 5, 14 32Gb/4GB Intelligent Memory IMBG32L4KBB 5,14 32Gb/4GB Kingston B3221PM3BDGUI -U 5 i.MX 8M Nano  16Gb / 2GB  Kingston C1612PC2WDGTKR-U  15 16Gb / 2GB  Kingston  D1611PM3BDGUI-U 5,14 32Gb / 4GB Micron MT53E2G32D4DT-046 AIT:A  5, 13, 15 16Gb / 2GB Intelligent Memory  IMAG16L4KBB 5,14 4Gb / 512MB Nanya NT6AN256M16AV-J2 5,14 4Gb / 512MB  Winbond W66CP6RBQAHJ 5,14 8Gb / 1GB ISSI IS43LQ16512A-053BLI 5,14 8Gb / 1GB  Micron MT53D512M32D2DS-053 WT:D 13, 15   i.MX 8M Plus   48Gb/6GB  Micron MT53E1536M32D4DT-046 WT:A  15 64Gb/8GB  Micron MT53E2G32D4DE-046 AUT:C  5, 14 32Gb/4GB Samsung K4FBE3D4HB-KHCL  5, 14 32Gb/4GB Kingston B3221PM3BDGVIW-U 5, 14 64Gb/8GB Kingston Q6422PM3BDGVK-U  5, 14 8Gb/1GB Winbond W66DP2RQQAHJ  5, 14 32Gb/4GB ISSI IS46LQ32K01S2A-046BLA2 5, 14 16Gb/2GB ISSI IS46LQ32512A-046BLA3 5 32Gb/4GB ISSI IS43LQ32K01S2A-046BLI 5, 14 32Gb/4GB IM IMBG32LK4BBG-046I 5, 14   LPDDR4 - list of incompatible devices Given the limitations mentioned in this document, the following memory devices were identified as incompatible with the particular SoCs as detailed in the following table:   Memory Vendor Memory Part# Density Incompatible SoCs Incompatibility reason Samsung K4FHE3S4HA-KU(H/F)CL 24Gb/3Gb i.MX 8M Quad  The memory device requires 17th row address bit to function. Samsung K4UHE3S4AA-KU(H/F)CL K4UJE3D4AA-KU(H/F)CL 24Gb/3Gb 48Gb/6GB i.MX 8M Quad i.MX 8M Mini i.MX 8M Nano i.MX 8M Plus The memory device only supports the LPDDR4X mode. Samsung K4FCE3Q4HB-KU(H/F)CL K4UCE3Q4AB-KU(H/F)CL 64Gb/8GB i.MX 8M Quad i.MX 8M Mini i.MX 8M Nano i.MX 8M Plus A byte mode memory device. The memory device only supports the LPDDR4X mode.    DDR4 - maximum supported densities SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8M Quad  32-bit 32Gb/4GB x16, 16Gb device with 1 bank group address, 17-row addresses and 10 column addresses 1, 6 i.MX 8M Mini  32-bit 64Gb/8GB x16, 16Gb device with 1 bank group address, 17-row addresses and 10 column addresses 1, 7 i.MX 8M Nano  16-bit 64Gb/8GB x8, 16Gb device with 2 bank group addresses, 17-row addresses and 10 column addresses 1, 8 i.MX 8M Plus  32-bit 64Gb/8GB x16, 16Gb device with 1 bank group address, 17-row addresses and 10 column addresses 1, 7   DDR4 - list of validated memories Please note that the validation process is an ongoing effort - regular updates of the table are expected. Please contact NXP if a specific vendor or configuration is required.   SoC Density Memory Vendor Validated Memory Part#  Notes i.MX 8M Quad 32Gb/4GB Micron 4x MT40A512M16JY-083EAAT  15 i.MX 8M Mini  16Gb/2GB Micron 2x MT40A512M16LY-075:E  15 i.MX 8M Nano 16Gb/2GB Micron 1x MT40A1G16RC-062E:B  15 8Gb/1GB Rayson 1x RS512M16Z2DD-62DT 14 8Gb/1GB UniIC SCB12Q8G160BF-06SI 14 i.MX 8M Plus 64Gb/8GB Micron 4x MT40A1G16RC-062E:B  15 16Gb/2GB Nanya NT5AD512M16C4-JRI  14   DDR3L - maximum supported densities SoC Max data bus width Maximum density Assumed memory organization Notes i.MX 8M Quad  32-bit 32Gb/4GB x16, 8Gb device with 16-row addresses and 10 column addresses 1, 9 i.MX 8M Mini  32-bit 64Gb/8GB x8, 8Gb device with 16-row addresses and 11 column addresses 1, 10 i.MX 8M Nano  16-bit 32Gb/4GB x8, 8Gb device with 16-row addresses and 11 column addresses 1, 11 i.MX 8M Plus  i.MX 8M Plus does not support DDR3L   DDR3L - list of validated memories Please note that the validation process is an ongoing effort - regular updates of the table are expected. Please contact NXP if a specific vendor or configuration is required. SoC Density Vendor Validated Memory Part#  Notes i.MX 8M Quad  16Gb/2GB Micron 4x MT41K256M16TW-107 AAT  14 i.MX 8M Mini  16Gb/2GB Micron 4x MT41K256M16TW-107 AAT  14              i.MX 8M Nano 8Gb/1GB Micron MT41K512M16VRN-107  15   Note 1: The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, and on the JEDEC standards JESD209-4/JESD209-4A (LPDDR4), JESD279-4/JESD279-4A (DDR4), and JESD79-3E/JESD79-3F/JESD79-3-1A (DDR3/DDR3L). Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that an SoC with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 2: Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification). Note 3: The memory vendors often do not offer so many variants of single-channel memory devices. As an alternative, a dual-channel device with only one channel connected may be used. For example: A dual-rank, single-channel device with 16-row address bits has a density of 16Gb. If such a device is not available at the chosen supplier, a dual-rank, dual-channel device with 16-row address bits can be used instead. This device has a density of 32 Gb however since only one channel can be connected to the SoC, only half of the density is available (16 Gb). Usage of more than one discrete memory chips to overcome market constraints is not supported since only point-to-point connections are assumed for LPDDR4. Note 4: Devices with 17-row addresses (R0-R16) are not supported by the DDR Controller Note 5: The memory part number did not undergo full JEDEC verification however, it passed all functional testing items. Note 6: The density can be achieved by connecting 2 single-rank discrete devices with one 16Gb die each. Since the SoC supports x8 devices and also has connectivity for a second rank, usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 32Gb/4GB of address space dedicated for the DDR. Two x16 16Gb devices giving 32Gb/4GB in total is, therefore, the optimal choice that balances the maximum density aspects, the signal integrity aspects (only two discrete devices used), and bandwidth aspects (full data bus width used). Note 7: The density can be achieved by connecting 4 single rank discrete devices with one 16Gb die each, 2 devices connected to each chip select. Since the SoC supports x8 devices, the usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 64Gb/8GB of address space dedicated for the DDR. Four x16 16Gb devices giving 64Gb/8GB in total is the optimal choice that balances the maximum density aspects, the signal integrity aspects (only four discrete devices used), and the bandwidth aspects (full data bus width used). Note 8: The density can be achieved by connecting 4 single rank discrete devices with one 16Gb die each, 2 devices connected to each chip select.  Note 9: The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select, or by connecting 2 dual rank discrete devices with two 8Gb dies each. Since the SoC supports x8 devices, the usage of more discrete devices is possible. However, this advantage cannot be used to get higher density since this SoC has only 32Gb/4GB of address space dedicated for the DDR. Four x16 8Gb devices giving 32Gb/4GB in total is, therefore, the optimal choice that balances the maximum density aspects, the signal integrity aspects (four discrete devices used), and bandwidth aspects (full data bus width used). Note 10: The density can be achieved by connecting 8 single rank discrete devices with one 8Gb die each, 4 devices connected to each chip select or by connecting 4 dual rank discrete devices with two 8Gb dies each. Note that the first option significantly exceeds the number of devices used on the validation board (4 discrete devices) therefore, it is not guaranteed that the i.MX would be able to drive the signals with margin to the required voltage levels due to increased loading on the traces. A significant effort would be required in terms of PCB layout and signal integrity analysis. Practically, it is not recommended to use more than 4 discrete DDR3L devices. This corresponds to the maximum density of 32Gb/4GB in the case of the single rank devices containing one 8Gb die or 64Gb/8GB in case of the dual-rank devices, each containing two 8Gb dies. Note 11: The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select or by connecting 2 dual rank discrete devices with two 8Gb dies each. Note 12: For single-channel (x16) memory devices, the current maximum available density in the market is 16Gb/2GB (Q1 2022). Note 13: Only one channel of the device (and hence, half of its density) was utilized due to the reduced data bus width (x16) of the SoC. Note 14: Part is active. Reviewed Jan 2026 Note 15: Part will either EoL or is not recommended for new designs by the respective vendor.   Additional Links https://community.nxp.com/t5/iMX-and-Vybrid-Support/i-MX-8-8X-8XL-maximum-supported-LPDDR4-and-DDR3L-densities/ta-p/1152715           

The purpose of this document is to provide supportive information for selection of suitable LPDDR4 and DDR3L devices that are supported by i.MX 8/8X/8XLite family of processors to aid project feasibility assessment capabilities of customers that are evaluating the SoCs for usage in their products.  It is strongly recommended to consult with NXP and the respective memory vendor, the final choice of the memory part number to ensure that the device meets all the compatibility, availability, longevity and pricing requirements. Please note that some of the LPDDR4 devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low speed operation is planned in the use case, please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured. In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the respective NXP i.MX 8 Hardware Developer's Guide available on NXP.com The i.MX8/8X/8XL Reference manuals declare that there are 16GB allocated for the DDR. Please note that this is only the address space, which is reserved for the DDR memory in the memory map. This specification does not guarantee that the entire region can be utilized as the maximum achievable densities listed below in the tables are restricted mainly by the addressing capabilities of the DDR controller, width of the data bus and other implementation-specific parameters as well as availability of supported devices on the market. Memory devices with binary densities (e.g., 1 GB, 2 GB, 4 GB) are preferred because they simplify memory management by aligning with system addressing schemes and reducing software complexity. For any questions related to specific DRAM part numbers please contact the respective DRAM vendor. For any questions regarding the i.MX SoC please contact your support representative or enter a support ticket.  LPDDR4 - maximum supported densities Please note that the SoCs only support memory devices that support either the LPDDR4 mode or support both LPDDR4 and LPDDR4X modes. Memory devices that support only the LPDDR4X mode are not supported. SoC Package Max data bus width Maximum density Assumed memory organization Notes i.MX 8QM/8QP 29x29 mm 32-bit (per controller) 32Gb/4GB (per controller) dual rank, dual-channel  device with 16-row addresses (R0-R15) 1, 2, 4 i.MX 8QXP/8DXP 21x21 mm 32-bit 32Gb/4GB dual rank, dual-channel  device with 16-row addresses (R0-R15) 1, 2, 4 i.MX 8QXP/8DXP 17x17 mm 16-bit 16Gb/2GB dual rank, single-channel  device with 16-row addresses (R0-R15) 1, 2, 3, 4, 9 i.MX 8XLite 15x15 mm 16-bit 32Gb/4GB dual rank, single channel  device with 17-row addresses (R0-R16) 1, 2, 3, 9   LPDDR4 - list of validated memories The validation process is an ongoing effort - updates of the table are expected. SoC Density Memory Vendor Validated Memory Part# Notes i.MX 8QM/8QP 24Gb/3GB (per controller) Micron MT53B768M32D4NQ-062 AIT:B   12, 13 32Gb/4GB (per controller)  Samsung K4FBE3D4HB-KHCL  10, 11 32Gb/4GB (per controller) Micron MT53E1G32D2FW-046 AUT:B (Z42M) 10, 11 32Gb/4GB (per controller) Micron MT53D1024M32D4DT-046 AAT:D   12 16Gb/2GB (per controller) Micron MT53D512M32D2DS-046 WT:D  10, 12 16Gb/2GB (per controller) Nanya NT6AN512T32AC-J1J  10, 11 16Gb/2GB (per controller) Nanya NT6AN512T32AC-J1H  10, 11 32Gb/4GB (per controller) Nanya NT6AN1024F32AC-J2J  10, 11 32Gb/4GB (per controller) Nanya NT6AN1024F32AC-J2H  10, 11 i.MX 8QXP/8DXP 24Gb/3GB Micron MT53B768M32D4NQ-062 AIT:B   12, 13 32Gb/4GB Nanya NT6AN1024F32AC-J2J  10, 11 32Gb/4GB Nanya NT6AN1024F32AC-J2H  10, 11 16Gb/2GB Nanya NT6AN512T32AC-J2J  10, 11 16Gb/2GB Nanya NT6AN512T32AC-J2H  10, 11 32Gb/4GB Micron MT53D1024M32D4DT-046 AAT:D   11 i.MX 8XLite 8Gb/1GB Micron MT53D512M16D1DS 046 AAT ES:D & Z9XGG   12 12Gb/1.5GB Micron MT53E768M16D1ZW-046 AAT:C 10, 11, 13 4Gb/0.5GB Samsung K4F4E164HD-THCL  10, 11 8Gb/1GB ISSI IS43LQ16512A-053BLI 10, 11 8Gb/1GB Nanya NT6AN512M16AV-J1I  10, 11   LPDDR4 - list of incompatible devices Given the limitations mentioned in this document, the following memory devices were identified as incompatible with the particular SoCs as detailed in the following table:   Memory vendor Part Number Density Incompatible SoCs Incompatibility reason Samsung K4FHE3S4HA-KU(H/F)CL 24Gb/3Gb i.MX8QM/8QP, i.MX8QXP/8DXP The memory device requires 17th row address bit to function. Samsung K4UHE3S4AA-KU(H/F)CL 24Gb/3Gb i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL The memory device only supports the LPDDR4X mode. Samsung K4UJE3D4AA-KU(H/F)CL 48Gb/6GB i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL The memory device only supports the LPDDR4X mode. Samsung K4FCE3Q4HB-KU(H/F)CL 64Gb/8GB i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL A byte mode memory device. Samsung K4UCE3Q4AB-KU(H/F)CL 64Gb/8GB i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL A byte mode memory device. The device only supports the LPDDR4X mode.    DDR3L - maximum supported densities SoC Package Max data bus width Maximum density Assumed memory organization Notes i.MX 8QXP/8DXP 21x21 mm 32-bit 64Gb/8GB x8, 8Gb device with 16-row addresses and 11 column addresses 5, 6 i.MX 8QXP/8DXP 17x17 mm 16-bit 32Gb/4GB x8, 8Gb device with 16-row addresses and 11 column addresses 5, 7 i.MX 8XLite 15x15 mm 16-bit 16Gb/2GB x8, 8Gb device with 16-row addresses and 11 column addresses 5, 8   DDR3L - list of validated memories The validation process is an ongoing effort -  updates of the table are expected. SoC Density Memory Vendor Validated Mamory Part#  Notes i.MX 8QXP/8DXP 8Gb/1GB Micron 2x MT41K256M16TW-093 IT:P 12 i.MX 8XLite 4Gb/512MB Micron MT41K256M16TW-093 IT:P 12   Note 1: The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, and on the JEDEC standard JESD209-4A. Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that a DRAM with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 2: Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification). Note 3: The memory vendors often do not offer so many variants of single-channel memory devices. As an alternative, a dual-channel device with only one channel connected may be used. For example: A dual-rank, single-channel device with 16-row address bits has a density of 16Gb. If such a device is not available at the chosen supplier, a dual-rank, dual-channel device with 16-row address bits can be used instead. This device has a density of 32 Gb however since only one channel can be connected to the SoC, only half of the density is available (16 Gb). Usage of more than one discrete memory chip to overcome market constraints is not supported since only point-to-point connections are assumed for LPDDR4. Note 4: Devices with 17-row addresses (R0-R16) are not supported by the SoCs.  Note 5: The numbers are based purely on the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, and on the JEDEC standard JESD79-3E/JESD79-3F. Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that a DRAM with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk. Note 6: The density can be achieved by connecting 8 single rank discrete devices with one 8Gb die each, 4 devices connected to each chip select, or by connecting 4 dual rank discrete devices with two 8Gb dies each. Note that this number of discrete devices significantly exceeds the number of devices used on the validation board (2 discrete devices, not taking into account the device used for ECC) therefore, it is not guaranteed that the i.MX would be able to drive the signals with margin to the required voltage levels due to increased loading on the traces. A significant effort would be required in terms of PCB layout and signal integrity analysis hence practically, it is not recommended to use more than 2 discrete DDR3L devices. This corresponds to the maximum density of 16Gb/2GB in the case of the single rank devices containing one 8Gb die or 32Gb/4GB in the case of the dual-rank devices containing two 8Gb dies (x16 8Gb devices with 16-row addresses and 10 column addresses assumed instead of x8 devices in such case). Note 7: The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select, or by connecting 2 dual rank discrete devices with two 8Gb dies each. Note that the first option exceeds the number of devices used on the validation board (2 discrete devices) therefore, it is not guaranteed that the i.MX would be able to drive the signals with margin to the required voltage levels due to increased loading on the traces. A significant effort would be required in terms of PCB layout and signal integrity analysis, hence practically, it is not recommended to use more than 2 discrete DDR3L devices. This corresponds to the maximum density of 16Gb/2GB in the case of the single rank devices containing one 8Gb die or 32Gb/4GB in the case of the dual-rank devices containing two 8Gb dies. Note 8: The density can be achieved by connecting 2 single rank discrete devices with one 8Gb die each to the i.MX. 8XLite supports only one chip select for DDR3L therefore, dual-rank systems are not supported. Note 9: For single-channel (x16) memory devices, the current maximum available density in the market is 16Gb/2GB (2025). Note 10: The memory part number did not undergo full JEDEC verification however, it passed all functional testing items. Note 11: Part is active. Reviewed Aug 2025 Note 12: Part is being End Of Life'd (EoL) by Vendor or obsolete. Note 13: Memory devices with binary densities (e.g., 1 GB, 2 GB, 4 GB) are preferred because they simplify memory management by aligning with system addressing schemes and reducing software complexity. Additional Links i.MX 8M Quad/8M Mini/8M Nano/8M Plus - LPDDR4, DDR4 and DDR3L memory compatibility guide 

   Memory Compatibility Guides   Processor/Family Link to Guide i.MX 8/8X/8XLite DDR3L and LPDDR4 i.MX 8M Quad/8M Mini/8M Nano/8M Plus DDR3L, DDR4, LPDDR4 i.MX 8ULP  LPDDR3, LPDDR4 & LPDDR4x i.MX 93 LPDDR4/LPDDR4x i.MX 95 LPDDR5/LPDDR4x - New Other Processor Families Please contact NXP Support or Sales   Additional Resources i.MX Memory Fact Sheet DDR memory selection & enablement for i.MX platforms Smarter World Blog Building Resilient Embedded Systems: NXP’s Approach to DDR Memory Selection and Support DDR Configuration Tools DDR Configuration tool for i.MX  Developer Resources i.MX Developer Resources SW & Tools