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******************************************************************************** * Detailed Description: * This example shows how to use the CTU module triggered from eTimer0 module channel 2. * * For closer details on how CTU works I suggest you to check application note * MPC5643LPWM_ADC_concept * https://community.freescale.com/docs/DOC-102559 * * This example sets eTimer0 channel2 for PWM signal generation. * This signal is than used to send MSR trigger to CTU module * Example contains also simple CTU module driver initialization * CTU scheduler submodule is toggling with external pin based on CTU triggers * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ******************************************************************************** Original Attachment has been moved to: Example-MPC5744P-CTU-eTimer-v1_1-GHS614.zip
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Q1: Why DisplayPort to LVDS adapter? DPRX-LVDS is an (embedded) DisplayPort to LVDS bridge device that enables connectivity between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and transmits processed stream in LVDS format.   NXP offers two eDP-LVDS devices: 1. PTN3460 is commercial grade, 0 – 70 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 25 MHz to 112 MHz. 2. PTN3460I is industrial grade, -40 – 85 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 6 MHz to 112 MHz.   Q2. How to configure eDP-LVDS device?   The eDP-LVDS has embedded microcontroller and on-chip Non-Volatile Memory (NVM) to allow for flexibility in firmware updates.   Both PTN3460 and PTN3460I have a built in configuration table in internal 1K SRAM, which allows users to program seven EDID and 128 configuration registers through M/S I2C-bus. Please follow the programming guides below for these devices. 1. AN11128 – Programming Guide for PTN3460 2. AN11606 – Programming Guide for PTN3460I   Q3. What is maximum resolution DP-LVDS can support? The available bandwidth over a 2-lane HBR DisplayPort v1.4 link limits pixel clock rate support to: 1. 1-lane DP with single LVDS bus supports 800x600 @ 60 Hz display, 40 MHz pixel clock. 2. 1-lane DP with dual LVDS bus supports 1366x768 @ 60 Hz display, 85.5 MHz pixel clock. 3. 2-lane DP with single LVDS bus operation up to 112 mega pixel per second – supports 1440x900 @ 60 Hz resolution display. 4. 2-lane DP with dual LVDS bus operation up to 224 mega pixel per second – supports 1920x1200 @ 60 Hz resolution display.   Q4. How to update the FW? FW for eDP-LVDS devices can be updated by the following methods: 1. Flash over AUX (FoA) – This is an executable window utility that can only run under Windows OS. FW is updated through DP AUX channel. AN11133 – PTN3460 FoA utility user’s guide. 2. Flash over DOS (FoD) – This is an executable DOS utility that can run under DOS without OS. FW is updated through M/S I2C bus. 3. Flash over I2C – FW is updated through external I2C device that is plugged in a M/S I2C header.   Q5. How to check the FW version? FW version can be read out with DPCD utility that runs under Windows OS. Please follow DPCD Tool User Manual V1.0.   Q6. How many DP lanes supported in NXP DP to LVDS bridge device? NXP DP to LVDS bridge device supports 2 lanes HBR/RBR.   Q7. What does HBR/RBR mean? HBR means “High Bit Rate”, it runs 2.7 Gbit/s. RBR means “Reduced Bit Rate”, it runs 1.62 Gbit/s.   Q8. What is DP AUX channel? DP AUX channel is used for communication channel between DP source and DP sink device.   Q9. What is DP source device? DP source device is DP signal transmitter.   Q10. What is DP sink device? DP sink device is DP signal receiver.
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This video shows the necessary configurations to flash a binary file to a target, in this case the FRDM-KL25
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****************************************************************************************************** * The PCF2127T is a CMOS Real Time Clock (RTC) and calendar with an integrated * Temperature Compensated Crystal Oscillator and a 32.768 kHz quartz crystal * optimized for very high accuracy and very low power consumption.   * This simple example code has been written for the FRDM-KL25Z + OM13513 * boards in MCUXpresso IDE v10.1.0 and demonstrates how to set and read * the time/date on the PCF2127T using the SPI (do not forget to remove the * JP1 jumper) interface. It also illustrates how to use a minute interrupt to * generate an interrupt on the INT pin once per minute when the Minutes * register increments. * * In this example the date/time to be set is Wednesday, January 17 2018, 2:45 PM. * * Connection:     FRDM-KL25Z        OM13513 * VDD               J9-4                         P2-2 * GND               J9-18                       P2-1 * MOSI              J2-8                         P2-5 * MISO              J2-10                       P2-6 * SCLK             J2-12                       P2-4 * CS                  J2-6                        P2-3 * INT                 J1-6                        P2-8 ******************************************************************************************************
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Hi Everyone, I would like to share with you a simple bare metal example for the the SC16IS752 to demonstrate NXP Bridge IC for SPI/ I 2 C host to Dual Uart/IrDa/GPIO interface. This example is based on the OM6273 demo board for the SC16752/762. I made this example working with the NXP FRDM-KL25Z development platform. The example shows the device functionality by creating a simple echo transmission, where you are able to read what you just write into the device. This example illustrates: 1. Initialization of the MKL25Z128 MCU (I 2 C and port modules) 2. I 2 C data write and read operations 3. Initialization of the bridge to perform the communication 4. Transmission and the reception done with interrupt technique 5. Visualization of the echo function using the serial terminal 1. As you can see in the FRDM-KL25Z schematics and the image below, I 2 C signals are routed to the I2C1 module (PTC1 and PTC2 pins) of the KL25Z MCU and the INT1 output is connected to the PTA16 pin. The INT1 output of the SC16IS752 is configured as a push-pull active-low output, so the corresponding PTA16 pin configuration is GPIO with an interrupt on falling edge.                                               Therefore, this is the MCU configuration: void MCU_Init(void) {      //I2C1 module initialization      SIM_SCGC4 |= SIM_SCGC4_I2C1_MASK;          // Turn on clock to I2C1 module      SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;          // Turn on clock to Port E module      PORTC_PCR1 = PORT_PCR_MUX(2);               // PTC1 pin is I2C1 SCL line      PORTC_PCR2 = PORT_PCR_MUX(2);               // PTC2 pin is I2C1 SDA line      I2C1_F  = 0x14;                               // SDA hold time = 2.125us, SCL start hold time = 4.25us, SCL stop hold time = 5.125us      I2C1_C1 = I2C_C1_IICEN_MASK;              // Enable I2C1 module      //Configure the PTA16 pin (connected to the IRQ of the SC16IS752) for falling edge interrupts      SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;               // Turn on clock to Port A module      PORTA_PCR16 |= (0|PORT_PCR_ISF_MASK              // Clear the interrupt flag                    | PORT_PCR_MUX(0x1)                    // PTA16 is configured as GPIO                    | PORT_PCR_IRQC(0xA));               // PTA16 is configured for falling edge interrupts      //Enable PORTA interrupt on NVIC      NVIC_EnableIRQ(PORTA_IRQn);                // Enable interrupts      NVIC_ClearPendingIRQ(PORTA_IRQn);          // Clear pending interrupts } ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ 2. To perform the read or write operation we'll make use of an I 2 C library which contains to main functions: void I2C_WriteRegister(unsigned char u8SlaveAddress, unsigned char u8RegisterAddress, /*unsigned*/ char u8Data); unsigned char I2C_ReadRegister(unsigned char u8SlaveAddress, unsigned char u8RegisterAddress) Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. Table 32. shows how the SC16IS752/SC16IS762’s address can be selected by using A1 and A0 pins. In the demo board OM6273, these  2 pins are connected to JP4 and JP3 and in this example there are two jumpers plugged so A1 = VDD and A2 = VDD, then the SC16IS752’s address is set to 0x90(Write) and 0x91(Read), and the master communicates with it through this address.                                                 The second parameter in the read or write function is the internal register address, these are defined in the SC16IS752.h attached to this document and explained with greater detail in the SC16IS752 datasheet.                                                           3. The SC16IS752 is set to work at 115, 200 baud/s , the Receive Holding Register interrupt is enabled and routed to the INT1 pin that is configured to be a push-pull, active-low output. The registers are shift 3 positions left because the UART's internal register select are the bits 3:0, as shown in table 33. In the example channel 0 is used. This initialization is based in the application notes AN10587 and AN10462, where is possible to find additional information in regards the SC16IS752 // Program channel A for I2C-UART void SC16IS752_Init_ChA (void) {      I2C_WriteRegister(SC16IS752_ADDRESS, LCR_REG     << 3, 0x80);            // 0x80 when LCR[7] = 1 DLL and DLH are accessible      I2C_WriteRegister(SC16IS752_ADDRESS, DLL_REG     << 3, 0x08);         // 0x08 = 115,200 baud rate when XTal = 14.7456 MHz      I2C_WriteRegister(SC16IS752_ADDRESS, DLH_REG     << 3, 0x00);         // 0x00 = 115,200 baud rate when XTal = 14.7456 MHz      I2C_WriteRegister(SC16IS752_ADDRESS, LCR_REG     << 3, 0xBF);            // Access special features register      I2C_WriteRegister(SC16IS752_ADDRESS, EFR_REG     << 3, 0x10);            // enable enhanced functions      I2C_WriteRegister(SC16IS752_ADDRESS, LCR_REG     << 3, 0x03);            // 8 data bit, 1 stop bit, no parity           I2C_WriteRegister(SC16IS752_ADDRESS, IODIR_REG   << 3, 0xFF);            // set GPIO [7:0] to output (input by default)      I2C_WriteRegister(SC16IS752_ADDRESS, IOSTATE_REG << 3, 0x00);            // set GPIO [7:0] to 0x00 (Turn LEDs on)      I2C_WriteRegister(SC16IS752_ADDRESS, IER_REG     << 3, 0x01);            // enable Rx data ready interrupt }‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ 4. In the interrupt service routine the program reads the interrupt identification register, and it's ready to add a different task for each interrupt, for now it simply enables the data ready flag when the interrupt was generated by the RHR. It also cleans the flag that generated the interrupt. We also have the write function and the read function of the SC16IS752, these two functions access the corresponding THR or RHR registers. void PORTA_IRQHandler() {      //Interrupt service routine      Interrupt_Source iir = I2C_ReadRegister(SC16IS752_ADDRESS, IIR_REG << 3);   //read IIR to retrieve the interrupt source      // IIR[5:1] 5-bit encoded interrupt      switch(iir & 0x3E) {           case RHR: DataReady = 1; break;           default : break;      }      PORTA_PCR16 |= PORT_PCR_ISF_MASK;               // Clear the interrupt flag } void writeSC16IS752(char data) {      I2C_WriteRegister(SC16IS752_ADDRESS, FCR_REG <<3, 0x04);              //clears the contents of the transmit FIFO      while(!(I2C_ReadRegister(SC16IS752_ADDRESS, LSR_REG <<3) & 0x40));    //Is it able to transmit? - Poll Transmit empty indicator      I2C_WriteRegister(SC16IS752_ADDRESS, THR_REG << 3, data);             //Write to the transmit holding register to start transmission } unsigned char readSC16IS752(void) {      return I2C_ReadRegister(SC16IS752_ADDRESS,RHR_REG);                  //Read receive holding register } ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ 5. We connect the I 2 C lines with each other in the board, JP6 contains INT1, SDA and SCL in that order, then P1 is connected to EVBUSB2SER (USB to serial device), and this last one to a computer. In the computer must be installed a serial terminal,   for this example Teraterm is used                 We set up Tera Term going to Setup > Serial Port and then select corresponding port to the EVBUSB2SER and baud rate 115,200 This is the main, that should be executed to perform the echo function char DataReady; int main(void) {      unsigned char echo = 0;      MCU_Init();      Pause(500000);      SC16IS752_Init_ChA();      for (;;) {           if(DataReady) {                DataReady = 0;                echo = readSC16IS752();            //Read RHR, since FIFO is disable it only reads the first location                writeSC16IS752(echo);            //Send back the value received           }      }      return 0; }‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ After this, every character written in the serial terminal will appear in the serial terminal as you were writing in the command prompt Attached you can find the complete source code written using KDS IDE and some other relevant documentation   If there are any questions regarding this simple application, do not hesitate to ask below. Your feedback or suggestions are also welcome.   Thanks to a major collaborator for this document david_diaz‌. Regards, Darío Arias
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The following wikis provide useful “how to” and FAQ information not available on Freescale websites or forums. The links below provide useful design resources for product designers and users. eGUI PEG GUI StarCore DSPs
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Hi, Trying download and debug in IAR for MAC57D54H from NXP but get an error as: "Warning:Stack pointer is setup to incorrect alignment.Stack addr=0xFFFFFFFF" What would be the reason?
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Subject:  Info on FET BUK7909-75AIE Description:  The datasheet for part number BUK7909-75AIE describes it as qualified to AEC standard for use in automotive critical applications.  It also says it is Q101 compliant.  We are not familiar with these automotive standards but would like to know if samples have been tested for either these or similar qualification tests: Lifetesting Tempeature Cycling HAST or 85/85. I am expecting the automotive qual to meet or exceed these requirements, but need to be sure that device samples or devices from the same process have had qualification testing performed.  Please comment. Also, we need to know if there is an MSL rating for this part?  Finally, what is the terminal finish?  What is the long-term availability.  WE are looking to use these to replace an obsolete FET from IR/Infineon, and we want to be sure it will remain available.
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Here an example project using the PCF8563 is shown to demonstrate the easy use of the RTC devices from NXP. The PCF8563 is a real-time clock based on an ultra -low power oscillator and using an I 2 C- bus for interfacing. 
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************************************************************************************************************** The FRDM-A9957HN is an EVB designed for evaluation of PCA9957 daisy-chain SPI-compatible 4-wire serial bus controlled 24-channel constant current LED driver optimized for dimming and blinking 32 mA Red/Green/Blue/Amber (RGBA) LEDs. * The FRDM-A9957HN is designed to be used with FRDM-KL25Z Freedom Development Platform and an SDK example code.  * * Connection:      FRDM-KL25Z           OM13513 * VDD                 J9-4                           J9-2                                                                                                           * VDDIO             J9-8                            J9-4 * GND                 J2-14                         J2-7 * MOSI               J2-8                            J2-4 * MISO               J2-10                          J2-5 * SCLK               J2-12                          J2-6 * CS                   J2-6                            J2-3 * RESET            J9-6                            J9-3 ***************************************************************************************************************  
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*************************************************************************************************** The PCA9957 is a daisy-chain SPI-compatible 4-wire serial bus controlled 24-channel constant current LED driver optimized for dimming and blinking 32 mA Red/Green/Blue/Amber (RGBA) LEDs. * This simple example code was created for FRDM-KL25Z freedom board plus FRDM-A9957HN evaluation board. The code is sets the PCA9957 for the gradation control of all LED channels. * * Connection:      FRDM-KL25Z           OM13513 * VDD                 J9-4                           J9-2                                                                                                           * VDDIO             J9-8                            J9-4 * GND                 J2-14                         J2-7 * MOSI               J2-8                            J2-4 * MISO               J2-10                          J2-5 * SCLK               J2-12                          J2-6 * CS                   J2-6                            J2-3 * RESET            J9-6                            J9-3 ***************************************************************************************************
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Q1. What is the difference between A and B? CBTL02043A has input and output pins on the opposite of the package, and is suitable for edge connector(s) with different signal sources on the motherboard. CBTL02043B has outputs on both sides of the package, and the device can be placed between two connectors to multiplex differential signals from a controller.     Q2. Can CBTL02043 be used for HDMI applications? No, CBTL02043 cannot be used for HDMI applications. HDMI TMDS signal has its DC termination supply voltage at 3.3V +/-5%. CBTL02043 maximum input voltage at differential pins is limited at 2.4V, only.   Q3. How does CBTL02043 affect the system channel loss budget? CBTL02043 will brings in extra insertion loss to the system. CBTL02043 has −1.3 dB loss at 4 GHz, which is equivalent to about 1.5 inch (3.81 cm) to 2 inch (5.08 cm) FR4 PCB loss. The system designers need to take this MUX insertion loss into account when planning the system loss budget.   Q4. Are there SPICE, IBIS or S-parameter models available for CBTL02043? There is no SPICE model. IBIS/S-parameter models can be found below in attachments.   Q5. How to bias the high-speed switch?   PCIe, DP, USB3, and SATA electrical signals require AC coupling between the transmitter and receiver. The AC coupling capacitors are usually placed close to the transmitter. CBTL02043 requires a bias voltage, less than 2 V, applied to its switches. There are several AC coupling capacitor placement options:   A. The capacitors can be placed between the MUX and the downstream controller, and the MUX is biased by the upstream controller.   B. The capacitors can be placed between the upstream transmitter and the MUX. RX signals on the motherboard sides usually do not require AC coupling capacitors since those capacitors are located on the add-in card. The TX MUX is biased by the downstream controller, and the RX MUX is biased by the upstream controller.   C. Do not place capacitors at both side of MUX, unless a bias voltage is provided. In case of that both upstream and downstream controllers’ common-mode voltage is higher than 2 V, a bias voltage, which is less than 2 V, is needed for CBTL02043. The following figure shows an implementation in this case.
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This simple method, commonly used by RF engineers every day, is effective for creating a fast change of frequency range in a demo circuit, when you only have something close to work with. Your ability to use Freescale RF Power products as drop-ins is increased! In addition to being able to purchase a demonstration board, you can download any of the available DXF files for the PCB layout and order the board and list of materials for your production line. In many cases, you may be able to save money by choosing, testing, and qualifying your own list of less costly components. The initial design work is done with a Freescale demo board! The tuning, manufacturing and qualification process is all that is left to you. Thanks for choosing Freescale RF Power!
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********************************************************************************************************* * This simple example code has been written for the FRDM-KL25Z + FRDM-FXS-MULT2-B * boards and demonstrates how to use the embedded magnetic threshold detection * function in conjunction with the auto-wake/sleep mode for reducing current * consumption of the FXOS8700CQ. * * The magnetic threshold is set to 100uT (1000 counts) on the X and Y axis. * Once this threshold is exceeded, the FXOS8700CQ is waken up and an interrupt * is generated on the INT1 pin. If the magnetic field is below this threshold * within the 20ms period, the FXOS8700CQ goes back to sleep mode and also * generates an interrupt on the INT1 pin. *********************************************************************************************************
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Q: How should I start to evaluate PEG? A:   Download: Desktop and Hardware Demos       Request for Window Builder  -  The free download is the full version of Window Builder, but no source code is provided, so applications can only be developed on provided compiled libraries (this by default is Windows, but can be extended to a EVB such as the Tower System).        Request for further evaluation please contact Freescale sales or distributor representative. Q: Is PEG software supported on NON-Freescale and Freescale silicon? A: Yes, PEG Software can be licensed for for NON-Freescale and Freescale silicon. There is a discount when used with Freescale silicon. Q:  Is the cost limited to 10,000 pieces? A:  There are 4 licensing models.       1) PEG Base Single Product/MCU (3 seats, <=10,000 units, 1 year support) is specific to the processor used AND the specific name and model of the customer end product.      2) Upgrade - Unlimited Run-time for PEG Base:  There are NO limits on the number of run-time units for the PEG Base Single Product/MCU      3) Upgrade - Same MCU across  Product Family (+3 seats, unlimited run-time): Supports a family of customer end products that use the same processor      4) Upgrade - Multi MCU across  Product Family (+6 seats, unlimited run-time): Supports a family of customer end products that use multiple processors Q: Is technical support included? A:  One year of support is included with the purchase of a license and can always renew. Q: How does the actual GUI image (in the frame buffer) get updated through interrupt routines or some other method. A:  PEG implemented a scheduler that runs at a defined rate (20 times per second by default) and quickly checks a messaging queue.  If updates to the image are required, then the appropriate actions are taken to update the screen. Q: How is the frame buffer decided on?  Does PEG do it as needed or does the designer set the size and update as needed? A: PEG will define the require space for the frame buffer depending on the screen resolution, color depth, and number of buffers (i.e double-buffering, multiple surfaces, etc…) Q: Do we have examples of wave form generation code with anti-aliasing filters? A: There are examples of PEG drawing a variety of graphs (in the demo folder of PEG). Q: What drivers hardware and screen drivers are supported? A: PEG screen drivers can be developed for virtually any processor/controller. The list here includes devices for which drivers currently exist. Q: How can I purchase PEG? A: You can purchase it direct please contact sales@swellsoftware.com or from a number of distributors/re-sellers:      - AIC Japan      - eCOS      - eSOL      - Express Logic      - Green Hills Software      - Microdigital      - Quadros      - Arrow      - Future      - Advent     
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Because of sometimes customer test fail on CAN short GND function, below shows the test step and result for verify. So need emphasize that EVB only works on debug mode.  Do not confuse about Debug/Normal mode and INIT/Normal mode in the state machine. You can short CAN on EVB every CAN points to GND, but actual in application customer boards sometimes the distance between CAN points and GND is so long and with more noise on bus line. so please take care of this short function should be meet the spec in datasheet.  ----Test 1: Test under INIT mode, CAN short GND function works well. Short CAN_L to GND, has a flag on CANL_.     We can’t write the CAN_LIN_MODE register, only can read.  After read CAN_LIN_MODE register, we find that CAN works on the normal mode.         ----Test 2: Test under normal mode operation after configure INIT_INT register. Short CANL to GND, the CANL_ flag set ‘1’ ,this CAN short to GND works well, without re-set the CAN_LIN_MODE register, then we read the information that CAN works on normal mode.     Setting the CAN in sleep mode then short CANL to GND,can’t detect the fault bit.  
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How can I distinguish between various MSC8154/MSC8156 devices? You can read the System Part and Revision ID Register (SPRIDR) from address  to get the part ID and revision ID numbers. Device             SPRIDR[PARTID] MSC8154                0x8304 MSC8154EC           0x831C MSC8154E             0x830C MSC8156               0x8302 MSC8156EC           0x831A MSC8156E             0x830A Revision           SPRIDR[REVID] Rev. 1                       0x0000 Rev. 2                       0x0001 [ return to top ] My configuration sets up the L2 unified cache/M2 memory to 256KB of M2 and 256 KB of L2 cache.  Does this mean L2 cache is 8 ways of 32 KB each? No. The L2/M2 is 512 KB, arranged in 8 ways of 64 KB each way. In your configuration, the L2 cache becomes 4 ways. Each way is still 64 KB. [ return to top ] Does an M3 ECC event trigger an interrupt? M3 memory is ECC-protected so a single-bit error is detected and corrected, therefore an interrupt is not necessary. [ return to top ] The L2 cache features 4 L2 software prefetch channels.  Are there 4 software prefetch channels per core or is this the total number per device? The L2 cache is private for each core, therefore the 4 software prefetch channels are per core. Each core configures its own set of L2 software prefetch registers. Each core can only configure its own L2. The L2 software prefetch registers cannot be configured externally from the DSP subsystem. [ return to top ] Do I need an I2C serial EEPROM for loading of the Reset Configuration Word (RCW)? No, there are other options for loading of the RCW besides the I2C serial EEPROM. Multiplexed RCW loading option(RCW_SRC[0:2]=000) - all 64-bits of the RCW are loaded in four passes using the external pins RC[15:0]  using the /RCW_LSEL[0:3] pins as lane select signals. Reduced RCW loading option (RCW_SRC[0:2]=011) - some bits of the RCW are latched from external pins and some bits are loaded from default hard-coded values. [ return to top ] How does MSC8156 MAPLE-B TVPE support Viterbi and Turbo decoding? Turbo and Viterbi decoding are supported by MSC8156 MAPLE-B TVPE in same µcode. You can initialize the Maple with one TVPE standard, plus some Viterbi parameters. Then you can use different Buffer Descriptors for Turbo and Viterbi. Note that MAPLE-B doesn't support multiple Turbo standards with the same µcode because Maple µcode is standard specific and a µcode re-load is required to switch from one standard to another. So supporting a mixture of users of different standard in real time cannot be done with current MAPLE-B.  Turbo and Viterbi decoding are supported in same µcode, since Viterbi decoding parameters are fully configurable and are not standard related. [ return to top ] I want to use the Debug and Profiling Unit (DPU) in the MSC8156 to log information into the virtual trace buffer. I have set up the DPU registers for core 0. How do I set up the DPU for the other cores 1/2/3/4/5 since there is only one set of DPU registers? Each DSP subsystem includes a DPU. Each core can access its own DPU registers using the same physical addresses. [ return to top ] I only need to reset an individual core in the MSC8156. How can I do that? All cores are reset together. There is not a method to reset a particular core in the MSC8156. [ return to top ] The MSC8156 Reference Manual shows the default DDR1 and DDR2 memory address spaces are 512 MB. How do I change the memory space to 1 GB? The MSC8156 Reference Manual shows the DDR address spaces as follows: 0x40000000–0x5FFFFFFF      DDR1 Memory (default value)                                               512 M 0x60000000–0x7FFFFFFF      Reserved.  Used for DDR1 memory if configured for 1 GB.      512 M 0x80000000–0x9FFFFFFF      DDR2 Memory (default value)                                               512 M 0xA0000000–0xBFFFFFFF     Reserved. Used for DDR2 memory if configured for 1 GB.       512 M After reset, the default DDR1 and DDR2 memory space is 512 MB. To increase to 1GB DDR memory range, you need to configure the CLASS registers as follows: For DDR1 memory controller, change C0EAD5 from the reset value of 0x0005FFFF to 0x0007FFFF [ return to top ] What is the maximum heat sink attachment force to avoid damaging the solder balls? Detailed information about the Flip-Chip Plastic Ball Grid Array (FC-PBGA) package type devices (MSC8144 and MSC8156) can be found in this document FC-PBGAPRES.pdf The maximum heat sink attachment force is 4 Newtons (10 lb force). [ return to top ] What does the NO_INC bit indicate in the DMA buffer descriptor BD_ATTR field? When would you use this? You can set NO_INC if you want to transfer to or from the same address. The address will not be incremented. For example, if you want to fill memory with data from a single memory location, you will need to set NO_INC for the source. However, the destination will have the NO_INC bit cleared. [ return to top ] If a MSC8156 DMA port A or B bus error happens, i.e., DMAERR[PAE] or DMAERR[PBE] bit is set, can I clear these bits and continue with the DMA operation? A port error will freeze the DMA channel so clearing the error bit has no effect. In this case, the DMA channel needs to be reinitialized before it can be used again. [ return to top ] If a DMA BD size 0 error occurs, i.e., DMAERR[BDSZ] is set, to indicate that the buffer descriptor field BD_SIZE is cleared, how can I tell which DMA channel is associated with the error? The DMAERR register does not indicate which channel accessed the BD with size 0. However, you can check the DMACHCRx registers to determine which channel did not finish the transfer by checking if the active ACT bit is high. A channel that does not encounter the error will finish (ACT bit gets cleared). [ return to top ] .
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