Q1: Why DisplayPort to LVDS adapter? DPRX-LVDS is an (embedded) DisplayPort to LVDS bridge device that enables connectivity between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and transmits processed stream in LVDS format.   NXP offers two eDP-LVDS devices: 1. PTN3460 is commercial grade, 0 – 70 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 25 MHz to 112 MHz. 2. PTN3460I is industrial grade, -40 – 85 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 6 MHz to 112 MHz.   Q2. How to configure eDP-LVDS device?   The eDP-LVDS has embedded microcontroller and on-chip Non-Volatile Memory (NVM) to allow for flexibility in firmware updates.   Both PTN3460 and PTN3460I have a built in configuration table in internal 1K SRAM, which allows users to program seven EDID and 128 configuration registers through M/S I2C-bus. Please follow the programming guides below for these devices. 1. AN11128 – Programming Guide for PTN3460 2. AN11606 – Programming Guide for PTN3460I   Q3. What is maximum resolution DP-LVDS can support? The available bandwidth over a 2-lane HBR DisplayPort v1.4 link limits pixel clock rate support to: 1. 1-lane DP with single LVDS bus supports 800x600 @ 60 Hz display, 40 MHz pixel clock. 2. 1-lane DP with dual LVDS bus supports 1366x768 @ 60 Hz display, 85.5 MHz pixel clock. 3. 2-lane DP with single LVDS bus operation up to 112 mega pixel per second – supports 1440x900 @ 60 Hz resolution display. 4. 2-lane DP with dual LVDS bus operation up to 224 mega pixel per second – supports 1920x1200 @ 60 Hz resolution display.   Q4. How to update the FW? FW for eDP-LVDS devices can be updated by the following methods: 1. Flash over AUX (FoA) – This is an executable window utility that can only run under Windows OS. FW is updated through DP AUX channel. AN11133 – PTN3460 FoA utility user’s guide. 2. Flash over DOS (FoD) – This is an executable DOS utility that can run under DOS without OS. FW is updated through M/S I2C bus. 3. Flash over I2C – FW is updated through external I2C device that is plugged in a M/S I2C header.   Q5. How to check the FW version? FW version can be read out with DPCD utility that runs under Windows OS. Please follow DPCD Tool User Manual V1.0.   Q6. How many DP lanes supported in NXP DP to LVDS bridge device? NXP DP to LVDS bridge device supports 2 lanes HBR/RBR.   Q7. What does HBR/RBR mean? HBR means “High Bit Rate”, it runs 2.7 Gbit/s. RBR means “Reduced Bit Rate”, it runs 1.62 Gbit/s.   Q8. What is DP AUX channel? DP AUX channel is used for communication channel between DP source and DP sink device.   Q9. What is DP source device? DP source device is DP signal transmitter.   Q10. What is DP sink device? DP sink device is DP signal receiver.

Hi, Trying download and debug in IAR for MAC57D54H from NXP but get an error as: "Warning:Stack pointer is setup to incorrect alignment.Stack addr=0xFFFFFFFF" What would be the reason?

Subject:  Info on FET BUK7909-75AIE Description:  The datasheet for part number BUK7909-75AIE describes it as qualified to AEC standard for use in automotive critical applications.  It also says it is Q101 compliant.  We are not familiar with these automotive standards but would like to know if samples have been tested for either these or similar qualification tests: Lifetesting Tempeature Cycling HAST or 85/85. I am expecting the automotive qual to meet or exceed these requirements, but need to be sure that device samples or devices from the same process have had qualification testing performed.  Please comment. Also, we need to know if there is an MSL rating for this part?  Finally, what is the terminal finish?  What is the long-term availability.  WE are looking to use these to replace an obsolete FET from IR/Infineon, and we want to be sure it will remain available.

********************************************************************************* * Detailed Description: * Updated the example lwip_FreeRTOS_SJA1110 for board MR-T1ETH8 * to enable ping from the command window, from all applicable ports * *ping 192.168.0.200 * *Pinging 192.168.0.200 with 32 bytes of data: *Reply from 192.168.0.200: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.200: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.200: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.200: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.200: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * Installed packages to S32DS 3.5 update 14: * SW32SJA11xx_S32DS_3.5.0_RFP_D2206.zip * SJA11XX_RTD_4.4_1.0.1_P02_HF01_D2510_DesignStudio_updatesite.zip * SW32SJA1110_XJA11XX_ETH_PHY_4.4_1.0.8_CD01_D2509_DesignStudio_updatesite.zip * SJA11XX_ETH_SWITCH_4.4_1.0.2_CD01_D2509_DesignStudio_updatesite.zip * SW32SJA11xx_FreeRTOS_11.1.0_0.8.0_CD2_D2411_DesignStudio_updatesite.zip * SJA11XX_TCPIP_2.0.0_CD01_D2510_DesignStudio_updatesite.zip * * EVB * - to enable flashing by Lauterbach TRACE32 - Populate R78, DNP R77 * * Configuration: * - Updated switch configuration * - Updated phy configuration * - Fixed Mcu/McuModuleConfiguration/McuPowerControlUnit - 1V8 and 2V5 * - Fixed Eth configuration * <setting name="EthMaxFrameLength" value="1518"/> * <setting name="EthCtrlConfigEgressFifoBufLenByte" value="1536"/> * <setting name="EthCtrlConfigIngressFifoBufLenByte" value="1536"/> * - TCPIP stack: enabled UDP_ECHO, etc. * - Added DIO * - Added nvm_metadata * - MAC learning is disabled * - All available ports initialized * - All ports checked, except 1 Gbit/s ix Industrial connector (J9) * * main.c * - Updated only the header * device.c * - Added LED routines * test.c * - Removed code that shuts down the TCP/IP stack after its predefined timeout * - Added debug stuff * - Commented out the code that initializes 2nd switch * * ----------------------------------------------------------------------------- * Test HW: MR-T1ETH8 * MCU: SJA1110 * Debugger: Lauterbach TRACE32 * Target: RAM or external FLASH (flash_image.bin generated) * EVB connection: any port <-> RDDRONE T1ADAPT (on ports where applicable) <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

********************************************************************************* * Detailed Description: * Updated the example lwip_FreeRTOS_SJA1110 for board SJA1110-MGS-EVM * to enable ping from the command window, from all applicable ports * *ping 192.168.0.200 * *Pinging 192.168.0.200 with 32 bytes of data: *Reply from 192.168.0.200: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.200: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.200: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.200: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.200: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * Installed packages to S32DS 3.5 update 14: * SW32SJA11xx_S32DS_3.5.0_RFP_D2206.zip * SJA11XX_RTD_4.4_1.0.1_P02_HF01_D2510_DesignStudio_updatesite.zip * SW32SJA1110_XJA11XX_ETH_PHY_4.4_1.0.8_CD01_D2509_DesignStudio_updatesite.zip * SJA11XX_ETH_SWITCH_4.4_1.0.2_CD01_D2509_DesignStudio_updatesite.zip * SW32SJA11xx_FreeRTOS_11.1.0_0.8.0_CD2_D2411_DesignStudio_updatesite.zip * SJA11XX_TCPIP_2.0.0_CD01_D2510_DesignStudio_updatesite.zip * * EVB: * - All jumpers in default positions, except J76 - open * - SW2.7 ON and SW2.6 OFF -> 0b01 - NVM Boot - SPI Flash * * Configuration: * - Updated switch configuration * - Updated phy configuration * - Fixed Mcu/McuModuleConfiguration/McuPowerControlUnit - 1V8 and 2V5 * - Fixed Eth configuration * <setting name="EthMaxFrameLength" value="1518"/> * <setting name="EthCtrlConfigEgressFifoBufLenByte" value="1536"/> * <setting name="EthCtrlConfigIngressFifoBufLenByte" value="1536"/> * - TCPIP stack: enabled UDP_ECHO, etc. * - Added DIO * - Added nvm_metadata * - MAC learning is disabled * - All ports initialized, except: * - TJA1104B - Port 2 SGMII * - Port 3 2.5G SGMII has not been tested * - cage - Port 4 SGMII * * Copied pcal9722 driver from SJA1110_MGS_Minimal (from package SJA1110 examples 0.2.0) * - fixed to MCAL Spi driver * - Updated Spi configuration * * main.c * - Updated only the header * device.c * - Added LED routines * test.c * - Removed code that shuts down the TCP/IP stack after its predefined timeout * - Added LED ALIVE task * - Added RX/TX blinking LED * - Added debug stuff * - Commented out the code that initializes 2nd switch * * ----------------------------------------------------------------------------- * Test HW: SJA1110-MGS-EVM SCH-94089_B1 * MCU: SJA1110 * Debugger: Lauterbach TRACE32 * Target: RAM or external FLASH (flash_image.bin generated) * EVB connection: any port <-> Media converter TE-1402 (1000M or 100M, Leader) <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

S32G-VNP-RDB2 Note: S32G-VNP-RDB2 examples can be used also on S32G-VNP-RDB3. Example SJA1110 FreeRTOS lwIP S32G-VNP-RDB2 S32DS 3.5 RTD 1.0.2   SJA1110-MGS-EVM Example SJA1110 FreeRTOS lwIP SJA1110-MGS-EVM S32DS 3.5 RTD 1.0.2   MR-T1ETH8 Example SJA1110 FreeRTOS lwIP MR-T1ETH8 S32DS 3.5 RTD 1.0.2

********************************************************************************* * Detailed Description: * Updated the example lwip_FreeRTOS_SJA1110 for board S32G-VNP-RDB2 * to enable ping from the command window, from all applicable ports * *ping 192.168.0.210 * *Pinging 192.168.0.210 with 32 bytes of data: *Reply from 192.168.0.210: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.210: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.210: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.210: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.210: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * Installed packages to S32DS 3.5 update 14: * SW32SJA11xx_S32DS_3.5.0_RFP_D2206.zip * SJA11XX_RTD_4.4_1.0.1_P02_HF01_D2510_DesignStudio_updatesite.zip * SW32SJA1110_XJA11XX_ETH_PHY_4.4_1.0.8_CD01_D2509_DesignStudio_updatesite.zip * SJA11XX_ETH_SWITCH_4.4_1.0.2_CD01_D2509_DesignStudio_updatesite.zip * SW32SJA11xx_FreeRTOS_11.1.0_0.8.0_CD2_D2411_DesignStudio_updatesite.zip * SJA11XX_TCPIP_2.0.0_CD01_D2510_DesignStudio_updatesite.zip * * EVB: * - SW10[1]: On, SW10[2]: Off * - SW12[1]: On, SW12[2]: Off * * Configuration: * - Updated switch configuration * - Updated phy configuration * - Fixed Mcu/McuModuleConfiguration/McuPowerControlUnit - 1V8 and 2V5 * - Fixed Eth configuration * <setting name="EthMaxFrameLength" value="1518"/> * <setting name="EthCtrlConfigEgressFifoBufLenByte" value="1536"/> * <setting name="EthCtrlConfigIngressFifoBufLenByte" value="1536"/> * - TCPIP stack: enabled UDP_ECHO, etc. * - Changed IP address to 192.168.0.210 * - Added DIO * - Added nvm_metadata * - MAC learning is disabled * - The example includes two flash images for Port 4 SGMII speed * configuration towards the S32G: * - flash_image_2G5.bin (tested) * - flash_image_1G.bin (not tested) * * main.c * - Updated only the header * device.c * - Added LED routines * test.c * - Removed code that shuts down the TCP/IP stack after its predefined timeout * - Added debug stuff * - Commented out the code that initializes 2nd switch * * ----------------------------------------------------------------------------- * Test HW: S32G-VNP-RDB2 REV E * MCU: SJA1110A * Debugger: Lauterbach TRACE32 * Target: RAM or external FLASH (flash_image.bin generated) * EVB connection: any port <-> RDDRONE T1ADAPT (on ports where applicable) <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

This article describes how to correctly install the SGTL5000 GUI on an existing Windows OS. and install documentations Since the initial user guide was written over a decade or two ago, the installation steps described in it have become invalid by now.

I would like to present a bare-metal example project named MK22F51212_Project_FXLS8974CF, developed for the FXLS8974CF accelerometer. This project utilizes the FRDM-STBC-FNM03 multisensory board in combination with the FRDM-K22F Freedom Kinetis MCU board, and was created using the MCUXpresso IDE. Hardware Setup To ensure proper functionality, please configure the jumpers on the multisensory board as follows: J5: 3–4 — Powers the FXLS8974CF sensor J9: 1–2 — Enables Motion Detection mode J10: 1-2 — If BT_MODE=VDD (J9: 1-2) must be populated All other jumpers can remain open Project Functionality The K22F MCU continuously reads the following registers from the FXLS8974CF sensor in an infinite loop: OUT_X_LSB, OUT_X_MSB OUT_Y_LSB, OUT_Y_MSB OUT_Z_LSB, OUT_Z_MSB The raw data is first stored in the g_master_rxBuff array, then parsed into the accelX, accelY, and accelZ variables. To convert the raw data into acceleration values (in g), divide each value by the nominal sensitivity of 512, which corresponds to the default ±4g measurement range. Building and Debugging Once the project is imported into MCUXpresso IDE, follow these steps: 1. Clean and Build the project 2. Debug the project as LinkServer and Run the application 3. View the raw and/or processed acceleration values in the Global Variables Window Data Visualization with FreeMASTER To visualize the accelerometer data using FreeMASTER, follow these steps: Download and launch the latest version of FreeMASTER Terminate the debug session in MCUXpresso IDE Ensure the FRDM-STBC-FNM03 + FRDM-K22F kit is still connected to your PC In FreeMASTER, open the Connection Wizard and configure as follows: Select “Connect through a debugger probe or on-board debugger interface”  Choose “CMSIS-DAP compliant interface from ARM”  Select “Direct access to target microcontroller memory” Click “Plug-in Configuration”                 9. Test the connection. If successful, click OK twice and then Finish                       10. Click “Open an Existing Project” and locate the Project.pmpx file in your                              MCUXpresso workspace                   Now you can observe live accelerometer data in the FreeMASTER Oscilloscope or Variable Watch Window.   Attached are: FRDM-STBC-FNM03 multisensory board GERBER files and BOM, and Project for the KIT.  Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design.  Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction. 

Here an example project using the PCF8563 is shown to demonstrate the easy use of the RTC devices from NXP. The PCF8563 is a real-time clock based on an ultra -low power oscillator and using an I 2 C- bus for interfacing. 

************************************************************************************************************** The FRDM-A9957HN is an EVB designed for evaluation of PCA9957 daisy-chain SPI-compatible 4-wire serial bus controlled 24-channel constant current LED driver optimized for dimming and blinking 32 mA Red/Green/Blue/Amber (RGBA) LEDs. * The FRDM-A9957HN is designed to be used with FRDM-KL25Z Freedom Development Platform and an SDK example code.  * * Connection:      FRDM-KL25Z           OM13513 * VDD                 J9-4                           J9-2                                                                                                           * VDDIO             J9-8                            J9-4 * GND                 J2-14                         J2-7 * MOSI               J2-8                            J2-4 * MISO               J2-10                          J2-5 * SCLK               J2-12                          J2-6 * CS                   J2-6                            J2-3 * RESET            J9-6                            J9-3 ***************************************************************************************************************  

*************************************************************************************************** The PCA9957 is a daisy-chain SPI-compatible 4-wire serial bus controlled 24-channel constant current LED driver optimized for dimming and blinking 32 mA Red/Green/Blue/Amber (RGBA) LEDs. * This simple example code was created for FRDM-KL25Z freedom board plus FRDM-A9957HN evaluation board. The code is sets the PCA9957 for the gradation control of all LED channels. * * Connection:      FRDM-KL25Z          FRDM-A9957HN * VDD                 J9-4                           J9-2                                                                                                           * VDDIO             J9-8                            J9-4 * GND                 J2-14                         J2-7 * MOSI               J2-8                            J2-4 * MISO               J2-10                          J2-5 * SCLK               J2-12                          J2-6 * CS                   J2-6                            J2-3 * RESET            J9-6                            J9-3 ***************************************************************************************************

   

   

Q1. What is the difference between A and B? CBTL02043A has input and output pins on the opposite of the package, and is suitable for edge connector(s) with different signal sources on the motherboard. CBTL02043B has outputs on both sides of the package, and the device can be placed between two connectors to multiplex differential signals from a controller.     Q2. Can CBTL02043 be used for HDMI applications? No, CBTL02043 cannot be used for HDMI applications. HDMI TMDS signal has its DC termination supply voltage at 3.3V +/-5%. CBTL02043 maximum input voltage at differential pins is limited at 2.4V, only.   Q3. How does CBTL02043 affect the system channel loss budget? CBTL02043 will brings in extra insertion loss to the system. CBTL02043 has −1.3 dB loss at 4 GHz, which is equivalent to about 1.5 inch (3.81 cm) to 2 inch (5.08 cm) FR4 PCB loss. The system designers need to take this MUX insertion loss into account when planning the system loss budget.   Q4. Are there SPICE, IBIS or S-parameter models available for CBTL02043? There is no SPICE model. IBIS/S-parameter models can be found below in attachments.   Q5. How to bias the high-speed switch?   PCIe, DP, USB3, and SATA electrical signals require AC coupling between the transmitter and receiver. The AC coupling capacitors are usually placed close to the transmitter. CBTL02043 requires a bias voltage, less than 2 V, applied to its switches. There are several AC coupling capacitor placement options:   A. The capacitors can be placed between the MUX and the downstream controller, and the MUX is biased by the upstream controller.   B. The capacitors can be placed between the upstream transmitter and the MUX. RX signals on the motherboard sides usually do not require AC coupling capacitors since those capacitors are located on the add-in card. The TX MUX is biased by the downstream controller, and the RX MUX is biased by the upstream controller.   C. Do not place capacitors at both side of MUX, unless a bias voltage is provided. In case of that both upstream and downstream controllers’ common-mode voltage is higher than 2 V, a bias voltage, which is less than 2 V, is needed for CBTL02043. The following figure shows an implementation in this case.

This video shows the necessary configurations to flash a binary file to a target, in this case the FRDM-KL25

This simple method, commonly used by RF engineers every day, is effective for creating a fast change of frequency range in a demo circuit, when you only have something close to work with. Your ability to use Freescale RF Power products as drop-ins is increased! In addition to being able to purchase a demonstration board, you can download any of the available DXF files for the PCB layout and order the board and list of materials for your production line. In many cases, you may be able to save money by choosing, testing, and qualifying your own list of less costly components. The initial design work is done with a Freescale demo board! The tuning, manufacturing and qualification process is all that is left to you. Thanks for choosing Freescale RF Power!

********************************************************************************************************* * This simple example code has been written for the FRDM-KL25Z + FRDM-FXS-MULT2-B * boards and demonstrates how to use the embedded magnetic threshold detection * function in conjunction with the auto-wake/sleep mode for reducing current * consumption of the FXOS8700CQ. * * The magnetic threshold is set to 100uT (1000 counts) on the X and Y axis. * Once this threshold is exceeded, the FXOS8700CQ is waken up and an interrupt * is generated on the INT1 pin. If the magnetic field is below this threshold * within the 20ms period, the FXOS8700CQ goes back to sleep mode and also * generates an interrupt on the INT1 pin. *********************************************************************************************************

Q: How should I start to evaluate PEG? A:   Download: Desktop and Hardware Demos       Request for Window Builder  -  The free download is the full version of Window Builder, but no source code is provided, so applications can only be developed on provided compiled libraries (this by default is Windows, but can be extended to a EVB such as the Tower System).        Request for further evaluation please contact Freescale sales or distributor representative. Q: Is PEG software supported on NON-Freescale and Freescale silicon? A: Yes, PEG Software can be licensed for for NON-Freescale and Freescale silicon. There is a discount when used with Freescale silicon. Q:  Is the cost limited to 10,000 pieces? A:  There are 4 licensing models.       1) PEG Base Single Product/MCU (3 seats, <=10,000 units, 1 year support) is specific to the processor used AND the specific name and model of the customer end product.      2) Upgrade - Unlimited Run-time for PEG Base:  There are NO limits on the number of run-time units for the PEG Base Single Product/MCU      3) Upgrade - Same MCU across  Product Family (+3 seats, unlimited run-time): Supports a family of customer end products that use the same processor      4) Upgrade - Multi MCU across  Product Family (+6 seats, unlimited run-time): Supports a family of customer end products that use multiple processors Q: Is technical support included? A:  One year of support is included with the purchase of a license and can always renew. Q: How does the actual GUI image (in the frame buffer) get updated through interrupt routines or some other method. A:  PEG implemented a scheduler that runs at a defined rate (20 times per second by default) and quickly checks a messaging queue.  If updates to the image are required, then the appropriate actions are taken to update the screen. Q: How is the frame buffer decided on?  Does PEG do it as needed or does the designer set the size and update as needed? A: PEG will define the require space for the frame buffer depending on the screen resolution, color depth, and number of buffers (i.e double-buffering, multiple surfaces, etc…) Q: Do we have examples of wave form generation code with anti-aliasing filters? A: There are examples of PEG drawing a variety of graphs (in the demo folder of PEG). Q: What drivers hardware and screen drivers are supported? A: PEG screen drivers can be developed for virtually any processor/controller. The list here includes devices for which drivers currently exist. Q: How can I purchase PEG? A: You can purchase it direct please contact [email protected] or from a number of distributors/re-sellers:      - AIC Japan      - eCOS      - eSOL      - Express Logic      - Green Hills Software      - Microdigital      - Quadros      - Arrow      - Future      - Advent     

Because of sometimes customer test fail on CAN short GND function, below shows the test step and result for verify. So need emphasize that EVB only works on debug mode.  Do not confuse about Debug/Normal mode and INIT/Normal mode in the state machine. You can short CAN on EVB every CAN points to GND, but actual in application customer boards sometimes the distance between CAN points and GND is so long and with more noise on bus line. so please take care of this short function should be meet the spec in datasheet.  ----Test 1: Test under INIT mode, CAN short GND function works well. Short CAN_L to GND, has a flag on CANL_.     We can’t write the CAN_LIN_MODE register, only can read.  After read CAN_LIN_MODE register, we find that CAN works on the normal mode.         ----Test 2: Test under normal mode operation after configure INIT_INT register. Short CANL to GND, the CANL_ flag set ‘1’ ,this CAN short to GND works well, without re-set the CAN_LIN_MODE register, then we read the information that CAN works on normal mode.     Setting the CAN in sleep mode then short CANL to GND,can’t detect the fault bit.