DPRX-LVDS is an (embedded) DisplayPort to LVDS bridge device that enables connectivity between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and transmits processed stream in LVDS format.
NXP offers two eDP-LVDS devices:
1. PTN3460 is commercial grade, 0 – 70 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 25 MHz to 112 MHz.
2. PTN3460I is industrial grade, -40 – 85 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 6 MHz to 112 MHz.
Q2. How to configure eDP-LVDS device?
The eDP-LVDS has embedded microcontroller and on-chip Non-Volatile Memory (NVM) to allow for flexibility in firmware updates.
Both PTN3460 and PTN3460I have a built in configuration table in internal 1K SRAM, which allows users to program seven EDID and 128 configuration registers through M/S I2C-bus. Please follow the programming guides below for these devices.
1. AN11128 – Programming Guide for PTN3460
2. AN11606 – Programming Guide for PTN3460I
Q3. What is maximum resolution DP-LVDS can support?
The available bandwidth over a 2-lane HBR DisplayPort v1.4 link limits pixel clock rate support to:
1. 1-lane DP with single LVDS bus supports 800x600 @ 60 Hz display, 40 MHz pixel clock.
2. 1-lane DP with dual LVDS bus supports 1366x768 @ 60 Hz display, 85.5 MHz pixel clock.
3. 2-lane DP with single LVDS bus operation up to 112 mega pixel per second – supports 1440x900 @ 60 Hz resolution display.
4. 2-lane DP with dual LVDS bus operation up to 224 mega pixel per second – supports 1920x1200 @ 60 Hz resolution display.
Q4. How to update the FW?
FW for eDP-LVDS devices can be updated by the following methods:
1. Flash over AUX (FoA) – This is an executable window utility that can only run under Windows OS. FW is updated through DP AUX channel.
AN11133 – PTN3460 FoA utility user’s guide.
2. Flash over DOS (FoD) – This is an executable DOS utility that can run under DOS without OS. FW is updated through M/S I2C bus.
3. Flash over I2C – FW is updated through external I2C device that is plugged in a M/S I2C header.
Q5. How to check the FW version?
FW version can be read out with DPCD utility that runs under Windows OS. Please follow DPCD Tool User Manual V1.0.
Q6. How many DP lanes supported in NXP DP to LVDS bridge device?
NXP DP to LVDS bridge device supports 2 lanes HBR/RBR.
Q7. What does HBR/RBR mean?
HBR means “High Bit Rate”, it runs 2.7 Gbit/s.
RBR means “Reduced Bit Rate”, it runs 1.62 Gbit/s.
Q8. What is DP AUX channel?
DP AUX channel is used for communication channel between DP source and DP sink device.