LA1224 FR1/FR2 テストツール (v5.1):シングルキャリア波形にオプション8時間領域注入を使用する LA1224 FR1/FR2 テストツール (v5.1):シングルキャリア波形に Option8 時間領域インジェクションを使用する場合、専用のイメージ/カーネル構成が必要ですか? こんにちは、NXPチームの皆様、 私はLA1224-RDB-BHSとFR1/FR2テストツールv5.1、およびこのツールのVSPAイメージ（例：MEvspa_images_HS.2T2R_400M_120K_1966_1966_TDDFDD）を使用して、オプション8時間領域モードでのFR2シングルキャリア（SC）波形伝送を検証しています。私は、LA1224-FR2-BRK と SMA ケーブルを使用して、単一の LA1224-RDB-BHS デバイスで TX を RX にループバックしています。 実行した手順: 1. 491.52 Msps (int16 IQ インターリーブ) で 10 ms の複素 IQ 波形を生成します。ファイル サイズは 19,660,800 バイトです。 2. 次の方法でロードします: ./boot_vspa.sh MEvspa_images_HS.2T2R_400M_120K_1966_1966_TDDFDD ./channels_start.sh 4 ./set_dfe_state.sh 4 正常 ./update_test_vector.sh my_waveform_10ms.bin ./dump_time_domain_tx.sh 4 ./dump_time_domain_rx.sh 4 取得したダンプ: - TXダンプ: tx_timedomain_20ms_1966080ksps_dump_ant4.bin (Fs=1.96608GSP) - RXダンプ: rx_timedomain_20ms_983040ksps_dump_ant4.bin (Fs=983.04 Msps) MATLAB 相関ベースのアライメントとベストウィンドウ比較を実行しました。 観察: - 相関ピーク スコアは非常に高い (例: 約 0.998) ため、挿入された波形は確実に送受信されています。 - しかし、基準波形 (A) と TX ダンプ (B) の間で測定された EVM は無視できません。 - PN/BPSK + RRCテスト波形の場合：A→B EVM ≈ 6.75% (NMSE ≈ -23.4 dB) - 別のSC波形の場合: A→B EVM ≈ 22.8% - 一部のカーネルを無効にしても EVM は大幅に変化しません。 ./kernels_disable_tx.sh 4 qec cfr dpd ./update_fine_cfo_nco_freq.sh 4 0 （EVM/NMSEはほぼ変化なし） 質問: 1.シングルキャリア FR2 検証の場合、提供されている VSPA イメージ (OFDM SCS ベースの命名を使用) は依然として適切ですか、それとも専用のシングルキャリア最適化イメージがありますか? 2. オプション8の時間領域注入では、アップサンプリング/ダウンサンプリング/CFO/QECカーネルは常にプロセッシングチェーン内にありますか?SC 波形テストのためにそれらをバイパスする（または「透過的なパススルー」を保証する）サポートされている方法はありますか? 3. この設定では、(A) 注入波形と (B) TX ダンプ間の EVM フロアはどれくらいになると予想されますか?固定小数点/フィルタリングによる 6～7% という値は妥当なものでしょうか、それとも設定ミスを示しているのでしょうか。 必要に応じて、正確なスクリプト、構成、波形を提供できます。 よろしくお願いします！ Re: LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform LA1224 のサポートは非公開です。 サポートが必要な場合は、以下のリンクでCASEを作成し、NDA を添付してください。 https://support.nxp.com/s/?language=en_US ありがとうございます。 Re: LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform こんにちは！時間領域で生成されたファイルをFs 491.52 MHzに置き換えた場合、DUC x4はVSPA上で1966.08 MHzまで動作しますか？ DACと同じFs周波数、つまり1966.08MHzのタイムドメイン信号を生成する必要があると思います。

LA1224 FR1/FR2 测试工具（v5.1）：对单载波波形使用 Option8 时域注入 LA1224 FR1/FR2 测试工具（v5.1）：对单载波波形使用 Option8 时域注入 — 是否需要专用的映像/内核配置？ 您好，NXP团队： 我在这个工具中使用带有 FR1/FR2 测试工具 v5.1 的 LA1224-RDB-BHS 和 VSPA 图像（例如，mevspa_images_hs.2t2r_400m_120K_1966_1966_TDDFDD）来验证 Option8 时域模式下的 FR2 单载波 (SC) 波形传输。我在 LA1224-FR2-BRK 上使用 SMA 电缆在单个 LA1224-RDB-BHS 设备上将 TX 环回到 RX。 我执行的步骤： 1.以 491.52 Msps（int16 IQ 交错）生成 10 毫秒的复杂 IQ 波形，文件大小 19,660,800 字节。 2。通过以下方式加载: ./boot_vspa.sh mevspa_images_hs.2t2r_400m_120K_1966_1966_1966_tddfdd ./channels_start.sh 4 ./set_dfe_state.sh 4 normal ./update_test_vector.sh my_waveform_10ms.bin ./dump_time_domain_tx.sh 4 ./dump_time_domain_rx.sh 4 获得的转储： - TX 转储：tx_timedomain_20ms_1966080ksps_dump_ant4.bin（Fs=1.96608Gsps) - RX dump: rx_timedomain_20ms_983040ksps_dump_ant4.bin (Fs=983.04 Msps) 我进行了基于 MATLAB 相关性的配准和最佳窗口比较。 观察结果： - 相关性峰值分数非常高（如 ~0.998），因此注入的波形肯定正在传输和接收。 -但是，我的参考波形 (A) 和 TX 转储 (B) 之间测得的 EVM 不可忽略不计： -对于 PN/BPSK + RRC 测试波形：A→B EVM ≥ 6.75% (NMSE ⇒-23.4 dB)-对于另一个 SC 波形：A→B EVM ≥ 22.8% -禁用某些内核不会显著改变 EVM：。 /kernels_disable_tx.sh 4 qec cfr dpd。 /update_fine_cfo_nco_freq.sh 4 0 （EVM/NMSE 几乎没有变化） 问题： 1.对于单载波 FR2 验证，提供的 VSPA 映像（使用基于 OFDM SCS 的命名）是否仍然合适，或者是否有专用的单载波优化映像？ 2。在 Option8 时域注入中，上采样/下采样/CFO/QEC 内核是否总是在处理链中？ 3. 在此设置中，(A) 注入波形和 (B) TX dump 之间的预期 EVM 底线是多少？由于固定点/过滤， ~6-7% 是合理的，还是说明配置有误？ 如果需要，我可以提供准确的脚本、配置和波形。 谢谢您！ Re: LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform LA1224 支持不公开。 如果您需要帮助，请在下面的链接中创建一个案例，并附上您的 NDA： https://support.nxp.com/s/?language=en_US 谢谢。 Re: LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform 你好如果你将时域中生成的文件替换为 Fs 491.52 MHz，那么 DUC x4 在 VSPA 上能否以高达 1966.08 MHz 的速度运行？ 我相信你需要生成与 DAC 相同的 Fs 频率的时域信号，即 1966.08 MHz。

从 RT685 上的 DSP 向 PSRAM 写入数据 我使用的是 RT685 平台，通过 FlexSPI 连接 PSRAM。PSRAM (ISSI IS66WVR8M8FALL) 连接到端口 A2，QSPI 闪存连接到端口 A1。 PSRAM 被配置为通过 AHB 访问，FlexSPI 在启动后配置在 MCU 端，几分钟后从 DSP 端写入数据。从 DSP 端写入数据时，PSRAM 中存在一些 0x00 数据，而且数据看起来很规则。为了调试这个问题，我一次写了 192 字节 0x32 然后写了 0x33... 从 MCU 端写入和读取数据没有问题。该问题仅在从 DSP 端写入数据时出现。 FlexSPI 的配置、 const flexspi_config_t FLEXSPI_config = { .rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally, .enableSckFreeRunning = false, .enableDoze = true, .enableHalfSpeedAccess = false, .enableSckBDiffOpt = false, .enableSameConfigForAll = false, .seqTimeoutCycle = 65535, .ipGrantTimeoutCycle = 255, .txWatermark = 8U, .rxWatermark = 8U, .ahbConfig = { .ahbGrantTimeoutCycle = 255, .ahbBusTimeoutCycle = 65535, .resumeWaitCycle = 32, .buffer = { { .priority = 0, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 1, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 2, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 3, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 4, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 5, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 6, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 7, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true } }, .enableClearAHBBufferOpt = true, .enableReadAddressOpt = false, .enableAHBPrefetch = false, .enableAHBBufferable = true, .enableAHBCachable = false } }; PSRAM 的配置、 flexspi_device_config_t FLEXSPI_config_Device_SPIRAM = { .flexspiRootClk = SPIRAM_ROOT_CLOCK_HZ, .isSck2Enabled = false, .flashSize = SPIRAM_SIZE_KBYTES, .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, .CSInterval = 2, .CSHoldTime = 3, .CSSetupTime = 3, .dataValidTime = 0, .columnspace = 0U, .enableWordAddress = false, .AWRSeqIndex = SPIRAM_LUT_SEQ_IDX_WRITE, .AWRSeqNumber = 1U, .ARDSeqIndex = SPIRAM_LUT_SEQ_IDX_READ, .ARDSeqNumber = 1U, .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 1, .enableWriteMask = false, }; 有人知道这个问题吗？ i.MX RT600

SJA1110 network is not connected. Hi,nxp fellows: We are currently debugging the SJA1110 and have encountered some issues. We would like to seek assistance. We plan to connect to the network through the AG35 4G module and share the network with other devices using the SJA1110. Our custom board uses the three ports of the SJA1110. Port 1 uses the 88Q2112-A2-NYD2A000 chip to convert SGMII to T1 network ports. Port 3 is connected to the SGMII port of the AG35 4G module, and Port 4 is connected to pfe1 of S32G. We ran the SJA1110ECT_Release_1.4.0/server/rtd program on S32DS in the SJA1110, and all three ports are in SGMII mode. S32G2 runs the BPS42 Linux system. After S32G starts, it can ping SJA1110, but pinging Port 1 and Port 3 does not work. Could you help us analyze the problem and give us some suggestions? Re: SJA1110 network is not connected. hello, @PavelL  When I was using the SJA1110ECT program, I made some simple modifications to the configurations of EthTrcv_43_PHY and EthSwt_43_SJA11XX. I uploaded the screenshots of the pages. Could you please confirm if they are correct? In the S32G2 Linux system, I was able to ping 192.168.0.200 successfully, but when I checked it through arp, the displayed MAC address was different from the one in the page. It should have been fixed in the code. root@s32g274ardb2:~# ping 192.168.0.200 PING 192.168.0.200 (192.168.0.200) 56(84) bytes of data. 64 bytes from 192.168.0.200: icmp_seq=1 ttl=255 time=1.06 ms 64 bytes from 192.168.0.200: icmp_seq=2 ttl=255 time=0.907 ms ^C --- 192.168.0.200 ping statistics --- 2 packets transmitted, 2 received, 0% packet loss, time 1001ms rtt min/avg/max/mdev = 0.907/0.983/1.059/0.076 ms root@s32g274ardb2:~# arp Address HWtype HWaddress Flags Mask Iface 192.168.0.200 ether 10:11:12:66:66:66 C pfe1 I used debug and saw the value of LINK_STS in the register. Could you elaborate on how to read each port SR_MII_STS and confirm that LINK_STS = 1 (link up)? I haven't modified the MAC. Do I need to change each port to a different value? Thanks. Re: SJA1110 network is not connected. Hello @zhipeng , Since your hardware differs from the reference design, I assume you updated: the PHY list in EthTrcv_43_PHY the PHY-to-port assignments in EthSwt_43_SJA11XX For each port, please read SR_MII_STS and confirm that LINK_STS = 1 (link up). Do all endpoints use unique MAC addresses? Best regards, Pavel Re: SJA1110 network is not connected. Hello @zhipeng , SGMII setup: I assume that AG35 expects connection to PHY, so SGMII port on SJA1110 shall be in PHY_MODE. Speed 1G, Full duplex and Autoneg off are the good starting points. The displayed MAC address in ARP belongs to Eth driver (internal MAC - port 0 - connected to the internal M7), where tcpip_stack is connected.  You may use Switch_Ip_InternalRead() to read register value. No, you don't have to modified MAC addresses for each port - end nodes need to have unique MAC addresses. Best regards, Pavel Re: SJA1110 network is not connected. Hello @zhipeng , I apologize, I forgot that SGMII uses indirect addressing. It's described: - in UM11107 Software user manual for SJA1110, Rev. 3.0, chapter 8.3.11 Register access. - and also in AN12925 SJA1110 software application notes, Rev. 1, chapter 4.1.6 Register access.  Best regards, Pavel

Problem in changing fps from 30 to 60 fps for mx95mbcam with imx95 I am using imx95 with mx95mbcam camera module with gmsl maixm serdes. The default working driver is running with 1920*1280@30 fps, I wanted to run it with  1920*1280@60 fps. I made the changes in the 0x03c10 sensor register, but the maximum I was able to achieve was 47fps. After that, I was not able to get a video feed. Is there any limitation with Maxim SerDes or any other problem?

Writing Data to PSRAM from DSP on RT685 I am using the RT685 platform, connecting a PSRAM through FlexSPI. The PSRAM (ISSI IS66WVR8M8FALL) is connected to PortA2, and there is a QSPI Flash connected to PortA1. PSRAM was configured to access by AHB, FlexSPI was configured on MCU side after startup, then after a few minutes, wrote data from DSP side. When writing data from DSP side, there were some 0x00 data in the PSRAM, and the data looks regular. To debug this issue, I wrote 192 bytes 0x32 at once and then 0x33 ... There is no problem of writing and reading data from MCU side. This issue only occurred when writing data from DSP side. The configuration of FlexSPI, const flexspi_config_t FLEXSPI_config = { .rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally, .enableSckFreeRunning = false, .enableDoze = true, .enableHalfSpeedAccess = false, .enableSckBDiffOpt = false, .enableSameConfigForAll = false, .seqTimeoutCycle = 65535, .ipGrantTimeoutCycle = 255, .txWatermark = 8U, .rxWatermark = 8U, .ahbConfig = { .ahbGrantTimeoutCycle = 255, .ahbBusTimeoutCycle = 65535, .resumeWaitCycle = 32, .buffer = { { .priority = 0, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 1, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 2, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 3, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 4, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 5, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 6, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }, { .priority = 7, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true } }, .enableClearAHBBufferOpt = true, .enableReadAddressOpt = false, .enableAHBPrefetch = false, .enableAHBBufferable = true, .enableAHBCachable = false } }; Configuration of PSRAM, flexspi_device_config_t FLEXSPI_config_Device_SPIRAM = { .flexspiRootClk = SPIRAM_ROOT_CLOCK_HZ, .isSck2Enabled = false, .flashSize = SPIRAM_SIZE_KBYTES, .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, .CSInterval = 2, .CSHoldTime = 3, .CSSetupTime = 3, .dataValidTime = 0, .columnspace = 0U, .enableWordAddress = false, .AWRSeqIndex = SPIRAM_LUT_SEQ_IDX_WRITE, .AWRSeqNumber = 1U, .ARDSeqIndex = SPIRAM_LUT_SEQ_IDX_READ, .ARDSeqNumber = 1U, .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 1, .enableWriteMask = false, }; Does anyone have idea about this problem? i.MXRT 600

S32K3 Freertos问题 Hi，NXP专家： 芯片：S32K312 软件：Mcal RTD4.0.0，集成FreeRTOS 10.6.0 问题：当在BaseNXP中修改为OsifFreeRtosType类型后，会存在MCAL库里用primask，FreRTOS用basepri的冲突。freertos的移植文件没法改，mcal库也不建议改。 是否可以把BaseNXP的OsifOperatingSystemType类型改成osifbarementaltype？   Re: S32K3 Freertos问题 你好，@Chenxu1、 你在使用 FreeRTOS 软件包和示例吗？BaseNXP 操作系统被选为"OsIfFreeRtosType" 。您可以使用"FreeRTOS_Toggle_Led_Example_S32K312" 。 致以最诚挚的问候， Julián

Debug u-boot SPL on NXP imx8mm-evk Hello, How to debug u-boot SPL on i.MX8M Mini (NXP imx8mm-evk) ? Why the $pc goes to 0x200 instead of executing spl instruction ? ``` user@desktop:~/sources/u-boot$ ../binutils-gdb/gdb/gdb -q spl/u-boot-spl Reading symbols from spl/u-boot-spl... (gdb) target remote :3333 Remote debugging using :3333 0x000000000000c904 in ?? () (gdb) load Loading section .text, size 0x101c8 lma 0x7e1000 Loading section .rodata, size 0x23a3 lma 0x7f11c8 Loading section .data, size 0x5f80 lma 0x7f3570 Loading section .u_boot_list, size 0x1400 lma 0x7f94f0 Start address 0x00000000007e1000, load size 104683 Transfer rate: 69 KB/sec, 11631 bytes/write. (gdb) i r pc pc             0x7e1000            0x7e1000 <_start> (gdb) x/i 0x7e1000    0x7e1000 <_start>:    b    0x7e1028 (gdb) stepi 0x0000000000000200 in ?? () (gdb) i r pc pc             0x200               0x200 (gdb) x/i 0x200 => 0x200:    b    0x13dc4 ``` BOOT_MODE[3:0] = 0101 (serial downloader) openocd 0.10.0 (openocd -f ./tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg -f ./tcl/board/imx8mp-evk.cfg) GNU gdb (GDB) 10.0.50.20200418-git Best regards i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Debug u-boot SPL on NXP imx8mm-evk Hi Yuri, I have the same issue. Could you share some material with me. Thanks a lot. Re: Debug u-boot SPL on NXP imx8mm-evk Everyone has the same problem. Who has the solution Re: Debug u-boot SPL on NXP imx8mm-evk Everyone has the same problem. Who has the solution Re: Debug u-boot SPL on NXP imx8mm-evk @joaze  Hello,    Last time I sent some material how to debug the issue. I do not know  exact solution. You can create separate thread for considerations. Regards, Yuri Re: Debug u-boot SPL on NXP imx8mm-evk Hi Yuri! I have similar problems on a imx8mn-evk board when I try to load the SPL. What was the solution to the https://community.nxp.com/t5/i-MX-Processors/Debug-u-boot-SPL-on-NXP-imx8mm-evk/m-p/1079629 question. Re: Debug u-boot SPL on NXP imx8mm-evk Yuri, Do you have a solution for the problem? Re: Debug u-boot SPL on NXP imx8mm-evk We got same issue. Could you pls email info to us.  Thanks Re: Debug u-boot SPL on NXP imx8mm-evk Hello,   I've sent You some comments. Regards, Yuri.

TJA1055/3 FT CANバス 私はしばらくの間、ESP32-P4とtwaiをフォールトトレラントCANバスシステムにインターフェースするのに苦労してきました。TJA1055/3はブレッドボード上にあり、接続されています。チップからのRx出力を測定できます。これはESPGPIOに送信されるはずですが、この電圧出力はHIで約3.2V、LOで約1.8Vにしか達しないようです。ESP32 GPIOはLOで0.8Vを必要とするため、これらのパルスをデコードして受信データを読み取ることができません。TJA1055のRx出力に様々なサイズのプルアップ抵抗を試してみましたが、ほとんど変化はありませんでした。また、ピン8と9の間、およびCAN HとCAN L信号の間の終端抵抗を変更してみましたが、多少の変化はありましたが、十分ではありませんでした。チップから使用可能な信号を取得する方法について、どなたかご教示いただけないでしょうか？それとも、TJA1055とESP GPIOの間に追加の信号調整回路を設ける必要があるのでしょうか？

LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform – is a dedicated image/kernel configuration required? Hi NXP team, I’m using LA1224-RDB-BHS with FR1/FR2 Test Tool v5.1 and VSPA images in this tool（e.g., MEvspa_images_HS.2T2R_400M_120K_1966_1966_TDDFDD） to validate FR2 single-carrier (SC) waveform transmission in Option8 time-domain mode. I’m using SMA cables with the LA1224-FR2-BRK to loop back the TX to RX on a single LA1224-RDB-BHS device. Steps I performed: 1. Generate a 10 ms complex IQ waveform at 491.52 Msps (int16 IQ interleaved), file size 19,660,800 bytes. 2. Load it via: ./boot_vspa.sh MEvspa_images_HS.2T2R_400M_120K_1966_1966_TDDFDD ./channels_start.sh 4 ./set_dfe_state.sh 4 normal ./update_test_vector.sh my_waveform_10ms.bin ./dump_time_domain_tx.sh 4 ./dump_time_domain_rx.sh 4 Dumps obtained: - TX dump: tx_timedomain_20ms_1966080ksps_dump_ant4.bin (Fs=1.96608 Gsps) - RX dump: rx_timedomain_20ms_983040ksps_dump_ant4.bin (Fs=983.04 Msps) I performed MATLAB correlation-based alignment and best-window comparison. Observations: - Correlation peak scores are very high (e.g., ~0.998), so the injected waveform is definitely being transmitted and received. - However, the measured EVM between my reference waveform (A) and TX dump (B) is not negligible: - For PN/BPSK + RRC test waveform: A→B EVM ≈ 6.75% (NMSE ≈ -23.4 dB) - For another SC waveform: A→B EVM ≈ 22.8% - Disabling some kernels does not change EVM significantly: ./kernels_disable_tx.sh 4 qec cfr dpd ./update_fine_cfo_nco_freq.sh 4 0 (EVM/NMSE nearly unchanged) Questions: 1. For single-carrier FR2 validation, is the provided VSPA image (with OFDM SCS-based naming) still appropriate, or is there a dedicated single-carrier optimized image? 2. In Option8 time-domain injection, are upsampling/downsampling/CFO/QEC kernels always in the processing chain? Is there a supported way to bypass them (or guarantee “transparent pass-through”) for SC waveform testing? 3. What is the expected EVM floor between (A) injected waveform and (B) TX dump in this setup? Is ~6–7% reasonable due to fixed-point/filtering, or does it indicate a misconfiguration? I can provide exact scripts, config, and waveforms if needed. Thanks! Re: LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform LA1224 support is not public. If you need assistance, please create a case at the link below and attach your NDA: https://support.nxp.com/s/?language=en_US Thanks. Re: LA1224 FR1/FR2 Test Tool (v5.1): Using Option8 time-domain injection for single-carrier waveform Hello! If you replace the file generated in the time domain with Fs 491.52 MHz, will the DUC x4 work up to 1966.08 MHz on the VSPA? I believe you need to generate a time domain signal with the same Fs frequency as the DAC, i.e., 1966.08 MHz.

MCXN527 USB ISP Hello, i am new to the MCX Controllers, and i can not establish an USB connection. I use a MCXN527VKLT Controller, and I have connected: -USB0-DM and -DP -VDD_USB (over a 3.3V regulator) -VSS_USB -USB0_VBUS_DET to 5V from USB My expectations are that when I pull ISPMODE_N pin to GND via a switch, then plug in USB in my computer, open the ISPMODE_N switch, the controller should be seen as an HID? I also tried testing the connection with the secure provisioning tool. What am I missing? Thanks in advance and sorry for this beginner question. Steve MCXN Re: MCXN527 USB ISP Hi @BuS  Thank you for your post, Could you confirm your external crystal oscillator value?  The UG10092: MCX N Series Hardware Design Guide | NXP Semiconductors has a note that is relevant in the case of ISP over USB: If using the HS USB in In-system programming (ISP) mode, a 24 MHz crystal must be used in at least the first access of the device. However, the user can modify the security fuse configuration to allow a different crystal. However, the user must configure it. For example, factory configuration requires a 24 MHz crystal for HS USB ISP operation. BR Re: MCXN527 USB ISP Hi, there is a 24MHz crystal attached to pin P1_30 and P1_31. Steve Re: MCXN527 USB ISP Hi @BuS  thank you for clarifying! Please review the VDD_CORE voltage. USB HS is not supported when VDD_CORE < 1.1 V Also review that your system follows the 2.5 Required Power-On-Reset (POR) Sequencing described at Highly integrated low-power dual-core Arm Cortex M33 MCU with on-chip accelerators Could you confirm if you were able to use your custom board before? 

在恩智浦上调试 u-boot SPL imx8mm-evk <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 你好 如何在 i.mx8M Mini（恩智浦 imx8mm-evk）上调试 u-boot SPL？ 为什么没有执行 spl 指令，而是将 $pc 设为 0x200？ ``` 用户 @desktop：~/sources/u-boot$../binutils-gdb/gdb/gdb-q spl/u-boot-spl 正在读取 spl/u-boot-spl 中的符号... (gdb) 目标远程：3333 在？？中使用:3333 0x00000000000000c90 4 进行远程调试 () (gdb) 加载加载部分 .text，size 0x101c8 lma 0x7e1000 正在加载 .rodata 部分、size 0x23a3 lma 0x7f11c8 正在加载 .data、size 0x5f80 lma 0x7f3570 正在加载 .u_boot_list 部分、大小 0x1400 lma 0x7f94f0 起始地址 0x00000000007e1000，负载大小 104683 传输速率：69 KB/秒，11631 字节/写入。 (gdb) i r pc pc 0x7e1000 0x7e1000<_start> (gdb) x/i 0x7e1000 0x7e1000<_start>: b 0x7e1028 (gdb) stepi 0x0000000000000200 in ?? () (gdb) i r pc pc 0x200 0x200 (gdb) x/i 0x200 => 0x200: b 0x13dc4 ``` BOOT_MODE[3:0]=0101（串行下载器） openocd 0.10.0 (openocd-f./tcl/interface/ftdi/olimex-Arm-usb-ocd-h.cfg-f。/tcl/板/imx8mp-evk.cfg) GNU gdb (GDB) 10.0.50.20200418-git 顺祝商祺！ i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Debug u-boot SPL on NXP imx8mm-evk 嗨，尤里，我也遇到了同样的问题。能否与我分享一些资料？非常感谢。 Re: Debug u-boot SPL on NXP imx8mm-evk 每个人都有同样的问题。谁有解决方案 Re: Debug u-boot SPL on NXP imx8mm-evk 每个人都有同样的问题。谁有解决方案 Re: Debug u-boot SPL on NXP imx8mm-evk @joaze 你好、 上次我发送了一些如何调试问题的材料。我不知道 精确的解决方案。您可以创建单独的线程来考虑这些问题。 致 Yuri Re: Debug u-boot SPL on NXP imx8mm-evk 你好，尤里！ 当我尝试加载 SPL 时，我在 imx8mn-evk 主板上遇到了类似的问题。 https://community.nxp.com/t5/i-MX-Processors/Debug-u-boot-SPL-on-NXP-imx8mm-evk/m-p/1079629的解决方案是什么？ 问题 Re: Debug u-boot SPL on NXP imx8mm-evk Yuri, 你有解决问题的办法吗？ Re: Debug u-boot SPL on NXP imx8mm-evk 我们遇到了同样的问题。请将信息通过电子邮件发送给我们。 谢谢！ Re: Debug u-boot SPL on NXP imx8mm-evk <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 你好 我给您发了一些评论。 此致， 尤里。

MCCXN527 USB IP 你好 我是 MCX 控制器的新手，无法建立 USB 连接。 我使用 MCXN527VKLT 控制器，并已连接： -USB0-DM 和 -DP -VDD_USB（通过 3.3V 稳压器） -VSS_USB -将 USB0_VBUS_DET 转换为 5V 电压 我的期望是，当我通过开关将 ISPMODE_N 引脚拉至 GND，然后在电脑上插入 USB，打开 ISPMODE_N 开关时，控制器是否应被视为 HID？ 我还尝试使用安全配置工具测试连接。 我错过了什么？ 在此先表示感谢，并对这个初学者问题表示歉意。 史蒂夫 MCX N Re: MCXN527 USB ISP 你好@BuS 感谢您的来信、 你能确认一下你的外部晶振（晶体振荡器）的值吗？ UG10092：MCX N系列硬件设计指南|恩智浦半导体有一条与USB上的ISP相关的注意事项：如果在系统内编程 (ISP) 模式下使用HS USB，则至少在首次访问设备时必须使用24 MHz晶体。但是，用户可以修改安全熔丝配置以允许使用不同的晶体。不过，用户必须对其进行配置。例如，出厂配置要求使用 24 MHz 晶体进行 HS USB ISP 操作。 BR Re: MCXN527 USB ISP 您好， P1_30 和 P1_31 引脚连接有一个 24MHz 晶振。 史蒂夫 Re: MCXN527 USB ISP 你好@BuS 谢谢您的澄清！ 请检查 VDD_CORE 电压。 当 VDD_CORE< 1.1 V 时，不支持 USB HS。 另请检查您的系统是否遵循带有片 上加速器 的高度集成的低功耗双核 Arm Cortex M33 MCU 中所述的 2.5 次上电复位 (POR) 顺序 你能确认一下你以前是否能够使用你的自定义板吗？

S32K3 Freertos problem Hi, NXP Expert: Chip: S32K312 Software: Mcal RTD 4.0.0, integrated FreeRTOS 10.6.0 Problem: Whenchanging toOsifFreeRtosTypetypeinBaseNXP, there is a conflict between using primask in MCAL library and basepri in FreRTOS. freertos porting file can't be changed, and mcal library doesn't recommend to change it. Is it possible to change the OsifOperatingSystemType type of BaseNXP to osifbarementaltype?   Re: S32K3 Freertos问题 Hello @Chenxu1, Are you using the FreeRTOS package and examples? The BaseNXP OS is selected as "OsIfFreeRtosType". You can use "FreeRTOS_Toggle_Led_Example_S32K312". Best regards, Julián

stack pushing and popping for JN5169 exception processing Hi Customer met an exception, wanted to analyze the stack content, but cannot find the document for the RISC core of JN5169 ， so do not know the sequence to push core registers.  who can help to provide the sequence to push register  for exception processing?  Customer wants to find the document to describe this.  Thanks! Derek   Priority: Normal - Important but not Urgent Product JN5189 Region: APAC Topic: SW Tools (IDE | SDK | MCUXpresso Tool) Type: Documentation Re: stack pushing and popping for JN5169 exception processing @hiwave can you let us know the customer name related to this case? @amigo_li can you help here?

用于 FRDM-A-S32K344 的闪光工具 我使用的是 FRDM-A-S32K344 mini-EVK 主板并成功使用 S32 Design Studio IDE 刷新了代码；现在我想知道是否有任何 GUI 工具可以刷新 .hex在不使用集成开发环境的情况下，回读已闪存的 .hex 文件。锉刀 Re: Flashing Tool for FRDM-A-S32K344 Hi@ganavi1 对于 FRDM-A-S32K344，除非使用第三方调试器及其相应软件，否则不支持使用。 Re: Flashing Tool for FRDM-A-S32K344 我在 FRDM-A-S32K344 主板上使用内置的 OpenSDA 调试器。我没有使用 J-Link 进行闪光。有没有办法在不使用 S32 设计工作室 IDE 的情况下刷新主板？ Re: Flashing Tool for FRDM-A-S32K344 Hi@ganavi1 赛格 J-Flash 可用于下载十六进制文件或从 MCU 读回数据。 https://www.segger.com/products/debug-probes/j-link/tools/j-flash/about-j-flash/ Re: Flashing Tool for FRDM-A-S32K344 有没有办法在 S32 IDE 工具的调试模式下读取闪存，以验证闪存中存储的是哪些数据？ Re: Flashing Tool for FRDM-A-S32K344 感谢您的答复。是否有任何方法可以使用 S32 IDE 擦除存储在用户空间的数据，就像芯片擦除一样？ Re: Flashing Tool for FRDM-A-S32K344 Hi@ganavi1 我还没有在 S32 DS 中看到过这种功能。

PMSMのV/f制御は可能ですか？ 私はV/f方法によるPMSM制御のためのSimulinkモデルを作成しています。このモデルは誘導電動機には有効ですが、PMSMの速度出力が振動します。磁界が同期していないのだと思います。何か見落としているでしょうか？ Re: can we do V/f control of a PMSM? こんにちは、 PMSMのV/f = 可能 しかし多くの条件下で本質的に不安定である 観測された振動は想定される挙動です 本格的なPMSMプロジェクトの場合： FOC（ベクトル制御）を使用する あるいは少なくともセンサーレスFOC V/f は: 研究/デモ用としては問題ない 生産用PMSM制御には不適切 V/f制御下のPMSMに関する問題点の概要 自己同期機能なし： PMSMはローターの磁界が固定されているため、固定子の磁界と同期を保つ必要がある。V/f制御ではこれは保証されません。 滑り機構なし（誘導モーターとは異なります）： 速度とトルクを一致させるための自然な「調整」機能がないため、不安定性が発生する可能性がある。 制御されていないトルク角度（δ）： トルクはローター磁界と固定子磁界の間の角度に依存するが、V/fはこの角度を制御しないため、トルクが不安定になる。 結果: 速度変動 同期の喪失（ステップアウト）の可能性 動的性能が低い よろしくお願いいたします。 ピーター

The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. @danielmartynek Hello, when I was using the LPUART1 of S32K314 as the LIN slave to communicate, I found that initially the slave could respond normally to the frame headers sent by the host, but after a period of time, the slave could no longer respond to the frame headers sent by the host. Moreover, when receiving data, starting from the second interrupt, it could no longer stay at my data receiving breakpoint. As shown in the figure below, I use the callback function to handle the responses and receptions of the slave machine. When using the debugging monitoring function, I found that the first time entering the interrupt could detect the status of the synchronization interval segment and enter the function for processing the synchronization interval segment. However, when entering the interrupt again, it would go into the (void)Lpuart_Lin_Ip_HwClearStatusFlag(Base, LPUART_LIN_IP_ALL_INT_FLAGS); routine. When the function re-enters the interrupt, it will detect LPUART_LIN_IP_FRAME_ERR && LPUART_LIN_IP_INT_FRAME_ERR_FLAG and perform error handling. Only after this handling is completed will it enter my callback function for execution. I set breakpoints in the Lpuart_Lin_Ip_FrameIrqHandler function at LPUART_LIN_IP_NODE_STATE_RECV_SYNC and LPUART_LIN_IP_NODE_STATE_RECV_PID respectively, but there was no execution to this point. I wonder what kind of problem might cause this. I am looking forward to your reply, as it is very important to me. Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. Hello, based on your request, I set a breakpoint at the Lpuart_Lin_Ip_FrameErrorIrqHandler location for monitoring. I found that during the running process, my LIN would switch back and forth between this code and my receiving callback function, and my buffer was able to receive data. There was no specific error reason in the Lpuart_Lin_Ip_FrameErrorIrqHandler function. Currently, what I can confirm is that this function Lpuart_Lin_Ip_FrameErrorIrqHandler is frequently called during the running process, but my receiving response buffer is still able to receive data. After a period of running, this function Lpuart_Lin_Ip_FrameErrorIrqHandler and my callback function will no longer enter the loop. I can interpret this as a communication interruption. How can I find out where the problem lies? Do I need to check any registers? Oh, by the way, the first picture shows that after learning about the error of not clearing the overflow register flag in the RTD2.0.0 version, I manually cleared it in the box. Am I understanding this correctly? This indeed solved the problem that I couldn't enter the callback function after running several times, but the communication still got disconnected afterwards. My description might be a bit complicated, but I'm looking forward to your help. I would be extremely grateful. Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. Hi @Aoyng, When you place a breakpoint in the RECV_SYNC case, the LIN master continues transmitting and does not wait for the slave. As a result, the PID field and the rest of the frame are sent while the CPU is halted, so they are not processed correctly by the driver. This likely causes the desynchronization and leads to the “spurious” interrupt you are observing. Instead, I recommend placing breakpoints in the error handling path, for example in Lpuart_Lin_Ip_FrameErrorIrqHandler(). These handlers are triggered by actual protocol or bus errors. Once you identify the initial LPUART error, we can analyze the issue further. BR, Daniel Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. Could you please tell me if there are any hidden bugs in my aforementioned code? Thank you very much for checking if there are any issues with my code logic. Since I haven't encountered the situation of LIN communication interruption before, I would greatly appreciate it if you could help me analyze it. Thank you! Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. It seems the message for LPUART_LIN_IP_FRAME_ERR && LPUART_LIN_IP_INT_FRAME_ERR_FLAG have blocked your LIN communication. Have you check from HARDWARE side? How about your LIN communication loop from structure point of view Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. Hello @Aoyng, If Lpuart_Lin_Ip_FrameErrorIrqHandler() is called, it indicates that a real framing error has been detected. Please verify both baud rates using an oscilloscope. Refer to the Reference Manual, section 77.3.2 Baud rate tolerance. The overrun occurs because the application is not able to read the received data in time. This may happen if a higher-priority interrupt preempts the LIN interrupt. You may try increasing the priority of the LPUART interrupt or temporarily disabling competing interrupts to confirm this behavior. Regarding your previous comment, it is not entirely clear: Do you mean that the overrun interrupt is not being processed in Lpuart_Lin_Ip_RxOverrunErrorProcess()? Can you confirm whether execution reaches this function? This function is responsible for clearing the overrun (OR) flag. Based on the current information, there is no indication that the driver itself needs to be modified. Regards, Daniel Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. Hello, currently my LIN interrupt priority is set to 0. I believe the priority has reached the highest level. The situation I mentioned about being unable to clear the overflow flag was seen in a post by a person named dongxun. The post is about a bug in the RTD 2.0.0 library: LIN: S32K312 MCU as a Master, Lin Timeout Error while waiting for LinID. And after clearing the received overflow in the interrupt, I did not encounter the situation where the program got stuck at the receiving part after running for the second time. It only ran for a while and then disconnected. Regarding the baud rate issue you mentioned, I set both the master and slave sides to a baud rate of 19200. I am certain of this because if it were a baud rate issue, I believe the communication would not have started in the first place. Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. What you are seeing is actually expected behavior in this setup. When you increased the LIN interrupt priority and lowered the PIT priority, you ensured that the LIN ISR is serviced in time, which is critical for correct operation. Each received byte must be read from the DATA register before the next byte arrives. If the CPU does not service the RX interrupt fast enough, the hardware sets the overrun (OR) flag. If the PIT interrupt is able to preempt the LIN interrupt, then the PIT interrupt service routine must be very short. Otherwise, it can delay the LIN ISR long enough to miss incoming data. Regards, Daniel Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. Hi @Aoyng, You’re correct—there is a bug in the LIN driver: the overrun interrupt is not enabled by default. Have you tried enabling this interrupt after initializing the LIN driver? The logic to clear the flag is already implemented. it’s always a good practice to verify baud rates using an oscilloscope to ensure proper timing. BR, Daniel Re: The S32K314 uses the LPUART to configure as a LIN slave communication interrupt. Hello, I was attempting to set the LIN interrupt priority to the highest level and the PIT priority to a lower level. After doing so, I found that the communication could run normally without any interruption. Could you please explain why there is a communication disconnection issue with LIN? Currently, I am using the LIN transceiver with the FS6500 chip. From my understanding, if there is an interrupt conflict, shouldn't there be a frame loss problem? Can you provide an answer? Looking forward to your reply.

周期的な測定中にMC33774Aのバランス調整を一時停止する こんにちは。MC33774Aに問題が発生しました。バルポーズを使用して周期的な測定を有効にします（MC33774_ALLM_CFG_OFFSETに3を書き込みます）。偶数セルのバランスをとっている場合にのみ、この方法が機能するようです。奇数セルでバランス調整が有効になっている場合、それらのセルの周期的な測定値がずれます。予想より少ないこともあれば、多いこともある。何が問題なのでしょうか？ あるいは、MC33774Aを周期モード（スリープ、測定、スリープを繰り返すモード）に設定するにはどうすればよいでしょうか？ SYS_CYC_WAKEUP_CFGに2を書き込んでからSYS_MODEに10を書き込んでも、デバイスはディープスリープ状態になります。

RT1189 with TSN Hi there, I am trying to build a project with RT1189/RT1186.The goal is to receive data from a netc port and send it through another netc port with tsn. Is there any tsn examples inside sdk to refer to? Thank you. Board Design Development Board Re: RT1189 with TSN Hi Gavin, Thank you so much for replying. I will definitely go looking to those examples you suggest. Best regards. Re: RT1189 with TSN Hi @alex_l1 , Thanks for your interest in NXP MIMXRT sereis!  For RT1189, there are NETC examples available in the MCUXpresso SDK. If your requirement is to receive frames from one NETC port and forward them to another NETC port, the closest SDK example is:   driver_examples/netc/switch   This example demonstrates how to configure NETC as a network switch.   You may also refer to:   driver_examples/netc/txrx_transfer   driver_examples/netc/psi_vsi_message   Please note that these examples are NETC driver-level examples. They are useful for NETC port TX/RX and switch forwarding, but they are not a full TSN protocol stack demo.   If you need actual TSN protocol features, such as gPTP, AVB/TSN endpoint, TSN bridge, stream reservation, or scheduled traffic, please refer to the NXP GenAVB/TSN middleware with detailed guides in RT1180 page:   https://www.nxp.com/products/i.MX-RT1180   Hope that helps!   Best regards, Gavin   Best regards,