VRC_CTRL Clarification Hello NXP Support, I would like to ask some questions on S32K3's VRC_CTRL (PTE13). (1) RM mentions VRC_CTRL is direct signal, could you please check the understanding/question in the following table (red font)? ALTx OBE IBE VRC_CTRL Question GPIO Disabled Disabled Enabled VRC_CTRL will take effect, right? GPIO Disabled Enabled Enabled VRC_CTRL will still take effect, right? GPIO Enabled Not Care Enabled Who will take effect? (2) If we configure PTE13 as GPIO + OBE Enabled + Output Level Low, will the VRC_CTRL negative feedback mechanism be broken because VRC_CTRL is treated as error signal and now maybe GPIO and VRC_CTRL are driving the pin at the same time? (3) In NXP MCAL, as long as I configure PTE13 as PG_VRC_CTRL_OUT, OBE will be automatically set by function Port_Ipw_SetOnlyOutputMode(), is it an issue of MCAL? (4) How to test VRC_CTRL feedback mechanism , what waveform is expected during which condition? (5) Why is MSCR141 documented as "Not Supported" in RM? Thanks. BR Re: VRC_CTRL Clarification Hello Pavel, Thanks a lot for your detailed answer. VRC_CTRL should not be configured or forced as a GPIO output while it is used by the last-mile regulator. In particular, setting a GPIO output level to Low is not the correct way to disable or control the regulator. What will happen if VRC_CTRL is enabled and OBE is also enabled at the same time? Maybe a intermediate level will be present on PTE13? Where can I find some diagram to describe the combined driving path from both direct signal and SIUL2 output-multiplexing? The following is my measurement. You can see when VRC_CTRL is enable, GPIO output can have some impact to the PTE13. For validation, V15 and VRC_CTRL should be measured together during startup and under load changes. How to trigger the load change, is it by switching the frequency of the core? MSCR141 is documented as “Not Supported” because PTE13/VRC_CTRL uses a direct connection from the PMC rather than the normal SIUL2 output-multiplexing path. Therefore, MSCR141 must not be used to control the VRC_CTRL function. I didn't quite understand here, at least GPIO141 can be used when VRC_CTRL is disabled, why does RM just mention MSCR141 is not supported? Actually I can access MSCR141 from debugger, and I can switch the settings there. Regarding Port_Ipw_SetOnlyOutputMode(), the fact that this function is called does not by itself prove that the PMC regulator is affected. Sorry, I didn't get your point here. Actually this is the main reason I asked this question, following code will be generated when I configure PTE13 PinMode as PG_VRC_CTRL_OUT in MCAL Port module. #define SIUL2_0_PORT141_PG_VRC_CTRL_OUT (PORT_ONLY_OUTPUT_MODE)
Port_Ipw_SetOnlyOutputMode() will be called and “OBE” bit will set in this function. I think it maybe a MCAL bug, PG_VRC_CTRL_OUT mode enables OBE by mistake. Could you please help to check? Do you think that configuring it to GPIO + PORT_PIN_HIGH_Z + PORT_PIN_LEVEL_NOTCHANGE can be a workaround, in this case, MSCR141 of PTE13 can be guaranteed to be 0 (OBE = 0)? Best regards Kumamon Re: VRC_CTRL Clarification Hello @kumamon ,
I think the main misunderstanding is that VRC_CTRL is being treated as a regular SIUL2/GPIO output.
VRC_CTRL is a direct output of the PMC last-mile regulator. When the external ballast-transistor supply option is used, the PMC monitors the V15 domain and adjusts VRC_CTRL, which is connected to the base of the external NPN transistor. This forms a closed analog feedback loop. Therefore, VRC_CTRL is not controlled through the normal GPIO output data registers.
For this reason, the GPIO ALTx, IBE and OBE combinations in the table are not applicable to the VRC_CTRL function:
IBE only controls the digital input buffer and has no role in the V15 regulator feedback loop.
VRC_CTRL should not be configured or forced as a GPIO output while it is used by the last-mile regulator. In particular, setting a GPIO output level to Low is not the correct way to disable or control the regulator.
The last-mile regulator is controlled by the PMC, including the PMC_CONFIG[LMBCTLEN] field and the initialization sequence documented in the device-specific PMC chapter.
VRC_CTRL is an analog control signal rather than a digital status output. Consequently, there is no single fixed waveform that applies to all designs. Its voltage depends on the external transistor, V15 load, supply voltage, external capacitance and operating mode. For validation, V15 and VRC_CTRL should be measured together during startup and under load changes. The expected result is that V15 remains within its specified operating range while VRC_CTRL adjusts the external transistor as required.
MSCR141 is documented as “Not Supported” because PTE13/VRC_CTRL uses a direct connection from the PMC rather than the normal SIUL2 output-multiplexing path. Therefore, MSCR141 must not be used to control the VRC_CTRL function.
Regarding Port_Ipw_SetOnlyOutputMode(), the fact that this function is called does not by itself prove that the PMC regulator is affected.
Please also note that the reset behavior is derivative-specific. For example, the S32K3x8 (and S32K356) PMC has a device-specific CONFIG reset value of 0x00000083, so the last-mile regulator configuration is enabled after reset. This must not be generalized from older S32K3 derivatives where LMBCTLEN may need to be enabled explicitly.
Best regards,
Pavel Re: VRC_CTRL Clarification Hello Pavel, Thanks for the answer. The generic Port driver enables OBE when an output mode is requested. Do you know which setting other than PG_VRC_CTRL_OUT in the following figure introduces the "output mode"? Sorry, but I still feel MCAL Port maps the PG_VRC_CTRL_OUT to output mode by mistake. For validation, V15 and VRC_CTRL should be measured together during startup and under load changes. How to trigger the load change, is it by switching the frequency of the core? Thanks. BR/Kumamon Re: VRC_CTRL Clarification Hello @kumamon ,
Thank you for the measurements. They confirm that setting MSCR141[OBE] = 1 enables the digital output driver and allows the GPIO level to influence the VRC_CTRL node. Enabling the GPIO output driver while the PMC last-mile regulator is active is not a supported configuration and can disturb V15 regulation.
This does not necessarily indicate an MCAL driver defect. PTE13/VRC_CTRL is a special-purpose pin that requires application-specific handling. The generic Port driver enables OBE when an output mode is requested, but it cannot determine whether the PMC regulator and the external ballast-transistor circuit are being used.
Your proposed workaround is appropriate, provided that the resulting configuration leaves MSCR141[OBE] = 0:
Use PORT_PIN_HIGH_Z.
Use PORT_PIN_LEVEL_NOTCHANGED.
Verify MSCR141[OBE] after Port_Init().
Do not subsequently configure PTE13 as a digital output while VRC_CTRL is active.
The essential requirement is to keep the digital output buffer disabled.
Best regards,
Pavel Re: VRC_CTRL Clarification Hello Pavel, Thanks. The configuration shown in your screenshot appears to be correct. But the question is that the generated code will enable OBE bit, which is not expected. changing the CPU workload while keeping the clock configuration unchanged is generally easier to interpret than changing the core frequency. Could you please explain a bit on how to change CPU workload? Thanks. BR/Kumamon. Re: VRC_CTRL Clarification Hello Pavel, Thanks. Please note that MSCR141 is documented as not supported for this special-purpose direct signal. According to the following diagram, PTE13 is not necessarily VRC_CTRL, it can be any of other functions. I feel It is conflicting to the statement "MSCR141 is not supported". Could you please provide the exact MCAL/RTD version and the relevant generated configuration and initialization code that sets OBE? Also provide exact version of used S32K3 MCU. RTD Version: Configuration: Generated: Note: Sorry, I made a mistake in previous discussion. OBE is not set by Port_Ipw_SetOnlyOutputMode(), it shall be set in Siul2_Port_Ip_PinInit(). MCU: S32K322 Thanks. BR/Kumamon Re: VRC_CTRL Clarification Hello @kumamon ,
The configuration shown in your screenshot appears to be correct.
Regarding the load-change measurement, this was only an optional suggestion for evaluating the regulator response. It is not required to verify the VRC_CTRL configuration. If such a test is desired, changing the CPU workload while keeping the clock configuration unchanged is generally easier to interpret than changing the core frequency.
Best regards,
Pavel Re: VRC_CTRL Clarification Hello @kumamon ,
I now understand your concern. Your configuration selects:
Pin Direction = PORT_PIN_HIGH_Z
Pin Level Value = PORT_PIN_LEVEL_NOTCHANGED
Pin Mode = PG_VRC_CTRL_OUT
Therefore, the digital output buffer is not expected to be enabled. If the generated code nevertheless sets OBE = 1, this behavior should be investigated in the MCAL Port configuration.
Please note that MSCR141 is documented as not supported for this special-purpose direct signal. PTE13/VRC_CTRL is controlled by the PMC and should not require a normal SIUL2 output-buffer configuration. Accessing or modifying MSCR141 manually is therefore not a supported application method.
Could you please provide the exact MCAL/RTD version and the relevant generated configuration and initialization code that sets OBE? Also provide exact version of used S32K3 MCU.
Regarding the CPU workload, this was only an optional suggestion for observing the regulator response and is not required to verify the VRC_CTRL configuration.
Best regards,
Pavel Re: VRC_CTRL Clarification Hello Pavel, Thanks a lot for detailed explanation. The best way seems to be excluding PTE13 from MCAL port configuration completely. Our use-case is a little special: - In bootloader, most of the pins are configured as input (IBE = 1). // and we do not want to change bootloader now. - in application, in order to make PTE13 perfectly untouched, I configure it to GPIO + HIGH_Z, so IBE can be cleared then. Question (Please forgive my verbosity): - According to previous discussion, "IBE = 1" will not impact VRC_CTRL function, right? I can keep IBE = 1? - If I configure PTE13 to GPIO + HIGH_Z to achieve perfect untouched state in application, it is also OK, right? Thanks BR/Kumamon Re: VRC_CTRL Clarification Hello @kumamon ,
I performed a detailed investigation. Here are the results:
The Port configuration data and the resulting behavior are consistent between S32K3 RTD 4.0.0 and RTD 7.0.1.
S32K3 Reference Manual: The statement that MSCR141 is not supported requires a clearer device-specific explanation. MSCR141 is not supported on S32K388 and S32K389, where PTE13 and the VRC_CTRL pin function are not defined.
Configuration when PTE13 is used as VRC_CTRL: If PTE13 is used as the VRC_CTRL output of the PMC last-mile regulator, the pin does not need to be configured in the MCAL Port module.
Configuration when PTE13 is used as GPIO or another peripheral function: In this case, the PMC VRC_CTRL function must not be active. This is particularly important for derivatives where the last-mile regulator is enabled after reset. The application must first configure the PMC supply appropriately before assigning PTE13 to a regular SIUL2 function.
The two use cases should therefore be treated as mutually exclusive:
VRC_CTRL use:
Configure the PMC last-mile regulator.
Leave PTE13 untouched by the MCAL Port module.
GPIO or peripheral use:
Disable or do not use the PMC last-mile regulator.
Configure PTE13 through the MCAL Port module.
Your measurements are consistent with this distinction. If the PMC VRC_CTRL function and the SIUL2 digital output buffer are active at the same time, the digital output path can influence the VRC_CTRL node and disturb the V15 regulation. This simultaneous configuration should therefore be avoided.
Best regards,
Pavel Re: VRC_CTRL Clarification Hello @kumamon ,
Thank you for clarifying your use case.
Yes, IBE = 1 can remain enabled.
Yes, you can configure PTE13 to GPIO + HIGH_Z.
Just do not select PG_VRC_CTRL_OUT in the MCAL Port configuration. RTD classifies this mode as PORT_ONLY_OUTPUT_MODE, independently of the selected PortPinDirection and consequently enables the output buffer. Selecting PORT_PIN_HIGH_Z does not override this behavior for PG_VRC_CTRL_OUT.
Best regards,
Pavel Re: VRC_CTRL Clarification Hello @Pavel, Thank you for your effective, and detailed support. It is clear to me now, I will close this ticket. BR/Kumanon
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