Errata ERR053404: Use Cases for Different Message Buffer Configurations This article discusses the different use cases and configuration of the errata "ERR053404: FlexCAN: Message Buffer (MB) and Enhanced RX FIFO Filter Element (ERFFEL) Memory Corruption". The errata is impacting Messabe Buffers (MB) and Enhanced RX FIFO Filter Elements (ERFFEL), the impact of each MB or ERFFEL depends on the configuration of the payload buffer, MB and/or ERFFEL. In this post, we plan to provide some examples of such configuration and impact on the FlexCAN IP.  Taking a 64-byte payload as an example, the following configurations illustrate the trade-off between the number of Message Buffers (MBs) and acceptance filters: /* ERR053404: This errata explains affected words depends on MB payload size, this example applies for MB configured for 64-byte payload */ #define BYTES_IN_MB kFLEXCAN_64BperMB FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); 1. MB0 is not used, MB1 is used. In this configuration, ERFFEL[0–29] can be fully utilized as acceptance filters, while MB1–MB6 are available as Message Buffers, maximum ERFCR[NFE] is 14. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x140. Used ERFFEL[0–29], ERFCR[NFE]=14 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; flexcan_rx_mb_config_t mbConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; /* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */ FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0)); #define RX_MESSAGE_BUFFER_1 (1U) /* Setup Rx Message Buffer 1. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x121U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true); 2. MB0 and MB1 are not used. In this case, ERFFEL[0–31] are available for acceptance filtering, and MB2–MB6 are reserved as Message Buffers, maximum ERFCR[NFE] is 15. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x142. Used ERFFEL[0–31], ERFCR[NFE]=15 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x130, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x131, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x132, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x133, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x134, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x135, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x136, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x137, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x138, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x139, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13E, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x13F, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x140, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x141, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x142, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; 3. MB0 and MB1 are both used. Under this configuration, only ERFFEL[0–11] can be used as acceptance filters. ERFFEL[12–31] are not available, while MB0–MB6 can be used as Message Buffers, maximum ERFCR[NFE] is 5. The following code can be used as reference for the driver configuration for this case.  /* Config fifo filters to make it accept STD frame with ID 0x123 ~ 0x12E. Used ERFFEL[0–11], ERFCR[NFE]=5 */ uint32_t rxEnFifoFilter[] = {FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x123, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x124, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x125, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x126, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x127, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x128, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x129, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12A, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12B, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12C, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12D, 0, 0x3F, 0), FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(0x12E, 0, 0x3F, 0)}; flexcan_enhanced_rx_fifo_config_t rxEhFifoConfig; flexcan_rx_mb_config_t mbConfig; /* Setup Enhanced Rx FIFO. */ rxEhFifoConfig.idFilterTable = rxEnFifoFilter; rxEhFifoConfig.idFilterPairNum = sizeof(rxEnFifoFilter) / sizeof(rxEnFifoFilter[0]) / 2U; rxEhFifoConfig.extendIdFilterNum = 0; rxEhFifoConfig.fifoWatermark = RX_MESSAGE_COUNT - 1U; /* Reduce the frequency to enter IRQ. */ rxEhFifoConfig.dmaPerReadLength = kFLEXCAN_19WordPerRead; rxEhFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; FLEXCAN_SetEnhancedRxFifoConfig(EXAMPLE_CAN, &rxEhFifoConfig, true); rxFifoXfer.framefd = &rxFrame[0]; rxFifoXfer.frameNum = RX_MESSAGE_COUNT; /* Set Rx Masking mechanism for MB. Only accept data frame with desired ID. */ FLEXCAN_SetRxMbGlobalMask(EXAMPLE_CAN, FLEXCAN_RX_MB_STD_MASK(0x7FFU, 0, 0)); #define RX_MESSAGE_BUFFER_0 (0U) /* Setup Rx Message Buffer 0. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x120U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_0, &mbConfig, true); #define RX_MESSAGE_BUFFER_1 (1U) /* Setup Rx Message Buffer 1. */ mbConfig.format = kFLEXCAN_FrameFormatStandard; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_STD(0x121U); FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_1, &mbConfig, true); Recommendation: To achieve a balanced trade-off between the number of Message Buffers and acceptance filters, Option 1 is recommended.

Using FreeMASTER block in Simulink 1 Table of Contents • Overview • Context • FreeMASTER Blocks • Generated ELF File • Application Example • References • Conclusion 2 Overview This article introduces the FreeMASTER blocks available in NXP Model-Based Design Toolbox (MBDT) and explains how they are used within a Simulink model to prepare an application for FreeMASTER integration. The primary focus is the FreeMASTER Config block, which enables the FreeMASTER Driver in the generated application and allows users to configure the communication interface and runtime parameters required by FreeMASTER. The article also introduces the FreeMASTER Recorder block, which can be used to add data-recording capabilities to the application. Why is this Important? Before FreeMASTER can communicate with an embedded application, the FreeMASTER Driver should be enabled and configured in the embedded application. The FreeMASTER blocks provided by MBDT simplify this integration process by allowing all required settings to be configured directly within the Simulink environment. This article is intended for: Simulink users working with NXP Model-Based Design Toolbox Developers integrating FreeMASTER into embedded applications Engineers interested in runtime monitoring and debugging Users preparing an application for future interaction with FreeMASTER By reading this article, you will understand how FreeMASTER support is enabled within a Simulink model and how the generated application is prepared for runtime communication and data access. You will also learn how the code-generation process produces an ELF file containing symbolic information corresponding to application variables, which is later used by FreeMASTER to access, monitor, and visualize application data. 3 Context Dedicated Simulink blocks integrate FreeMASTER into a Model-Based Design Toolbox project by automatically generating the software infrastructure required by the application. The overall workflow is illustrated below: Figure 1. FreeMASTER workflow In this workflow, the FreeMASTER blocks serve as the interface between the Simulink model and the FreeMASTER Driver that will be included in the generated application. 4 FreeMASTER Blocks FreeMASTER blocks can be found in the MBDT library under: S32K3xx Core, System, Peripherals and Utilities → Utility Blocks Figure 2. FreeMASTER Simulink Library Three blocks are available for FreeMASTER integration: FreeMASTER Config block FreeMASTER Poll block FreeMASTER Recorder block 4.1 FreeMASTER Config Block The FreeMASTER Config block is responsible for enabling and configuring the FreeMASTER Driver within the generated application. It inserts the software infrastructure required for communication between the embedded target and the FreeMASTER desktop tool and serves as the foundation for integrating FreeMASTER functionality into a Simulink model. Figure 3. FreeMASTER Config block This block provides a configuration interface divided into two sections: communication settings and runtime settings. 4.1.1 General Tab The General tab contains communication-related parameters: Connection Type – selects the communication interface used by FreeMASTER. Instance – specifies the peripheral instance assigned to FreeMASTER communication. Baudrate – defines the communication speed. ISR Priority – sets the interrupt priority associated with FreeMASTER communication. Figure 4. FreeMASTER General tab During configuration, a dedicated communication peripheral is assigned to the FreeMASTER Driver. In the example shown, communication is performed through LPUART6 operating at 115200 bps. Note: The peripheral assigned to FreeMASTER should not be reused simultaneously for other communication purposes. During initialization, the FreeMASTER Driver assumes control of the communication resources associated with the selected peripheral. 4.1.2 FreeMASTER Configuration Tab The FreeMASTER Configuration tab contains runtime-related settings: Mode – defines the FreeMASTER operating mode. Number of Scopes – specifies the number of available scope instances. Max Variables – defines the maximum number of variables handled by a scope. Automatic Buffer Size – automatically calculates communication buffer size. FIFO Receiver Queue Size – configures the receive queue used by the communication driver. Figure 5. FreeMASTER Configuration tab Together, these settings determine how the FreeMASTER Driver operates within the generated application. 4.2 FreeMASTER Recorder Block In addition to the configuration block, MBDT provides a FreeMASTER Recorder block that enables support for FreeMASTER recording functionality. Figure 6. FreeMASTER Recorder block Unlike the Config block, which is primarily focused on communication setup and driver integration, the Recorder block is designed for high-speed monitoring and visualization of application variables. It configures data acquisition resources that can be accessed later through the FreeMASTER desktop application, enabling detailed analysis of system behavior. The Recorder block is typically placed in application execution paths where rapidly changing signals need to be captured periodically. To support this, it uses an on-board memory buffer to store acquired samples, allowing high-frequency data to be recorded without requiring immediate transfer to the host PC. The buffered data can then be retrieved and displayed in FreeMASTER for waveform visualization, performance evaluation, and post-run analysis. The block provides the following configuration parameters: Id – unique identifier of the recorder instance. Name – user-defined recorder name. Buffer Size – amount of memory allocated for storing captured samples. Timebase – time reference used during recording operations. Figure 7. FreeMASTER Recorder block parameters The Recorder block is optional and can be used whenever runtime data recording capabilities are required. 4.3 FreeMASTER Poll Block MBDT also provides a FreeMASTER Poll block, which allows the application to explicitly call the FreeMASTER polling function within the Simulink model. Figure 8. FreeMASTER Poll block The Poll block does not require any configuration parameters. Its purpose is to provide a configurable location within the application where FreeMASTER communication handling and command processing can be executed. Figure 9. FreeMASTER Poll block mask The role of the Poll block depends on the operating mode selected in the FreeMASTER Config block. When the FreeMASTER Driver is configured in Poll Mode, the Poll block is responsible for both communication handling and command processing. When the Driver operates in Short Interrupt Mode, communication is handled by interrupts, while command processing is performed through the Poll block. Note: For both Poll Mode and Short Interrupt Mode, the Poll block is required and should be placed in an execution path that runs periodically, such as the application's main step function, to ensure timely processing of FreeMASTER requests. When the FreeMASTER Driver is configured in Long Interrupt Mode, communication handling and command processing are performed entirely by the driver interrupt routines. In this configuration, the Poll block is not required, and its execution has no effect on FreeMASTER operation. The Poll block complements the FreeMASTER Config and FreeMASTER Recorder blocks by providing a configurable mechanism for communication processing when required by the selected FreeMASTER operating mode. 5 Generated ELF File Once the FreeMASTER blocks have been added and configured, the model can be built using the standard code-generation workflow provided by Embedded Coder and MBDT. In addition to the application code generated from the Simulink model, the build process also produces an ELF (Executable and Linkable Format) file. When debug information is enabled during the build process, the ELF file contains symbolic information about application variables, functions, and memory locations stored in the DWARF debug sections. Otherwise, this information may be removed, preventing the FreeMASTER desktop tool from extracting the symbols required for variable access and monitoring. The ELF file is later loaded by the FreeMASTER desktop tool, allowing variables to be identified automatically without requiring manual memory address entry. This enables features such as variable monitoring, runtime configuration, data visualization, and recording. Note: Generating a valid ELF file with debug information is an important preparation step before attempting to establish communication with the target application. 6 Application Example To showcase the concepts described above, we can create a simple Simulink model example that uses the FreeMASTER Config block together with two application variables: counter and increment . In this example, the counter variable is periodically incremented by the value of the increment variable. The increment variable can be modified at runtime by the user directly from the FreeMASTER desktop application, allowing the rate at which counter grows to be adjusted on the fly. Figure 10. Application example Simulink model This simple model demonstrates the two fundamental capabilities enabled by FreeMASTER integration: Variable monitoring – observing the value of counter as it changes over time. Runtime variable modification – updating the value of increment from FreeMASTER and immediately observing its effect on counter . Figure 11. FreeMASTER application of the counter example   Once the model is built and the resulting application is running on the target, both variables become accessible through FreeMASTER using the symbolic information contained in the generated ELF file. The user can watch counter update in real time and interactively change increment to influence the application's behavior without recompiling or reflashing the target. 7 References Introduction to FreeMASTER FreeMASTER Driver and Documentation Package – The FreeMASTER Driver and its accompanying documentation are delivered as part of the MBDT installation. After installing the toolbox, they can be found in the root installation directory: NXP_MBDToolbox_S32K3\FreeMASTER\ 8 Conclusion This article introduced the FreeMASTER Configuration blocks provided by NXP Model-Based Design Toolbox and explained their role in preparing a Simulink model for FreeMASTER integration. By configuring the block appropriately, developers can include the required FreeMASTER support in the generated application and produce an ELF file suitable for runtime access to application data. The next article in this series will demonstrate how to use the generated application and ELF file to establish a connection between the target device and the FreeMASTER desktop application.

[LPC55S69] Zephyr MCUboot for Device Firmware Update Over UART Not Working with MCUmgr on LPC55S69 Hi, I've been trying to get Zephyr's MCUboot to work on the LPC55XpressoS69 using core 0. I am running the simple Blinky sample application in Zephyr.  Running the application just fine without any errors. However, I've been trying to send a device firmware update (DFU) over UART using mcumgr and for some reason I can't even establish a connection between mcumgr and my device. I keep getting a "NMP timeout." For context, my directory structure looks like the following: | __boards                 |__ lpcxpresso55s69_lpc55s69_cpu0.overlay __ src                |__main.c __sysbuild               |__mcuboot.conf                __mcuboot.overlay __prj.conf __sysbuild.conf My prj.conf looks as follows:   # Enable MCUMGR subsystem and OS/Image management commands CONFIG_MCUMGR=y CONFIG_MCUMGR_GRP_OS=y CONFIG_MCUMGR_GRP_IMG=y # DIRECT SMP over UART CONFIG_MCUMGR_TRANSPORT_UART=y CONFIG_MCUMGR_TRANSPORT_SHELL=n # Dedicate flexcomm0 to SMP — nothing else on the UART CONFIG_CONSOLE=n CONFIG_UART_CONSOLE=n CONFIG_LOG=n CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y # Required for SMP UART processing thread CONFIG_NET_BUF=y CONFIG_ZCBOR=y CONFIG_BASE64=y # Required subsystems for DFU CONFIG_FLASH=y CONFIG_IMG_MANAGER=y CONFIG_MCUBOOT_IMG_MANAGER=y # Dependencies for System/Reboot management via DFU CONFIG_REBOOT=y My sysbuild.conf is as follows:   SB_CONFIG_BOOTLOADER_MCUBOOT=y SB_CONFIG_MCUBOOT_MODE_OVERWRITE_ONLY=y My mcuboot.conf looks like    CONFIG_LOG=y CONFIG_MCUBOOT_LOG_LEVEL_INF=y CONFIG_MCUBOOT_SERIAL=y CONFIG_BOOT_SERIAL_UART=y CONFIG_UART_CONSOLE=n   My mcuboot.overlay looks like /* Step 3.4 - Configure button and LED for Serial Recovery */ // zephyr,console = &flexcomm0; // zephyr,uart-mcumgr = &flexcomm0; / { chosen { zephyr,code-partition = &boot_partition; zephyr,uart-mcumgr = &flexcomm0; zephyr,shell-uart = &flexcomm0; }; }; &flexcomm0 { status = "okay"; }; / { aliases { mcuboot-button0 = &user_button_3; mcuboot-led0 = &blue_led; }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &blue_led { status = "okay"; }; /* Enlarge boot partition to 64KB to fit MCUboot with serial recovery */ &boot_partition { reg = <0x00000000 DT_SIZE_K(64)>; }; &slot0_partition { reg = <0x00010000 DT_SIZE_K(160)>; }; &slot1_partition { reg = <0x00038000 DT_SIZE_K(160)>; }; &storage_partition { reg = <0x00060000 DT_SIZE_K(50)>; }; And finally my lpcxpresso55s69_lpc55s69_cpu0.overlay looks like / { chosen { zephyr,code-partition = &slot0_partition; zephyr,mgmt-smp = &flexcomm0; zephyr,uart-mcumgr = &flexcomm0; }; }; &flexcomm0 { status = "okay"; }; /* Enlarge boot partition to 64KB to fit MCUboot with serial recovery */ &boot_partition { reg = <0x00000000 DT_SIZE_K(64)>; }; &slot0_partition { reg = <0x00010000 DT_SIZE_K(160)>; }; &slot1_partition { reg = <0x00038000 DT_SIZE_K(160)>; }; &storage_partition { reg = <0x00060000 DT_SIZE_K(50)>; }; When I run the following MCUmgr command, I get back an NMP timeout, as seen below: > mcumgr --conntype serial --connstring "dev=COM11,baud=115200" echo "test" Error: NMP timeout So the mcumgr definitely realizes that the port is available (it would deny access otherwise), but it keeps getting timed out. I'm pretty sure this is a config option error. I've tried changing the config options numerous times but nothing quite seems to do the trick. I'm also pretty sure I'm missing some config option somewhere which is crucial for this to work.  I've looked through about as many application notes and user manuals out there as I can. None of them seem to help for my particular case: DFU using Zephyr MCUboot on an LPC55Sxx chip running a Zephyr application. Any help would is appreciated, though it may be best if someone tried it out on their board e.g. LPCXpresso55S69 and confirm they can carry out a UART DFU with any simple program. LPC55S6x LPC55S69-EVK  LPC55xx

LPC55s28 PN5190 NFC Read Library porting Hello Community, hello NXP-Team I'm looking for LPC55S28 ↔ PN5190 connection details (Host SW + DAL / BAL layer) I already have the PN5190 NFC Reader Library and would like to connect the LPC55S28 MCU to the PN5190 NFC frontend. I have reviewed the article “Using NFC Reader Library with LPC55S69”, but I am looking specifically for an LPC55S28‑compatible setup. Questions Is there an existing DAL/BAL (Driver Abstraction Layer) implementation for connecting the LPC55S28 to the PN5190? Has anyone successfully connected LPC55xx (LPC55S16 / LPC55S28 / LPC55S69) to a PN5190 using the NFC Reader Library? Is there a ready solution, reference project, or recommended starting point for the LPC55S28 + PN5190 combination? If not, is the LPC55S69 guide the correct and closest reference to follow for porting? Thank you! Re: LPC55s28 PN5190 NFC Read Library porting Hello @EduardoZamora, Thank you for your response. The guides you referenced are already much more helpful than what I initially found on the NXP website, so thank you for pointing them out. While reviewing these guides, I noticed that many of them include preconfigured folders or ready-to-use packages for specific processors or boards. These packages typically integrate the NFC Reader Library together with the control processor setup and, in some cases, DiscoveryLoop examples, which makes it much easier to get started. Would it be possible to provide a similar reference package or project (for example, importable into MCUXpresso) for the LPC55S28 + PN5190 combination, or at least for the closest supported LPC55xx configuration? Having such a project as a starting point would be extremely helpful for porting and validation. Thank you in advance for your support. Best regards, Radoslaw Tomasik Re: LPC55s28 PN5190 NFC Read Library porting Hello @RadoslawTomasik My apologies, there is no specific documentation or guide for PN5190 + LPC55S28. However, as you mention, you can refer to the following guides: - Using NFC Reader Library with LPC55S69 - NFC Reader Library Porting FRDM_K64F - NFC Reader Library Porting to i.MX RT1050 - NXP Community Those guides can be a good starting point. Regards, Eduardo. Re: LPC55s28 PN5190 NFC Read Library porting Hi, Unfortunately, there is no reference project for this specific setup. The NFC Reader Library for PN5190 includes support for LPC1769 and Kinetis K82; support for any other Host MCU must be implemented by the user. When you mention that linking the NFC Reader Libraries is no longer possible, does it mean that you are getting an error message when trying to link the folders? What is the procedure you are following? You should be able to link the folder by following the steps listed in NFC Reader Library Porting FRDM_K64F, "Link the NFC Reader Library" section. Also, linked resources should appear in Project Properties > Resource > Linked Resources. Regards, Eduardo. Re: LPC55s28 PN5190 NFC Read Library porting @EduardoZamora  When following the guide below: https://community.nxp.com/t5/NFC-Knowledge-Base/NFC-Reader-Library-Porting-FRDM-K64F/ta-p/1117798 I am able to successfully perform the described steps: Add the NFC Reader Libraries Create a project for LPC55Sxx Copy the DiscoveryLoop files into the LPC project However, when performing the same steps for PN5190 (using NxpNfcRdLib_PN5190_v07.14.00_Pub), I am able to: Add the libraries Create the LPC55Sxx project but when attempting to copy the DiscoveryLoop files, I encounter the following error: Problem occurred while copying resources. Cannot create linked resource. Could you please check this on your side and let me know whether this is a known limitation, or if there is a recommended workaround for PN5190 with LPC55Sxx? Thank you for your support. Best regards, Radoslaw Tomasik Re: LPC55s28 PN5190 NFC Read Library porting Hello @EduardoZamora , As a follow-up, I found that the original “Cannot create linked resource” error was caused by an excessively long file path. After shortening the path, this specific issue was resolved. However, a related problem still persists when adding the NFC Reader Libraries to the workspace with the “Copy projects into workspace” option enabled (see attached screenshot). Several documents (e.g. AN13425) explicitly recommend not selecting this option. When I follow this recommendation, copying the DiscoveryLoop files into the LPC55Sxx project works correctly. The downside is that, in this case, linking the NFC Reader Libraries is no longer possible, because the workspace does not contain any NFC example projects. As a result, it is not possible to link the following folders from NfcrdlibEx1_BasicDiscoveryLoop into the lpc55sxx_basic_discovery_loop project: DAL NxpNfcRdLib phOsal intfs Could you please advise whether this is a known limitation for PN5190 with LPC55Sxx, or if there is a recommended workaround? Also, is a preconfigured LPC55Sxx + PN5190 project available, similar to those referenced in other NFC Reader Library guides? Best regards, Radoslaw Re: LPC55s28 PN5190 NFC Read Library porting Hi, Could you please kindly clarify what you mean with "the DAL and intfs folders are part of the DiscoveryLoop example and cannot be linked independently"? You should not face any restriction when trying to link these folders to your project. You can either copy the folders to the workspace and link them or link the folders directly from the path where the Library was extracted; how they are shown in the project structure may depend on the method used. Relevant paths that need to be included are shown in "Add include paths" section from NFC Reader Library Porting FRDM_K64F after linking the folders. Regards, Eduardo. Re: LPC55s28 PN5190 NFC Read Library porting Hello @EduardoZamora , thank you for your reply and for the clarification. I understand that there is no reference project for the LPC55S28 + PN5190 combination, and I am prepared to implement the SPI DAL myself. My intention is to follow the NFC Reader Library Porting FRDM_K64F procedure as closely as possible, but I am encountering some differences when working with the PN5190 package. Here is the current status and the open questions: Importing an LPC55S28 SDK example (e.g. hello_world) works without any issues. Link the NFC Reader Library: The NxpNfcRdLib and phOsal folders can be linked to the LPC55S28 project and are visible under Project Properties → Resource → Linked Resources. However, these linked folders do not appear in the project structure as shown in the porting guide. The DAL and intfs folders are part of the DiscoveryLoop example and cannot be linked independently. Should these folders be copied from the DiscoveryLoop project into the LPC55S28 project instead of being linked? If so, which parts are considered platform-specific and expected to be modified by the user? Include paths can be configured manually, but it is unclear: Which include directories should be taken from the NxpNfcRdLib / phOsal libraries Which ones should come from the DiscoveryLoop example Since the libraries differ depending on the host MCU, and the integration procedure seems to vary from project to project, I would appreciate your guidance on the recommended setup for this configuration. This is fully within NXP platforms; I already have both evaluation boards connected and would like to proceed with basic driver and connection tests. Best regards, Radoslaw Re: LPC55s28 PN5190 NFC Read Library porting Hi Eduardo, thank you for your reply. To clarify what I meant: the issue is how the DiscoveryLoop example project is structured and imported. When importing the DiscoveryLoop project into MCUXpresso, it cannot be added to the workspace using the “Copy files into workspace” option. As a result, the project remains outside the MCU workspace directory and the DAL and intfs folders are therefore not visible within the workspace file system. Because of this, they cannot be linked independently in a practical way, as described in the FRDM_K64F porting guide. Due to this, I proceeded with a manual port: Copied the required DAL, intfs, NxpNfcRdLib, and phOsal folders directly into the LPC55S28 project so that they are fully visible in the project structure. Manually added all required include paths, preprocessor symbols, and source locations. Modified the DAL implementation to match the LPC55S16/LPC55S28 platform (SPI, GPIO, IRQ handling, timing, etc.). With this approach, the project builds and the structure is now consistent and transparent inside the MCU workspace. Regards, Radoslaw Re: LPC55s28 PN5190 NFC Read Library porting Hello, Thank you for your reply! It's greatly appreciated. I'm using the LPC55S69-EVK  + PNEV5190BP. I have downloaded the latest NxpNfcRdLib (NxpNfcRdLib_PN5190_v07.16.00_PUB) and SDK (SDK_26_06_00_LPCXpresso55S69) from the website. At first I imported the DiscoveryLoop example from the NxpNfcLib made for the K82F microcontroller. This was not a great success because there are a lot of micrcocontroller specific settings that were interfering with that process.  I then found the LPC porting guide mentioned earlier in this thread. This was also not a success because the SDK and Nfc lib versions were basically too old to properly use. I then did what you already mentioned. I imported the lpcxpresso55s69_lpc_gpio_led_output_cm33_core0 example from the newest SDK and added the DAL, intfs, NxpNfcRdLib, and phOsal folders directly to the project. Then I configured the paths, preprocessor and source locations. The I added the missing SDK components. I tried to modify the DAL but because there were quite a few differences between the DAL that worked for the old Nfc lib and the new lib I was not able to pull this off. It actually compiles but it gets stuck in the hardfault handler on the SPI_MasterInit function caled bij phbalReg_Init().  I think this is mostly because I'm quite new to using NXP products. I'll include a zip file of the project. Maybe there are things that I did wrong or maybe I missed something. Re: LPC55s28 PN5190 NFC Read Library porting Hello, Were you able to figure out how the library can be ported? I keep getting stuck at rewriting the DAL because the SDK and NFC-library structure were changed quite significantly. I tried to base my code of off this guide with included source code . However this NFC-library version does not include the PN5190 drivers. When the PN5190 was added quite a few significant changes were added to the library which causes a lot of errors when I tried to just replace the NfcRdLib, phOsal and intfs folders. I also ran into a couple of errors that were caused by the newer SDK version so I basically don't really know what to do now. Especially because the recommended guides 1 & 2 are not up-to-date anymore. Thanks in advance!  Re: LPC55s28 PN5190 NFC Read Library porting Hi Emiel, Are you using the same hardware combination (LPC55xx + PN5190)? Basically, you can use the existing porting guides as a reference, even though there is no official LPC55S28 + PN5190 project. I would recommend downloading the latest NxpNfcRdLib_PN5190 package and importing it into MCUXpresso. As a starting point, create a new project from an LPC55xx SDK example (for example, hello_world) and port the NFC Reader Library manually. The approach that worked for me was: Copy the DAL, intfs, NxpNfcRdLib, and phOsal folders directly into the LPC55S28 project so everything is part of the project structure. Manually configure all required include paths, preprocessor symbols, and source locations. Rewrite the DAL for the LPC55xx platform (SPI, GPIO, IRQ handling, timing, etc.). Enable any missing MCU drivers through Manage SDK Components in MCUXpresso and adapt the DAL to use those drivers. Regarding the drivers you mentioned as missing: which ones are they exactly? If you can list the missing modules or post the compiler errors, it will be much easier to identify what still needs to be ported. The errors caused by the newer SDK may also depend on the exact LPC device and SDK version you're using. I would first verify that you're using the latest SDK available for your MCU from NXP and make sure it matches the version expected by your project. From your description I can only make an educated guess, but if you can share: the exact LPC55xx device, the SDK version, the NFC Reader Library version, and a few of the compilation errors, I'd be happy to help identify the required changes. I went through a similar manual port, so I may be able to point you in the right direction. I hope this helps you move a bit further. Re: LPC55s28 PN5190 NFC Read Library porting EDIT: I managed to "fix" this error by adding uint32_t flags instead of void to the definitions of PH_DRIVER_LPC_TIMER_IRQ_HANDLER. Still doesn't work though Re: LPC55s28 PN5190 NFC Read Library porting Thank you very much. I'm not entirely sure how I should configure the pin_mux and clocks. I did it via the pin configuration tool though but I'm not sure if I have done it correctly. But I also don't quite understand why I would have to do it like this because these settings seem to be overwritten in the phbalReg_LpcOpenSpi.c file anyway.  I did find out that in phbalReg_Init(), I think it was, I needed to change the way the clock frequency was selected because this had been changed some time ago.  I then was able to compile and download the code to the microcontroller. However, nothing works except the debug text :(. I took a look at your code however, I ran into more problems. The library version I have expects the interrupt handler to be like this: PH_DRIVER_LPC_TIMER_IRQ_HANDLER(uint32_t flags); while literally every example I have found thus far uses your define: PH_DRIVER_LPC_TIMER_IRQ_HANDLER(void); This results in the following error:  ../DAL/src/LPCOpen/phDriver_LPCOpen.c:42:47: error: initialization of 'void (*)(uint32_t)' {aka 'void (*)(unsigned int)'} from incompatible pointer type 'void (*)(void)' [-Wincompatible-pointer-types] 42 | ctimer_callback_t ctimer_callback_table[] = { PH_DRIVER_LPC_TIMER_IRQ_HANDLER, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Your help has been very helpful thus far. Would it be possible to include the phDriver_LPCOpen.c file or a zip of the entire project? Thanks in advance! Re: LPC55s28 PN5190 NFC Read Library porting Hi Emiel, From your description, the first thing I would double-check is your pin configuration (pin_mux) and verify that the correct Flexcomm instance is configured for SPI. A mismatch there can easily cause the code to end up in the HardFault handler during SPI_MasterInit(). Additionally, make sure that the spi_master_config structure is properly initialized before calling SPI_MasterInit(). It's also worth reviewing the Exchange function to ensure that both the WRITE and READ phases are implemented correctly, as the newer Reader Library expects slightly different behavior than the older versions. I've attached my files for reference. They may help you compare your implementation with a working example, but I can't guarantee they'll work without modification since they were created for a different setup. Hopefully this points you in the right direction. Re: LPC55s28 PN5190 NFC Read Library porting Hi Emiel, Yes, you need to configure the ports using the MCUXpresso Config Tools (Pins/Clock Configurator). The DAL assumes that the MCU peripherals are configured correctly, so those settings are not completely replaced by phbalReg_LpcOpenSpi.c. I've attached my pin_mux files and the LPCOpen sources for reference. Please keep in mind that this is reference code only. The project was never fully tested or finalized, so I can't guarantee it will work out of the box. I think there's still quite a bit of debugging ahead before everything works correctly. Unfortunately, I won't be available for about the next two weeks, so I probably won't be able to respond to any further questions until then. Good luck with the porting, and I hope the attached files help you move forward. Re: LPC55s28 PN5190 NFC Read Library porting EDIT: Yes the data stream send over SPI seems correct Line 151 of phhalHw_Pn5190.c: uint8_t PH_MEMLOC_REM pTxBuff[] = {0x7F /* Direction byte */, 0x00, 0x04 /* HDLL Get Version command length */, 0xE1 /* HDLL Get version command OP code */, 0x00, 0x00, 0x00, 0x75, 0x48 /* Crc */}; This is exactly the data that can be seen in the logic analyzer screenshot I sent earlier. Re: LPC55s28 PN5190 NFC Read Library porting Hello, Thanks yet again. This is my last week before school starts so I doubt I'll be able to work on it after you get back from your holiday 🥲. I managed to get the SPI sort of working though. I'm not really sure how though. Out of desperation I replaced the pin_mux.c and .h files with your files. This obviously didn't work so I changed them back to what I had before and the SPI started working 🤷‍♂️. Anyway, I have included the logic analyzer screenshot. I have no idea if the data that is being send is correct but it looks sensible to me. However, as you can see there is no response from the PNEV5190B. I have also included a photo of my setup. I've switched R5 over to R7 to enable the external SPI interface. In the debug window you can see that it goes through the functions without a problem. However, after sending the config in line 286 of phhalHw_Pn5190.c it waits for an interrupt it never receives and errors out.  This is the pin map: JP1 on PNEV5190B P23 on LPCXpresso55S69 (Mikroe) P24 on LPCXpresso55S69 (Mikroe) 1.   EXT_SPI1_CLK 4.  LSPI_HS_SCK (PIO1_2) X 2.  EXT_SPI1_MOSI 6.  LSPI_HS_MOSI (PIO0_26) X 3.  EXT_SPI1_MISO 5.  LSPI_HS_MISO (PIO1_3) X 4.  EXT_SPI1_CS0 3.  LSPI_HS_SSEL1 (PIO1_1) X 5.  EXT_NFC_IRQ X 1.  PIO1_5_GPIO_ARD (PIO1_5) 6.  EXT_NFC_CLK_REQ X X 7.  EXT_NFC_WKUP_REQ X 2.  WAKE/GPIO (PIO1_18) 8.  EXT_NFC_DWL_REQ X 3.  PLU_OUT6/GPIO/FC2_USART_RXD_ARD/SD1_D1 (PIO1_24) 9.  GND X X 10. GND 8. GND X

LX2160A get MP key failed Hi NXP, We are building LX2160A secure boot system based on LLDP and verifying MP key function. Install and start up the secure boot system on our LX2160A board are OK and so we think ITS bit value is 1, but get "Device is not initiated" error after execute "mp_app -p" command. Do you have any advice to check this issue ? Thank you, Jeffrey  Re: LX2160A get MP key failed Did customer follow LLDP document section 6.4.4?   Such as Run tee-supplicant & command from the Linux prompt. Depending on the Linux kernel version used insmod securekeydev.ko from right folder Please also let customer enable kernel printk when run 'mp_app', and share their log. echo 8 > /proc/sys/kernel/printk dmesg Re: LX2160A get MP key failed Hi yipingwang, Yes, we start tee-supplicant and load securekeydev.ko before execute mp_app command. The following is dmesg information. Jeffrey Re: LX2160A get MP key failed Please refer to the following update from the AE team. From customer's feedback, I can see "error: caam_submit_mp_get_pub_key_op: submit_job", it indicates send job to SEC failed. Please ask customer do below test in their Linux system, 1. run xtest, to see any error report? 2. please run "modprobe caam" to install caam module for LX2160, if install module failed, please update modules compatible with your kernel version. 3. If also report error, apply below patch to check SEC return result to identify the error type, and share their full log. diff --git a/securekeydev/securekey_caam.c b/securekeydev/securekey_caam.c index b82acd3..d657742 100644 --- a/securekeydev/securekey_caam.c +++ b/securekeydev/securekey_caam.c @@ -59,12 +59,14 @@ static int submit_job(struct device *jrdev, uint32_t *desc) /* Call caam_jr_enqueue function for Enqueue a job descriptor head. */ ret = caam_jr_enqueue(jrdev, desc, caam_op_done, NULL); + pr_err("caam_jr_enqueue ret (%d)\n", ret); if (!ret) wait_for_completion_interruptible(&comp); else return ret; ret = job_comp_status; + pr_err("job_comp_status ret (%d)\n", ret); return ret; } Regards, Re: LX2160A get MP key failed About your comments, 1. run xtest, to see any error report? Please refer to attached xtest log. 2. please run "modprobe caam" to install caam module for LX2160, if install module failed, please update modules compatible with your kernel version. We built caam module in kernel already. 3. If also report error, apply below patch to check SEC return result to identify the error type, and share their full log. The dmesg about caam and mp_app return as below.   Thank you. Re: LX2160A get MP key failed 1. Please make sure caam job ring work well in Linux kernel, please run below command to check caam jr interrupt increase or not root@localhost:~# cat /proc/interrupts | grep jr 378: 41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GICv3 172 Level 8010000.jr 379: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GICv3 173 Level 8020000.jr 380: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GICv3 174 Level fsl-jr0 root@localhost:~# root@localhost:~# root@localhost:~# dd if=/dev/hwrng of=/tmp/random.dat bs=1 count=16 16+0 records in 16+0 records out 16 bytes copied, 0.000420759 s, 38.0 kB/s root@localhost:~# root@localhost:~# root@localhost:~# cat /proc/interrupts | grep jr 378: 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GICv3 172 Level 8010000.jr 379: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GICv3 173 Level 8020000.jr 380: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GICv3 174 Level fsl-jr0 root@localhost:~# 2. In submit_job() the called function caam_jr_enqueue() return (-EINPROGRESS = -115) on success. Please try apply below patch to check caam enqueue return result. https://github.com/nxp-qoriq/linux/commit/4d370a1036958d7df9f1492c345b4984a4eba7f6#diff-8acc41c534456288daba59a125ddb3f779635dc493ff4888545adbf1dd0a17c1R327 diff --git a/securekeydev/securekey_caam.c b/securekeydev/securekey_caam.c index b82acd3..808e8da 100644 --- a/securekeydev/securekey_caam.c +++ b/securekeydev/securekey_caam.c @@ -59,12 +59,14 @@ static int submit_job(struct device *jrdev, uint32_t *desc) /* Call caam_jr_enqueue function for Enqueue a job descriptor head. */ ret = caam_jr_enqueue(jrdev, desc, caam_op_done, NULL); - if (!ret) + pr_err("caam_jr_enqueue ret (%d)\n", ret); + if (ret == -EINPROGRESS) wait_for_completion_interruptible(&comp); else return ret; ret = job_comp_status; + pr_err("job_comp_status ret (%d)\n", ret); return ret; } Re: LX2160A get MP key failed 1. Please make sure caam job ring work well in Linux kernel, please run below command to check caam jr interrupt increase or not Ans: Yes 2. In submit_job() the called function caam_jr_enqueue() return (-EINPROGRESS = -115) on success. Please try apply below patch to check caam enqueue return result. Ans: Our system uses Linux kernel v5.15.71-rt51 and it seems need not do any additional patches. 3. In addition, after run mp_app -p command, the process stops at wait_for_completion_interruptible() and it is waiting the return so far.     Re: LX2160A get MP key failed Please double check your kernel source code. caam_jr_enqueue() has update return value in this brach. https://github.com/nxp-qoriq/linux/blob/95448dd0dc9b621ae027cbefedaaa7c3d0d3ad2d/drivers/crypto/caam/jr.c#L565 Re: LX2160A get MP key failed Please refer to the following update from the AE team. Customer can check whether ITS bit enabled by u-boot 'md' command. md 0x1e80200 Can customer share caam_jr_enqueue() function source code? The source code path is "linux/drivers/crypto/caam/jr.c". Or they can share us their source code link. Re: LX2160A get MP key failed We checked all drivers/crypto/caam source files and they are the same. We enable ITS by uboot scripts as below mw.l 0x1e80200 0x4 mw.l 0x1e80020 0x2 Do you think the ITS activation process is incomplete ?

68LC302 and serial bootstrap feature Hi all. Hopefully there is still someone around in 2026 that has some knowledge tucked away in the back of their brains regarding the LC302. I've been working on a little project involving an LC302 and I am interested in using the serial bootstrap feature. I just cant seem to get it to work and I wondered if there is anything particularly special that needs to be done to make it work. I've tried everything I can think of, and I'm currently looking at replacing the LC302 that I currently have in case it is somehow faulty, but thought I'd ask the question before I go to that effort. FWIW the markings on the package are (with Motorola logo): MC68LC302PU25CT 2J29A QQDJ0316 I am powering it with 5V. Basically I cannot get it to echo back anything that I am sending to it. I came across the following post which seemed to describe the same problem, but I dont seem to have the same issue: https://community.nxp.com/t5/ColdFire-68K-Microcontrollers/We-have-been-using-the-68LC302-for-decades-without-major/m-p/612300 Things I've tried/I can observe with my scope/logic analyser: I've tried using both PLL mode and not. In PLL mode I used a 4MHz oscillator (4.192 is hard to come across). In this mode I used 9174 baud (4MHz*4, /109, /16). Without the PLL I used a 20MHz oscillator with baud 11467. I've used my signal generator to feed 4.192MHz in and used the baud rate quoted in the datasheet also to no avail. If I pull PA7 high to disable bootstrap mode, I can observe some brief activity on the AS pin, presumably as the CPU tries to read its reset vector from external memory. If I pull PA7 low to enable bootstrap mode I don't observe this activity any more, presumably as the CPU is held in reset. I did early on discover that PA7 seems to have some kind of current source on it, and was sourcing approx 3-4mA of current (measured with my multimeter in current mode), overpowering my external pull down resistor and resulting in a logic high. This feels like an extremely high amount of current to me, and does anyone have an explanation for that? It seems vaguely related to the above thread causing PA7 to be pulled too high unexpectedly. Maybe my part is faulty? Reset and HALT are being asserted simultaneously (I've got lots of 68k experience from hobby projects over the past several years). 🙂 I've double and triple checked all of my wiring including the polarity of the TX/RX signals, and even pulled the flow control inputs for SCC1 to their negated state just in case. I've measured with my oscilloscope that my USB-serial adapter does indeed generate the baud rate that I am requesting, and looping TX to RX allows me to echo back the characters that I send in putty, so I am fairly confident there is nothing odd going on there. I havent wired up any of the memory busses, because for now I am just interested to see if I can load some code in via serial and make an LED blink, but the BUSW pin has been strapped for 16-bit bus operation, if that matters? Does anyone have any other suggestions before I go desoldering stuff? Thanks! Re: 68LC302 and serial bootstrap feature Hi, thanks for the message. I have made sure that I am using SCC1 related pins. My setup is on a perfboard with wire wrap, so there are no other influences on any of the pins other than what I have wire wrapped. I've verified with a multimeter that reset and halt are asserted together and that they reach 0V, and that all strap pins are seeing the required voltage levels with no floating pins. Also, as mentioned in my post, I have also tried using 4.192MHz supplied by my signal generator and the baud rate quoted in the datasheet, but this didn't help. Apologies when I said I had tied CD1 to its negated state, I've just mixed up my terminology and it is indeed tied to ground (asserted), along with CTS1 for good measure. I'll try sending 576 bytes as a test in case it is just not echoing them back for some reason, but is still receiving them correctly. Thanks Re: 68LC302 and serial bootstrap feature Hello, The first thing I would check is CD1 . For the LC302 serial bootstrap echo path, the manual says the SCC hardware echoes received characters back on TXD1 , but CD1 must be asserted; on SCC1 the external CD1 pin must be tied low . If you pulled the SCC1 modem-control inputs to their “negated” state, that may be exactly why you see no echo. Other important points from the LC302 boot description: Serial bootstrap is enabled by sampling PA7 = 0 during hard reset , where hard reset means both RESET and HALT asserted . PA7 must not float; it must be deliberately pulled high or low during reset. The first 576 bytes received on SCC1 are stored in dual-port RAM, and each received character is echoed back out of TXD1 ; the device will not leave boot mode until all 576 bytes are received. For internal-clock bootstrap, the documented nominal clock assumptions are 4.192 MHz or 32.768 kHz , with the SCC programmed to approximately 9600 baud. In asynchronous UART mode, the bit rate is 1/16 of the TCLK1/RCLK1 clock rate when using the external clock option. So before replacing the part, I would try this exact minimal setup: Hold RESET and HALT low together . Strap PA7/BOOT low with a strong enough pulldown to overcome whatever is on your board. Select the intended clock mode with PA5 : PA5 = 0 : internal boot clock mode. PA5 = 1 : external clock on TCLK1/RCLK1 , 16× baud. Strap PA12/MODCLK0 consistently with the clock source; the manual samples it during hard reset to distinguish the nominal EXTAL frequency. Tie CD1 low . Keep RXD1 , TXD1 , RCLK1 , and TCLK1 wiring consistent with SCC1, not SCC2. The boot feature is for SCC1 in the LC302 description. Send a full 576-byte test stream, not just one character, although the echo should appear character-by-character once receive is working. The 3–4 mA sourced from PA7 is suspicious . The datasheet-level input leakage value retrieved is only 20 µA max , far below milliamps. Since PA7 is also a bidirectional multi-function pin, it is possible to get contention if something else is driving it or if the part has already left the reset-sampling state, but during reset-as-boot-strap it should not require sinking several mA just to read a low. I would check for a board-level pullup/driver/solder bridge on PA7 , verify the package pin orientation, and measure the current while both RESET and HALT are actively asserted. One more practical note: your 4 MHz internal-clock attempt is not equivalent to 4.192 MHz . It may be close enough for some UARTs if the other side is adjusted, but the documented internal bootstrap mode assumes the nominal LC302 clock values, so for eliminating variables I would use 4.192 MHz with the documented baud , or use the external-clock mode and provide clean TCLK1/RCLK1 = 16 × baud .   regards Re: 68LC302 and serial bootstrap feature So, I replaced the 68LC302 for another one, and for about 2 seconds it worked (echoed back the characters I was sending it), until I power cycled it, and from then on it wouldnt work any more again. Initially I didnt have CD1 grounded, because the datasheet says this is a "dont care" for the purposes of the serial bootstrap process, and it did indeed work in this configuration. After it stopped working I tried grounding CD1 but this didnt help. So close, and yet so far. This project is just cursed. 😞 This one also seems to have some kind of heavy-ish current source on PA7 that needs a reasonably strong resistor to pull it down sufficiently, or a tri-state driver to override it. Re: 68LC302 and serial bootstrap feature Initially when I tested with the signal generator I didnt have it terminated. In the most recent case I am using an on-board 20MHz oscillator and ignoring the PLL configuration for the time being just to simplify things. (This isn't the configuration I want to run in the final version of my project (if I ever get there) though, becuase I want to use a 4MHz oscillator to drive another part as well.) Power for the whole board is coming from a small USB-serial module from Mikroe which has an MCP2221A on it. This unfortunately has a diode in series with the 5V supply so the board sees closer to 4.7V, but I have also used a bench PSU to supply a solid 5V. I cant think of a case where the CPU would not have power but a 5V signal would be present on any of the pins - power is either there for everything or it isnt. But if that is a situation that could result in latch-up and destroy the chip then I might just ditch the whole project now, because I am looking at building it into an arduino style board, and if these parts are just too overly sensitive to wierd and wacky power situations then they are probably highly unsuitable for this project. 😞 Re: 68LC302 and serial bootstrap feature I think you're killing the chip. There are a few ways to do that, and reading your posts suggests two possibilities. You're running (or have run) the clock from an external signal generator. Have you terminated the cable from the signal generator so as to avoid reflections and overshoots? If you've got a 50 ohm coax from the signal generator without a 50 ohm resistor on the end, it'll glitch (the reflections) up to 10V and down to -5V. That'll kill the chip for sure. If you have an Agilent signal generator (others might be similar), program it to "0 to 5V" and don't notice the "terminated or not" option, then setting it to terminated and not adding one will have it generate 0-10V which will then glitch to -10V to 20V. Check the clock signal at the CPU with a good (high frequency, like 100MHz or better) oscilloscope. How are you powering the chip driving the serial port on the CPU? Do you have a MAX RS232 transceiver powered from the 5V that is powering the CPU (and being fed 12V RS232 from a PC or something)? Or are you using an external TTL-level (3V3 or 5V) serial port connected directly to the CPU? If you're using the latter then when you power the CPU off you'll still be driving that external voltage into that CPU pin. TTL-RS232 idles at 5V, so doing that might damage the pin or even cause fatal latch-up. Google says this chip can suffer fatal latch-up if you do this. Check "latch-up" on Wikipedia. And make sure everything is grounded together. This but this is something people using CAN always forget to do. Ditto RS-232. Tom Re: 68LC302 and serial bootstrap feature I suppose another option is to just build something properly on a PCB. I have one designed already, but I was hoping to test said design with a prototype first, before comitting to PCBs. I sort of get the feeling that if I tried to build it up on a PCB where it has a better electrical environment, maybe it would just work. Part of the reason for wanting to prototype it was to make sure I had the correct logic for multiplexing the strapping pins between their straps and GPIOs to enter bootstrap mode during reset. The reset and bootstrap enable can be provided by some GPIOs of the MCP2221A, such that you can either do a reset on its own, or reset with bootstrap enabled. My signal generator is a Siglent SDG2122X. When I use it I have it set to 5V peak to peak with a 2.5V offset such that it ranges from 0 to 5V, rather than -2.5 to +2.5. My scope is a Keysight MSOX2024A, and I used that to check the signal coming from the signal gen. I wouldnt say I was using a fully optimal ground setup at the time when I did that, so I was seeing over/undershoot on the clock signal, but I'd have put that down to the fact I wasnt using a group clip or ground spring on the scope probe - I was more interested in measuring the frequency seen at the pin of the chip and just double checking the voltage was achieving 5V and not being dragged down by anything. I dont remember to what extent it was over/under shooting, I'd have to measure it again I guess. Re: 68LC302 and serial bootstrap feature We've flown to the moon on wire wrap too. 🙂 Power is formed by some rings of wire that I've run around the perimiter of the footprint for the breakout board that the chip is soldered to. It's probably not 100% ideal, but the general technique has worked pretty well for me to date. But I have added decoupling caps to all power pins as close to the chip as I can get them. I recovered the chips from some old Cisco modules. They were known to be working when I pulled them off, and probably wouldn't be fakes coming from Cisco. I'm travelling for work at the moment but I am thinking to try wiring up a ROM when I get back , and program it with some simple code to see if I can make it receive and echo back data. Re: 68LC302 and serial bootstrap feature I'll have to check the settings of the signal generator when I get back home as I don't recall off the top of my head what that is set to. I've only used the signal generator on the first chip I tried though, the second one has only ever had the on-board 20MHz oscillator connected to it. Re: 68LC302 and serial bootstrap feature There's nothing wrong with wire-wrap. I've seen some very high speed stuff built on that. The thing you need to do is to have a perf-board with power traces or a ground plane on it. A ground plane is best (and maybe a power grid on the other side). Then you wrap the ground pins with a short wire and solder to the power plane. You can get better signal integrity on one of those than you can manage with a PCB. Make sure all ground pins are solidly grounded and that you have plenty of small and large bypass caps on the board. It should work. Unless the chips you have are dark-grey-market and scraped off of faulty boards. I've seen that. That's a good signal generator. But if you have it defaulting to "Load: 50 ohm" like it shows in the User Manual, but don't have that terminator it will (and is documented to) send a -2.5V to 7.5V signal with 50 ohms source impedance. Connected to your board, the MPU input protection diodes will cut in, conducting 50mA into the ground and power rails, so it might not be obvious on the oscilloscope that is happening. But 50mA is way too much. Tom

LX2162A USXGMII link never completes Hey all, I have an LX2162A SoM manufactured by Solidrun. I'm using a Clearfog devkit but moving to a custom carrier soon.  Solidrun provides base RCW/DCP/DPL and I've verified functionality. In my case, the DPC for dpmac3 works for the SFP cage and I get an XFI link via SFP DAC cable and various SFP modules. The RCW "rcw_2000_650_2900_3_11_0_auto" sets to SerDes1=3, SerDes2=11 and I'm using a QorIQ kernel (lf-6.6.52-2.2.0) and mc-utils (10.39.0) but with some Solidrun patched applied to both. Uboot and other things are also patched. All patches come from here: https://github.com/SolidRun/lx2160a_build/tree/develop-ls-6.6.52-2.2.0 I have a MaxLinear GPY245-EKV-1 (and -2) devkit(s) that wants USXGMII over DAC cable to connect the phy to the device. Apparently this is pretty normal. Eventually this phy chip will be integrated into SerDes2=7 Lane6 and Lane7 but I have to use the SFP cage on the Clearfog for testing. Clearfog SFP (mac3) <-> DAC CABLE <-> GPY245-EVK-2 SFP I'm only trying to configure dpmac3 to use this USXGMII link via DPC: mac@3 { link_type = "MAC_LINK_TYPE_PHY"; enet_if = "USXGMII"; }; (I've also tried MAC_LINK_TYPE_BACKPLANE) Confirmed via "restool dpmac info dpmac.3" shows "DPMAC ethernet interface: DPMAC_ETH_IF_USXGMII". In Linux, I added the MaxLinear driver and patched a few things: gpy_update_interface() fix (LKML, Daniel Golle). This was returning -EINVAL for USXGMII interface, crashing phy_state_machine. Patched lynx_pcs_config_usxgmii() in pcs-lynx.c to also write MII_BMCR (BMCR_ANENABLE | BMCR_ANRESTART) via mdiobus_c45_modify(), since the function only ever wrote MII_ADVERTISE and never enabled AN on the Replicator block itself. This gap matches another post on this forum ("LS1028A 10g-qxgmii phy bring-up") which found the identical symptom (MMD31.0/Replicator control register stuck at 0) and got AN to kick in after manually setting bit 12. This is the DPMAC3 Linux devicetree entry: &dpmac3 { managed = "in-band-status"; phy-mode = "usxgmii"; phy-handle = <&gpy245_p0>; phys = <&serdes_1 7>; status = "okay"; }; where `gpy245_0` is the MDIO node. MDIO traffic to the phy is working. I added a printout in the lynx_pcs driver which shows the readback: mdio_bus 0x0000000008c0f000:00: USXGMII: wrote ADV=0xd601 BMCR=0x1a00 readback ADV=0x6b00 BMCR=0x0800 BMSR=0x0000 LPA=0x0000 Question: Given writes to MDIO_MMD_VEND2 registers on this PCS instance don't appear to persist, is there a known additional step (SerDes/PCS block enable, protocol-specific initialization, or similar) required before the USXGMII on the LX2162A family SoCs will accept configuration? Is protocol 3 fully validated for USXGMII on dpmac3, or primarily intended/tested for XFI? Other questions: Maybe I don't understand GPY245 and USXGMII. I see some folks refer to this as QXGMII and I can't tell if the LX2162A is even capable of that working. Maybe I need to reach out to Solidrun, but all of their patches do not seem to limit the LX2162A's capability. Thanks!

Code, Connections, NXP with WS2812 Hello, I am new to NXP microcontrollers and would like to interface a 16-pixel WS2812B RGB LED strip. Which NXP development board would you recommend for this project? I would also appreciate any example projects, SDK examples, or documentation for controlling WS2812B LEDs. Thank you. Re: Code, Connections, NXP with WS2812 Thank you for your interest in NXP products! The FRDM-MCXA366 is an ideal board for your project. NXP provides a dedicated, beginner-friendly application note that specifically demonstrates how to control WS2812B LEDs using the MCX A366. The document includes board recommendations, hardware connections, source code, and step-by-step setup instructions. AN14980 – Emulating the WS2812 Bus with FlexIO on MCX A366 This application note explains in detail how to use the FlexIO module on the MCX A366 to emulate the WS2812 communication protocol and drive WS2812B LEDs. This should provide everything you need to get started with your design. Please let me know further questions Best regards, Alondra Re: Code, Connections, NXP with WS2812 Hello Alondra, Thank you for the suggestion! Our design is still in the evaluation phase. Before we decide on a board, I wanted to check if the LPC5514JBD64E can also support WS2812 LEDs? Best regards, Kishore

S32K324 FlexIO SPI Master Emulation (S32DS 3.5 / RTD 4.0.0 ) Hello, I am configuring a FlexIO-emulated SPI Master on an S32K324 to communicate with an external SPI slave device. Due to trace routing on our custom board, the physical lines targeting this device are wired to the chip's default FlexSPI0 pins. Therefore, I must use the emulated Flexio_Spi driver stack. this is my setup BUS_FLEXSPI0_UP_SBC_CS PTD8 fxio_d11 BUS_FLEXSPI0_UP_SBC_CLK PTD9 fxio_d0 BUS_FLEXSPI0_UP_SBC_MOSI PTD15 fxio_d10 BUS_FLEXSPI0_UP_SBC_MISO PTD22 fxio_d27 My Environment: IDE:S32 Design Studio for S32 Platform (Version: 3.5, Build id: 240726 Update 13) CPU : S32K324 SDK: Real-Time Drivers (RTD) Version 4.0.0 (Production Release) Is there an official NXP application note or guide that illustrates the end-to-end integration stack specifically for RTD 4.0.0? I need a reference that covers everything from assigning the pins in the tool, mapping the shifters/timers, up to initializing the driver in the main application code. Re: S32K324 FlexIO SPI Master Emulation (S32DS 3.5 / RTD 4.0.0 ) Hello @Kazarian , There is no dedicated application note, to my knowledge, that describes the full end-to-end integration of FlexIO-emulated SPI specifically for S32K324 with RTD 4.0.0 and with this exact pin assignment. The closest official reference is the example project included in the S32K3 RTD package. Please check the RTD example similar to  Lpspi_Flexio_Ip_Transfer_S32K344. This example demonstrates the intended RTD integration flow for FlexIO-based SPI transfer, including the FlexIO SPI driver initialization and the relation between LPSPI and FlexIO SPI instances.   For your custom board, the main points to adapt are the following (as a general guidance): Pins configuration Configure the listed pins in the Pins tool as FlexIO signals: PTD8 → FXIO_D11, chip select PTD9 → FXIO_D0, clock PTD15 → FXIO_D10, MOSI PTD22 → FXIO_D27, MISO Make sure the MISO pin has the input buffer enabled. Also verify in the S32K324 IOMUX/pinout documentation that these FlexIO functions are available for your exact package. FlexIO SPI configuration In the FlexIO SPI configuration, map the SPI signals to the corresponding FlexIO pin numbers, not only to the physical MCU pins: SCK = FXIO_D0 MOSI = FXIO_D10 CS = FXIO_D11 MISO = FXIO_D27 Assign the required FlexIO timers and shifters consistently with the generated configuration. Best regards, Pavel

IMX8MP On chip RAM memory access Hello, I want to learn how I can access the OCRAM  to read and data to the memory. Can anyone advice how I could achieve that on Linux cortex A-53? On-Chip RAM - OCRAM (576 KB) start address: 0x00900000 => reserved for ROM start address: 0x00918000  =>OCRAM FREE AREA end address: 0x0097FFFF https://www.nxp.com/webapp/Download?colCode=IMX8MPRM  Thank you! IMX8MPLUS  i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Yocto Project Re: IMX8MP On chip RAM memory access Hi Roman Luz, does this tip works for you? Regards, Stefano Gigli Re: IMX8MP On chip RAM memory access Hi @Roman_Loz , you could try including compatible = "shared-dma-pool"; and it should work. ocram_dma: ocram_dma@970000 { no-map; compatible = "shared-dma-pool"; reg = <0 0x970000 0 0xC00>; // 3KB }; Regards, Samhitha Kashyap Re: IMX8MP On chip RAM memory access Hi, I am trying to use the OCRAM the way you suggested but I get kernel panic when I try to memcpy to/from it. Could you please help me understand what am I doing wrong or missing? dtsi: resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; ocram: ocram@900000 { no-map; reg = <0 0x900000 0 0x70000>; }; ocram_dma: ocram_dma@970000 { no-map; reg = <0 0x970000 0 0xC00>; // 3KB }; ... module init: // Find the OCRAM DMA node by name np = of_find_node_by_name(NULL, "ocram_dma"); if (!np) { pr_err("Failed to find OCRAM DMA node in device tree\n"); return -ENODEV; } // Lookup the reserved memory region rmem = of_reserved_mem_lookup(np); if (!rmem) { pr_err("Failed to lookup reserved memory for OCRAM DMA\n"); return -ENODEV; } // Map the reserved memory region ocram_dma_base = ioremap(rmem->base, rmem->size); if (!ocram_dma_base) { pr_err("Failed to map OCRAM DMA memory\n"); return -ENOMEM; } copy: memcpy(current_address, mv->A, MATRIX_STRUCT_SIZE);   Re: IMX8MP On chip RAM memory access Hi @Samhitha_Kashyap, Please note that the NXP does not recommend the modification in the node for 448 KB OCRAM Space as it is used by other drivers. One can use memory regions after 0x970000 to Support DMA using the compatible = "shared-dma-pool" property. Thanks & Regards Sanket Parekh Re: IMX8MP On chip RAM memory access Hi @Sanket_Parekh, Thanks for the response, it was helpful!  Would it be possible for me to modify the device tree to support DMA within the 448 KB OCRAM space, if I can't use it for the user application? Thanks & Regards, Samhitha Kashyap Re: IMX8MP On chip RAM memory access Hi @Samhitha_Kashyap , I hope you are doing well.   You can determine how much memory in the OCRAM, Linux kernel Reserved for itself by looking into the dtsi file (reserved memory node) of the soc in the case of imx8mp, it is 448 KB.   resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; ocram: ocram@900000 { no-map; reg = <0 0x900000 0 0x70000>; };   ..... .....   }   So here 0x70000 ( 448K) bytes are reserved for Linux usage. and cannot be virtually mapped to the userspace as specified by the no-map property. after 0x7000 bytes you can use it for other applications. But you need to make sure that any  M7 core Application not using OCRAM. which can be determined by looking into the Linker script of a particular application.   Thanks & Regards Sanket Parekh   Re: IMX8MP On chip RAM memory access Hi Sanket, Would it be possible to verify how much memory the Linux utilizes and the rest can be used for the user application. If it is possible, how could I verify the same and allocate the rest of the memory for my application.  Thanks & Regards, Samhitha Kashyap Re: IMX8MP On chip RAM memory access Hi @Samhitha_Kashyap  I hope you are doing well. To access OCRAM First you need to ensure that you don't try to access the region that is used by ATF. in the case of u-boot, one can use md/mw command to access OCRAM directly. It is not recommended to use OCRAM in userspace as Linux itself uses it. Thanks & Regards Sanket Parekh

Question about RW612 OTBR Thread Certification Architecture Hello NXP Team,   I noticed the Thread Group certified component:   "NXP RW612 Wireless MCU With Integrated Tri-Radio OTBR" (Thread 1.4)   I also found separate certifications for:   - NXP i.MX MPU With IW610 Tri-Radio OTBR - NXP i.MX MPU With IW612 Tri-Radio OTBR - NXP RW612 Wireless MCU With Integrated Tri-Radio OTBR   I would like to better understand the certification architecture used for the RW612 OTBR certification.   Could you please clarify:   1. Was the certification achieved using RW612 as a standalone MCU/RTOS-based Thread Border Router?   2. Was an external RCP/NCP device used in the certified configuration?   3. Which software platform was used during certification (FreeRTOS, Zephyr, or another platform)?   4. Is there any public reference design or documentation describing the certified RW612 OTBR implementation?   Our goal is to understand whether the RW612 OTBR certification represents a standalone MCU-based Thread Border Router solution rather than a Linux-host-based OTBR architecture.   Thank you for your support.   Best regards, Kyonghwan Cho   Re: Question about RW612 OTBR Thread Certification Architecture Hello, Hope you are doing well. My name is Ricardo and I have been assigned this case. A1: Yes. The RW612 OTBR certification is a true standalone, single-chip solution. A2: No. Unlike the i.MX MPU + IW610/IW612 OTBR certifications (which use a Linux host with an external IW6xx radio co-processor in RCP mode), the RW612 certification does not use any external RCP or NCP device. A3: Let me confirm. A4: For specific details on the test configuration, test reports, or certification scope, please contact the Thread Group directly at threadgroup.org. Best Regards, Ricardo Re: Question about RW612 OTBR Thread Certification Architecture Hello @KyonghwanCho , Thank you for your patience. I have the confirmation that the SW platform used was FreeRTOS. Also, please check below OTBR user guide and build guide ot-nxp/examples/br/README-OTBR.md at release/v1.4.0.5_26.03 · NXP/ot-nxp ot-nxp/src/rw/rw612/README.md at release/v1.4.0.5_26.03 · NXP/ot-nxp Best Regards, Ricardo

I need to configure DMA for SPI I am using S32DS IDE and RTD 3.0 can anyone tell me how to start the DMA with SPI with step by step instructions or any other example code if available Re: I need to configure DMA for SPI Thank you for your response Do this work for s32k322 MCU Re: I need to configure DMA for SPI Hi @ershi  Included with the RTDs are provided two example codes for SPI communication using DMA, one using Low-Level Drivers (Ip) and one using High-Level Drivers (MCAL). You can refer to the thread HOWTO: S32 Design Studio - Create a New S32DS Project from Example for guidance on how to import the examples. Also, you can refer to the example provided in the thread Example S32K31 SPI Multiple Packet Transmit & Receive: Solution for DMA Cache Issue. BR, VaneB Re: I need to configure DMA for SPI Hi @ershi  Although the examples are not specifically designed for the S32K322, the functionality is generally the same across the S32K3 family, unless otherwise stated in the Reference Manual Therefore, you can use this project as a reference for your implementation and adapt it as needed for your specific device. Re: I need to configure DMA for SPI I had configurated everything but still it is not working initially it is return as LPSPI_IP_STATUS_SUCCESS  for (Lpspi_Ip_AsyncTransmit )and second time it is showing failed LPSPI_IP_STATUS_FAIL  I can able to send the data through spi using this api without the dma Lpspi_Ip_SyncTransmit() I have attached few configuration screenshot  Re: I need to configure DMA for SPI Hi @ershi  Could you also share images of the RM and IntCtrl_Ip driver configurations? Re: I need to configure DMA for SPI Hi @VaneB  I've attached the screenshots for the RM and IntCtrl_IP driver configurations, along with a short video clip for your detailed reference. I noticed one difference in the LPSPI configuration page. In the SPI General tab, under Spi_Phy_TxDmaChannel, the naming is different between the TX and RX configurations. Please let me know if you need any additional details InterruptsInterruptsInterruptsInterruptsInterruptsInterruptsInterruptsInterruptsInterrupts RMRMRMRMRMRMRMRMRM Re: I need to configure DMA for SPI Hi @ershi  Thank you for sharing all the information. I just have one observation. In the Dma_Ip driver configuration, you have defined DMA_SPI_CALLBACK_0 as the Interrupt Callback. However, the LPSPI DMA callbacks are already provided by the driver and can be found in the Lpspi_Ip_Irq.c file. For LPSPI2, the configured callbacks should be: Lpspi_Ip_LPSPI_2_IrqTxDmaHandler for the TX DMA channel Lpspi_Ip_LPSPI_2_IrqRxDmaHandler for the RX DMA channel Re: I need to configure DMA for SPI Hi @VaneB  Thank you for the clarification. I updated the Dma_Ip configuration so that, for LPSPI2, the TX and RX DMA channels now use the callbacks from Lpspi_Ip_Irq.c: Lpspi_Ip_LPSPI_2_IrqTxDmaHandler for the TX DMA channel Lpspi_Ip_LPSPI_2_IrqRxDmaHandler for the RX DMA channel nxp However, the DMA-based LPSPI transfer is still not working as expected on my side. I have attached a screenshot of the current configuration for your reference. If there are any additional settings, I should adjust please let me know Re: I need to configure DMA for SPI Hi @ershi  Could you please let me know how you are implementing the SPI communication? Also, have you test the code from the example I shared previously? Re: I need to configure DMA for SPI Hi @ershi  Are you connecting the LPSPI2 SOUT signal directly to SIN, or are you using a logic analyzer to verify the transmitted and received data? Re: I need to configure DMA for SPI Hi @VaneB       I have deleted the previous configuration and now the SPI data is transmitting through DMA, but the problem is that the data is not matching  #define RX_MSG_SIZE (15U) #define TX_MSG_SIZE (15U) uint8_t txBuffer_check[TX_MSG_SIZE] = {0x48,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x10,0x11,0x12,0x13,0x14,0x15}; uint8_t rxBuffer_check[]={0};  if(Lpspi_Ip_AsyncTransmit(&Lpspi_Ip_DeviceAttributes_SpiExternalDevice_1_Instance_2_BOARD_InitPeripherals,txBuffer_check,rxBuffer_check,TX_MSG_SIZE,spi_DMA_Function) == LPSPI_IP_STATUS_SUCCESS) { Dma_Ip_ReturnType status = {0},status1 = {0}; Dma_Ip_LogicChannelStatusType channelStatus ={0},channelStatus1 ={0}; status = Dma_Ip_GetLogicChannelStatus(DMA_LOGIC_CH_0,&channelStatus); status1 = Dma_Ip_GetLogicChannelStatus(DMA_LOGIC_CH_1,&channelStatus1);    return SYS_SUCCESS; }   Re: I need to configure DMA for SPI Hi @VaneB, I have rewritten the code and it is working perfectly now. The data is coming in correctly. Thank you for your assistance. Re: I need to configure DMA for SPI Hi @VaneB  In our previous discussion about configuring DMA for SPI. I have noticed the RX buffer data is not matching with the logic analyser data Tx buffer is working perfectly working well. I have added detailed information in the dropbox.

S32K3 ADC Optimize DMA Streaming Hello, When the adc group has only one channel and the Adc Enable Optimize DMA Streaming Groups configuration item is checked, a hard fault occurs when the Adc_Ipw_SetupTcdSingleAdcChannelMajorLink function is executed. In the case of a single channel, if the Adc Group Without Interrupts configuration item is checked and ACCESS_MODE_STREAMING, Select Adc Streaming Dma Channel is enabled. Otherwise, the number of the dma channel in the configuration file is 255, which is reasonable here. But what I don't understand is why when ADC_ENABLE_GROUP_STREAMING_RESULTS_RORDER or ADC_OPTIMIZE_DMA_STREAMING_GROUPS is STD_ON, instead of STD_ON==GroupPtr ->AdcWithoutInterrupt, the Adc_Ipw_SetupTcdSingleAdcChannelMajorLink function will be called. This seems unreasonable, and also because the call to this function leads to hard fault. BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Jason22 Please do not use your QQ email account next time; please use your company email account instead. I tested this, but I didn't find any problems. I have attached my test project and test result for your reference. Also, i check your code and i found some error in your code. 1.clock init is wrong, your code can't not run successfully, 2."adc_group0_val" should be attribute to "no-cacheable area" also: The usage instructions for Optimize DMA streaming groups are clearly explained in the user manual. RTD_ADC_UM.pdf

Error reporting module MCU: S32K148 in 144 pin package RTD version: SW32K1_S32M24x_RTD_4.4_3.0.0_QLP03_D2507 S32 DS Version: 3.6.6 Target OS: Bare Metal Host OS: Windows With the above, I cannot find a module called "ERM" (or anything similar) in the driver module. I have looked in both both MCAL and Non-MCAL modules. Is the ERM supported as a driver module or should the user manipulate raw pointers, as it used to be with the older 'Processor Expert' based framework?

i.MX8MP SError. remote proc starts M7 core and arecord plughw:wm8962audio,0 Hi, On FRDM-i.MX8MP (Linux 6.12.34-lts-next), ALSA capture on wm8962 works fine until the Cortex-M7 is started via remoteproc. After any M7 firmware starts, arecord triggers a kernel panic.   Summary: - Without M7: arecord OK - After starting M7: panic in fsl_sai_runtime_resume → regmap_write (SError 0xbf000002) - Reproduced with BSP stock firmwares: - imx8mp_m7_DDR_hello_world.elf - imx8mp_m7_DDR_rpmsg_lite_str_echo_rtos.elf So this does not look specific to our custom M7 app.   Reproduce: 1) Boot Linux, keep M7 stopped 2) arecord -D plughw:wm8962audio,0 -f S16_LE -r 16000 -c 1 -d 1 /tmp/t.wav → OK 3) echo stop > /sys/class/remoteproc/remoteproc0/state echo imx8mp_m7_DDR_hello_world.elf > /sys/class/remoteproc/remoteproc0/firmware echo start > /sys/class/remoteproc/remoteproc0/state 4) same arecord → Kernel panic (SError)   Panic path (abbreviated): snd_pcm_capture_open → ... → fsl_sai_runtime_resume → regmap_write → SError 0xbf000002   Tried: - Remove optional "audio" (AUDPLL) clock from imx8mp-cm7 DT node → still fails - Disable AudioMIX ownership / Audio PLL init in our M7 clock_config → still fails with stock hello_world anyway   Questions: 1) Is concurrent use of Linux SAI/wm8962 and M7 remoteproc supported on i.MX8MP? 2) Does SDK BOARD_BootClockRUN() mapping AudioMIX to M7 conflict with A53 audio power domain? 3) Any known 6.12 fixes for AudioMIX / fsl_sai runtime resume SError? 4) Recommended clock_config for M7 when audio must remain owned by Linux (UART/RPMsg only on M7)?   Thanks.   ------------------------- imx8mp-cm7 dts node -------------------------- imx8mp-cm7 {         compatible = "fsl,imx8mn-cm7";         rsc-da = <0x55000000>;         clocks = <&clk IMX8MP_CLK_M7_DIV>;              //<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;         clock-names = "core", "uart4";         mbox-names = "tx", "rx", "rxdb";         mboxes = <&mu 0 1               &mu 1 1               &mu 3 1>;         memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>,                 <&m4_reserved>;         status = "okay";         fsl,startup-delay-ms = <500>;     };   ------------------ Panic log ------------------ root@FRDM-test:/lib/firmware# echo imx8mp_m7_DDR_hello_world.elf > /sys/class/remoteproc/remoteproc0/firmware root@FRDM-test:/lib/firmware# echo start > /sys/class/remoteproc/remoteproc0/state root@FRDM-test:/lib/firmware# root@FRDM-test:/lib/firmware# root@FRDM-test:/lib/firmware# root@FRDM-test:/lib/firmware# arecord -D plughw:wm8962audio,0 -f S16_LE -r 16000 -c 1 -d 1 /tmp/t_ex.wav [ 58.448085] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError [ 58.448101] CPU: 0 UID: 0 PID: 644 Comm: arecord Tainted: G C O 6.12.34-lts-next #1 [ 58.448109] Tainted: [C]=CRAP, [O]=OOT_MODULE [ 58.448111] Hardware name: NXP FRDM-IMX8MPLUS (DT) [ 58.448113] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 58.448118] pc : _raw_spin_unlock_irqrestore+0x10/0x50 [ 58.448130] lr : regmap_unlock_spinlock+0x14/0x20 [ 58.448136] sp : ffff8000854e3670 [ 58.448138] x29: ffff8000854e3670 x28: ffff8000854e3c30 x27: 0000000000000001 [ 58.448147] x26: ffff0000d06da088 x25: 0000000000000000 x24: ffff0000d06da390 [ 58.448153] x23: ffff0000d1c18f60 x22: ffff0000d0363c10 x21: 0000000001000000 [ 58.448160] x20: 0000000000000000 x19: ffff0000d14a3000 x18: 0000000000000002 [ 58.448168] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000 [ 58.448174] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 [ 58.448180] x11: 0000000000000000 x10: ffff0000dccabb90 x9 : 0000000000000390 [ 58.448188] x8 : ffff0000dccabbac x7 : ffff8000854e3940 x6 : ffff0000dccabba0 [ 58.448194] x5 : ffff8000808ed440 x4 : 0000000000000008 x3 : ffff8000808ece60 [ 58.448200] x2 : 0000000001000000 x1 : ffff0000dcca5280 x0 : 0000000100000001 [ 58.448208] Kernel panic - not syncing: Asynchronous SError Interrupt [ 58.448211] CPU: 0 UID: 0 PID: 644 Comm: arecord Tainted: G C O 6.12.34-lts-next #1 [ 58.448217] Tainted: [C]=CRAP, [O]=OOT_MODULE [ 58.448221] Hardware name: NXP FRDM-IMX8MPLUS (DT) [ 58.448223] Call trace: [ 58.448225] dump_backtrace.part.0+0xd4/0xe0 [ 58.448234] show_stack+0x18/0x30 [ 58.448240] dump_stack_lvl+0x60/0x80 [ 58.448246] dump_stack+0x18/0x24 [ 58.448251] panic+0x168/0x360 [ 58.448258] add_taint+0x0/0xbc [ 58.448264] arm64_serror_panic+0x64/0x70 [ 58.448269] do_serror+0x3c/0x70 [ 58.448273] el1h_64_error_handler+0x30/0x54 [ 58.448279] el1h_64_error+0x64/0x68 [ 58.448283] _raw_spin_unlock_irqrestore+0x10/0x50 [ 58.448289] regmap_write+0x58/0x80 [ 58.448294] fsl_sai_runtime_resume+0xc4/0x280 [snd_soc_fsl_sai] [ 58.448304] pm_generic_runtime_resume+0x2c/0x44 [ 58.448312] __genpd_runtime_resume+0x30/0x80 [ 58.448318] genpd_runtime_resume+0x130/0x2c4 [ 58.448325] __rpm_callback+0x48/0x1e0 [ 58.448330] rpm_callback+0x68/0x80 [ 58.448334] rpm_resume+0x3bc/0x6a0 [ 58.448340] __pm_runtime_resume+0x50/0x9c [ 58.448344] snd_soc_pcm_component_pm_runtime_get+0x3c/0x138 [ 58.448350] __soc_pcm_open+0x60/0x488 [ 58.448355] soc_pcm_open+0x30/0x58 [ 58.448359] snd_pcm_open_substream+0x594/0x850 [ 58.448364] snd_pcm_open+0x118/0x24c [ 58.448368] snd_pcm_capture_open+0x4c/0x7c [ 58.448372] snd_open+0xa0/0x19c [ 58.448379] chrdev_open+0xb0/0x21c [ 58.448386] do_dentry_open+0x138/0x4c4 [ 58.448392] vfs_open+0x2c/0xf0 [ 58.448397] path_openat+0x6fc/0x1074 [ 58.448403] do_filp_open+0xa0/0x15c [ 58.448407] do_sys_openat2+0xc8/0x100 [ 58.448413] __arm64_sys_openat+0x64/0xc0 [ 58.448420] invoke_syscall+0x48/0x104 [ 58.448427] el0_svc_common.constprop.0+0xc0/0xe0 [ 58.448433] do_el0_svc+0x1c/0x28 [ 58.448438] el0_svc+0x30/0x100 [ 58.448444] el0t_64_sync_handler+0x120/0x12c [ 58.448450] el0t_64_sync+0x190/0x194 [ 58.448458] SMP: stopping secondary CPUs [ 58.448464] Kernel Offset: disabled [ 58.448466] CPU features: 0x00,00000080,00200000,4200420b [ 58.448469] Memory Limit: none [ 58.762124] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---   i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: i.MX8MP SError. remote proc starts M7 core and arecord plughw:wm8962audio,0 Hi @humm  Q1. Yes, but only if the two cannot compete for the same audio resources. Q2. Yes, there will be conflicts. In scenarios where Linux controls the audio, the M7 side must remove the AUDIOMIX mapping and the code related to power-on and SAI PLL initialization, leaving AUDIOMIX entirely to the A53/Linux's audiomix_pd management. Q3. No—because this isn't a bug in the fsl_sai driver, but rather a resource ownership configuration issue. Q4.M7 SDK BOARD_RdcInit() — The most crucial step: Removes the M7 (DID1) allocation for SAI3/SDMA3/I2C3. Remove the allocations of RDC_PDAP_SAI3, RDC_MDA_SDMA3*, RDC_PDAP_SDMA3, and RDC_PDAP_I2C3 to DID1, keeping these resources accessible to A53. B.R Re: i.MX8MP SError. remote proc starts M7 core and arecord plughw:wm8962audio,0 Hi @pengyong_zhang  Thank you very much for your guidance. Following your advice, I updated the RDC configurations to assign SDMA3 to Domain 0 (A53/Linux) and shared SAI3, I2C3, and SDMA3 permissions between Domain 0 and Domain 1. Here is the diff of the RDC changes I applied: -RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 +RDC_MDA RDC_MDA_SDMA3p DID0 0x0 0x0 -RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 +RDC_MDA RDC_MDA_SDMA3b DID0 0x0 0x0 -RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 +RDC_MDA RDC_MDA_SDMA3_SPBA2 DID0 0x0 0x0 -RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 +RDC_PDAP RDC_PDAP_SAI3 PDAP_D0D1_ACCESS 0x0 0x0 -RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0 +RDC_PDAP RDC_PDAP_SDMA3 PDAP_D0D1_ACCESS 0x0 0x0 -RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0 +RDC_PDAP RDC_PDAP_I2C3 PDAP_D0D1_ACCESS 0x0 0x0 After applying these changes, arecord works on Linux without triggering any SError, even while the M7 core is running its RTOS firmware. Thanks again for your help!

RW612 FLEXCOMM3/I2S3 Supporting driver We are using RW612 FLEXCOMM3/I2S3 with the following fixed hardware wiring: - GPIO24 = I2S DATA input from PCM6120 SDOUT - GPIO25 = I2S SCK output to PCM6120 BCLK - GPIO26 = I2S WS output to PCM6120 FSYNC The codec is PCM6120 in slave mode. RW612 is intended to be the I2S master generating BCLK/WS and receiving audio data. What we have verified: - GPIO25/GPIO26 can be driven correctly in plain GPIO mode - FLEXCOMM3 clock source is AUDIO PLL at 12.288 MHz - I2C communication with PCM6120 is working - PCM6120 register configuration is accepted Observed behavior: 1. FLEXCOMM3 configured as I2S RX with kI2S_MasterSlaveNormalMaster does not generate any SCK/WS edges on GPIO25/GPIO26. 2. FLEXCOMM3 configured as I2S TX with kI2S_MasterSlaveNormalMaster also does not work: FIFOSTAT.TXNOTFULL=1, but TXLVL remains 0 after writes to FIFOWR, and no SCK/WS edges appear on the pins. 3. PCM6120 reports missing clocks (ASI_STS=0xFF, DEV_STS1=0x80). Questions: 1. Is RW612 FLEXCOMM I2S RX in Normal Master mode expected to drive SCK/WS onto external pins? 2. Is a single FLEXCOMM instance supported for the use case “master clock generation + receive data from external codec”, or is a dual-FLEXCOMM architecture (TX master + RX slave with I2S bridge) required? 3. For FLEXCOMM3 I2S TX master, are there additional prerequisites for FIFO writes to be accepted beyond I2S_TxInit(), FIFOWR writes, and MAINENABLE? 4. Is there any known limitation specific to FLEXCOMM3 on GPIO24/25/26 (AON domain) for I2S clock output? Pls help about the topic Re: RW612 FLEXCOMM3/I2S3 Supporting driver Hi @duyhung, hope you are doing well. Would you please clarify if you are using FreeRTOS or Zephyr to perform the tests? Are you using the FRDM-RW612 board? Please also provide which version (either SDK or Zephyr) you are using, and if you're taking an example as base for your development. Additionally, the Reference Manual of RW612 (UM11865) includes a basic configuration guide for I2S peripheral in section 28.2, would you please confirm if you have followed this general steps? Re: RW612 FLEXCOMM3/I2S3 Supporting driver Hi @RomanVR , Thank you for your response. Please find the clarifications below. 1. RTOS We are using bare-metal and FreeRTOS for both test. No Zephyr is involved in these tests. All initialization and I2S configuration are done directly with the NXP SDK drivers. 2. Board We are not using the FRDM-RW612. We are using a custom Dev Board based on RW612ETA2I. The MCU is the same, but the board layout differs. The audio codec (PCM6120) is wired to FLEXCOMM3 / I2S3 on the following fixed pins: Signal GPIO Direction I2S DATA (SDOUT from PCM6120) GPIO24 Input I2S SCK (BCLK to PCM6120) GPIO25 Output I2S WS (FSYNC to PCM6120) GPIO26 Output I2C SDA (PCM6120 config) GPIO56 (FC14) Bidirectional I2C SCL (PCM6120 config) GPIO57 (FC14) Bidirectional AUX_EN (PCM6120 power) GPIO54 Output 3. SDK Version We are using SDK_2.x_RD-RW612-BGA, version 25.03.00. 4. Base Example We used rdrw612bga_i2s_dma_record_playback as the reference example. That example uses FLEXCOMM1 (TX master) + FLEXCOMM0 (RX slave) + I2S bridge, which we confirmed is working. However, our hardware constraint forces us to use a single FLEXCOMM (FC3 only) for the entire I2S link to PCM6120. PCM6120 must work in Slave mode because we dont have External clock to source for BCLK . We attempted to configure FC3 as kI2S_MasterSlaveNormalMaster to have it generate SCK/WS while receiving data. 5. UM11865 Section 28.2 – I2S Configuration Steps We have reviewed UM11865 Section 28.2 and can confirm all 6 configuration steps are followed: Step 1: Flexcomm enabled with CLOCK_EnableClock + RESET + CLOCK_AttachClk Step 2: FIFO configured (FIFOCFG=0x35, ENABLETX=1, SIZE=8) Step 3: I2S pins set via IO_MUX_SetPinMux(IO_MUX_FC3_I2S), AON MCI_IOMUX enabled Step 4: Rate configured (CFG1 MSTSLVCFG=0b11=NormalMaster, DIV=3 → BCLK=3.072MHz) Step 6: DMA enabled in FIFOCFG Despite following all steps, we observe: - No SCK/WS edges on GPIO25/GPIO26 - TX FIFO not accepting data: TXNOTFULL=1 but TXLVL stays 0 after FIFOWR writes Section 28.2 Step 4 states "For controller operation, the clock determines the I2S rate" but does not specify whether PERSEL=I2S_RECEIVE with NormalMaster is expected to drive SCK/WS onto the pads. Can you clarify: 1. Is PERSEL=I2S_RECEIVE (0b101) capable of driving SCK/WS as outputs when MSTSLVCFG=NormalMaster? 2. Why does TXLVL remain 0 after writes to FIFOWR with PERSEL=I2S_TRANSMIT? Is MAINENABLE required before FIFOWR writes are accepted? 6. Observed Issue – Our Specific Question After all configuration above, GPIO25 and GPIO26 produce zero edges. PCM6120 reports missing clocks (ASI_STS = 0xFF, DEV_STS1 = 0x80). We further ran a diagnostic: we configured FC3 as I2S TX master (instead of RX master) and found that writes to FIFOWR do not increment TXLVL — FIFOSTAT stays at 0x30 (TXNOTFULL=1, TXLVL=0) regardless of how many words we write. Relevant register state after TX master probe:   CFG1 = 0x17003C (MSTSLVCFG=3 = NormalMaster, DATALEN=24, MAINENABLE=0) DIV = 3 (divider=4, BCLK = 12.288MHz / 4 = 3.072MHz) FIFOCFG = 0x35 (ENABLETX=1, TXI2SE0=1) FIFOSTAT = 0x30 (TXNOTFULL=1, TXLVL=0 after writes) After MAINENABLE=1: STAT = 0x5 (BUSY=1, LR=1 — clock logic running internally) SCK/WS edges on GPIO25/GPIO26: 0 Our specific question to NXP: When FLEXCOMM3 I2S is configured as kI2S_MasterSlaveNormalMaster (either TX or RX), is it expected behavior on RW612 that SCK/WS are not driven onto GPIO25/GPIO26 (AON domain), even though STAT shows the peripheral is internally running? Alternatively: Is a single-FLEXCOMM topology (one FC as both clock master and RX data receiver) supported by the RW612 I2S hardware, or does RW612 always require two separate FlexComm instances (one TX master + one RX slave via I2S bridge) for this use case? Thank you. Re: RW612 FLEXCOMM3/I2S3 Supporting driver Hi @duyhung, thanks for providing additional details of your setup. Based on the reference manual (RM00278), when the I2S instance is configured in normal master mode, the SCK and WS signals are configured to be generated but not to transmit or receive data, as it is detailed in section 31.1.2 of the RM00278 in CFG1[MSTSLVCFG] register. In the I2S driver, this configuration is applied within the "I2S_TxInit();" function, which also configures the Flexcomm instance being used and the FIFO as a transmitter instance. Given the previous information, the double Flexcomm topology with shared signals (as it is done in the example you have already tested) is suggested, as it is demonstrated in a similar example shown in Figure 9 in section 3.6.2.1.1 of UM11865. Additionally, if you are taking as base the I2S with DMA playback example, would you please share the modifications you have done to the example?

Will multiple Ara240's support P2P communication? Subject says everything. Can you connect multiple Ara240's through an appropriate PCIe switch and use P2P communication to run larger models? Re: Will multiple Ara240's support P2P communication? The online resource for ARA24 is quite limited but it would be helpful with BAR2 content

S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi, I'm using S32 Design Studio 3.4 with the S32K1xx SDK RTM 4.0.1 for the S32K142. I'm facing an issue where the .mex file and ConfigTools (Pins/Clocks/Peripherals) no longer open. What happens: Double-clicking the .mex file does nothing. ConfigTools → Pins also does nothing. Once, the .mex editor opened correctly and I could see the Pins view, chip package, and peripherals, but after clicking OK, it never opened again. This happens even in a new workspace   I have already tried: Creating a new workspace. Importing the project again. Updating the S32 Design Studio Platform Tools package. Selecting S32 Configuration Tools as the editor for .mex. Restarting S32DS. The project builds correctly, but the Configuration Tools editor never opens. Has anyone seen this issue before? Is this caused by an SDK installation problem, corrupted Config Tools, or a workspace issue? Any suggestions would be appreciated. Eclipse IDE Usage and Settings SDKs Re: S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi @VaneB, Thank you for your reply. I installed S32K1xx SDK RTM 4.0.3 in S32 Design Studio 3.4 and created a new Hello project using the 4.0.3 SDK (not an imported project). The project builds correctly, but the .mex file still does not open in the Configuration Tools editor. When I double-click the .mex file, I can select S32 Configuration Tools as the editor, but after clicking OK, nothing happens. I also verified that the Configuration Tools plugins (Pins Tool, Clocks Tool, Peripherals Tool, Framework, etc.) are installed. Could you please advise what else I should check? Is there a known issue with the Configuration Tools editor not opening in S32DS 3.4? Thank you. Re: S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi @Resham_Bhattad  Please note that S32K1xx SDK RTM 4.0.1 is not compatible with S32DS 3.4. For IDE version, the supported SDK versions are S32K1xx SDK RTM 4.0.2 and 4.0.3. Based on the error, it looks like the IDE cannot find the SDK path. This can happen if the SDK is not installed, the project was imported, or the SDK location configured in the project does not match the SDK installed on your machine. BR, VaneB Re: S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi @Resham_Bhattad  If you access any of the ConfigTools tools, are you able to see and select the project you created from the drop-down list?

S32K312 Secureboot Authentication When changing to a different FBL while Secureboot is enabled, the META Data values ​​generated via the HMAC Key change. As the FBL is changed, the HSE needs to recalculate the META Data using the HMAC Key; however, because the HMAC Key is deleted due to the new FBL, recalculating the META Data becomes impossible. Consequently, a reset occurs due to a verification failure at the FBL, making it impossible to launch the application. Is there a way to re-authenticate the changed FBL using the HMAC Key, thereby allowing both the FBL and the application to run normally?  When running the HSE_SRV_ID_SMR_ENTRY_INSTALL service, HseResponse returns 0xA5AA5317. This corresponds to the following definition: #define HSE_SRV_RSP_KEY_EMPTY ((hseSrvResponse_t)0xA5AA5317UL) This indicates that the key is empty. (As I asked previously, I suspect this response appears because that region has been erased.) I have checked the smrEntry values. When I set a breakpoint at the point where SecureBootState is 0, I confirmed that smrEntry was entirely 0. When I set a breakpoint at the return point where Fota_S32k3_SecureBootProcess ends, I confirmed that the values appeared. At the time of return, the SecureBootState value was 1. I would greatly appreciate it if you could guide me on how to inject the key or otherwise resolve this issue. 1) When a breakpoint is set at if(SecureBootState == 0) / Result: smrEntry = 0 2) A breakpoint at return secureBootProcessResult, the last part of the Fota_S32k3_SecureBootProcess function Re: S32K312 Secureboot Authentication All cryptographic keys declared within the NVM and RAM key catalogs, except for the key type HSE_KEY_TYPE_SHE, can be provisioned (i.e. initialized and updated) by the host via a key import service, defined by the structure hseImportKeySrv_t. The SHE keys is provisioned by the host via services hseSheLoadKeySrv_t or hseSheLoadPlainKeySrv_t.The keys can be installed in plain or encrypted text as shown in the above figure, in the demo all keys are installed in plain text. Do you try the reference code about S32K344_Update_NVM_keys_related_test at \S32K3_HSE_DemoExamples\? # Update NVM keys. ## 1. Objective The main purpose of this example is to a import symmetric key and AES GMAC generate keys. ## 2. Procedure The steps followed to achieve this are: 1. Format Key Catalogs. 2. Declare the HMAC key info that will update initial version. 3. Declare a key container. 4. Copy the key info to the key container. 5. Copy the key data in the container. 6. *You can add any other data to the container*. 7. Import in RAM a copy of the AES provision key to sign the container using the HSE. 8. Sign the container and generate GMAC ## 3. Hardware This example requires the following hardware in order to properly execute: - S32K344-EVB or S32K344-CVB. - If using S32K344-CVB, then an external debugger is also required (PEmicro Multilink rev. C). Re: S32K312 Secureboot Authentication Hi @jeongwoo  It seems that the primary issue currently blocking further progress is that we do not know whether the HMAC key is still available. As a first step, could you please confirm whether you have performed the check I suggested previously and what the result was? “To confirm if the key is erased or not, you can use service HSE_SRV_ID_GET_KEY_INFO, structure struct hseGetKeyInfoSrv_t. Using this service, you will get information in hseKeyInfo_t, so you can check the state of key.” Once we have confirmed the state of the key, we can proceed with the next steps. If the key is missing or has been erased, we can try to install it again. Alternatively, you could also attempt to install the key directly using the same procedure that was originally used during provisioning and see whether the operation succeeds. Regards, Lukas Re: S32K312 Secureboot Authentication A key can be imported or update by HSE service HSE_SRV_ID_IMPORT_KEY. Take a look at these tables in HSE Firmware reference manual rev. 2.7: Table 47. Key provisioning usage when importing a key in an empty slot in the NVM key catalog Table 48. Key provisioning usage when updating  a key (non-empty slot) in the NVM Key Catalog This explains when a key can be imported in plain and when authentication and encryption is needed. If a key slot is empty and you have SU rights, a key can be imported in plain without authentication. If a key slot is not empty (you are updating a key) and you have SU rights, authentication is mandatory and encryption is optional. With user rights only, authentication and encryption is always mandatory regardless of fact that a slot is empty or not. S32K344_Update_NVM_keys_related_test example only shows, how to prepare and sign a key container which is needed for authenticated key import. But the key is not imported in this example. Import of a key is shown in S32K344_AES_EncryptDecrypt, for example. Used API for AES key is LoadAesKey in this project. For HMAC, there’s LoadHmacKey API. This can be used for import of HMAC key in plain without authentication or encryption.

FRDM-MX95 PRO software packages? I was wondering what OS software packages will be available for the MX95 PRO?  Will Android AAOS be available for it as a demo image?  Is there anyone we can communicate with about what will specifically be available? Re: FRDM-MX95 PRO software packages? currently, only linux 6.18.20_2.0.0 demo images for imx95 frdm pro Embedded Linux for i.MX Applications Processors | NXP Semiconductors you can download demo images from the link above, for android, I checked the board file, the latest android 16.0.0_2.0.0 is based on kernel 6.18.20_2.0.0, so should support frdm pro, but this version android hasn't verified on this board yet, only 19x19 evk and 15x15 frdm Re: FRDM-MX95 PRO software packages? Any news if we will get android automotive on the frdm-mx95 or would we have to upgrade to frdm-mx95 pro version? Re: FRDM-MX95 PRO software packages? let me confirm auto android team again, the owner is on vacation, and come back office in next week, any update I will let you know it Re: FRDM-MX95 PRO software packages? refer to the link as below https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/android-automotive-os-for-i-mx-applications-processors:ANDROID-AUTO auto android demo images are only for imx95 19x19 evk Re: FRDM-MX95 PRO software packages? Are there any plans for android or AAOS?  Seems weird that the FRDM MX95 Pro wouldn't have an AAOS version especially since the Evaluation board 19x19 has been discontinued and benched.  Is there a reason the pro being a 19x19 processor wouldn't work as the evaluation board. Re: FRDM-MX95 PRO software packages? Thanks. There seems to be a genuine lack of Android automotive support. The frdm has a lot of potential but without additional support from nxp we are left on our own. From my understanding the evk has been dropped from support from toradex and discontinued. With the frdm pro having the same hardware there should be some support. We need the BSP which would make building the images a lot easier.