Connects - Training Material

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As IC geometries continue to shrink and switching speeds increase, designing electromagnetic systems and printed circuit boards to meet the required signal integrity and EMC specifications has become even more challenging. A new design methodology is required. Specifically, the utilization of an electromagnetic physics-based design methodology to control the field energy in your design will be discussed. This training module will walk through the development process and provide you with guidelines for building successful, cost effective printed circuit boards.

The session will provide an overview of the AUTOSAR software for NXP Ethernet products. It will describe the software products, starting from the AUTOSAR standard requirements, but also the extensions implemented to leverage the hardware capabilities of our products. It will also point out the advantages of using the AUTOSAR Switch and Transceiver drivers, from integration with NXP or 3rd party microcontrollers to application use-case diversity and leveraging the software ecosystem and quality requirements set by the automotive industry standards.

NXP’s latest i.MX 8M processors require the latest memories to keep them running efficiently. As a system designer, your memory choices can impact the performance, size, cost, power reliability and longevity of your end product. We will discuss the latest memories supported on the new i.MX 8M processor family. This includes DDR3, DDR4 and LPDDR4. We will show designers how they can prioritize performance, power or price to develop the most optimum system. We will also provide details on eMMC 5.1 storage products. This includes high performance features including command queueing, and several new Cache operations. We will also highlight a new MCP that includes LPDDR4 and eMMC in a single space saving package. This session will provide designers with the tools necessary to create state-of-the-art i.MX 8M systems.

i.MX RT has a flexible external SPI Flash interface, which supports all existing SPI protocols. However, Serial Flash products may vary in READ performance due to the number of I/O, command protocols and the maximum frequency. Serial Flash Read performance has a direct impact on the system bootup time as well as code execution efficiency. In an advanced system design where system code is shadowed from Flash to DRAM, the initial boot time depends on the data transfer time from Flash to DRAM. In a cost-efficient system design, DRAM is reduced or eliminated since the processor will be able to fetch execution instructions directly from the Flash to the internal cache. During code fetching, a fixed length of data (typically 32- or 64-Byte) is read out from the flash. Shortening the overall 32-Byte or 64-Byte Read time will greatly reduce processor’s wait cycle, leading to improvement on XiP efficiency.

Join this session to understand the breakthrough security features integrated in the recently launched LPC5500 MCU Family. Along with Arm® TrustZone technology the LPC5500 SRAM PUF based key management makes security easy to use and easy to deploy. This session will start off by introducing the scope of securing a smart connected device. It will explain the need for addressing device life cycle in a scalable way that is easy to use and easy to deploy. Then it will detail the protected key management achievable when using LPC5500 with MCUXpresso Software & Tools.

Hands-on workshop using the low cost KIT-HGDRONEK66 HoverGames drone reference platform for small autonomous vehicles. Learn about the open source PX4 flight stack vehicle manangement unit, NuttX RTOS, Mavlink, DDS RTPS services, associated Linux companion computer and Qgroundcontrol groundstation for vehicle configuration and flight logging and planning. Learn by example compiling the code and adding new functions within the PX4 modular software framework. Discover interfacing to Rapid-IOT via MAVLINK.

Connects - Training Material

Connects - Training Material

Training Sessions Material

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