Issue: During DDR3 Burst Write, the DQS strobe signal must be driven low for a minimum of 0.3 x cycle period on the last data clock cycle before it is released. This ensures sufficient time for the write to be strobed correctly. When measuring this timing parameter, it has often been found to be too short. This may be contributing to write errors on customer boards, depending on the signal layout used by the board. Root Cause: The internal DQS strobe enable signal is controlled by the MMDC, which is tied to the SDCLK clock signal. But the DQS strobe signal can be delayed in the MMDC to match different SDCLK trace lengths by using Write Leveling parameters to ensure the the DQS strobe edge reaches the DDR3 device at the same time the SDCLK edges reaches the device. If the write level delay is too long, the MMDC can crop the end of the DQS strobe signal too short, causing a violation of the Write Post Amble Delay timing specification and potentially leading to  write errors. How much delay in the Write Leveling parameter would cause this problem? The Reference Manual states that a delay around half a cycle may cause problems, but testing on some boards indicates that delays even as short as 1/4 a cycle could cause violations of the Write Post Amble Delay. Solution: The MMDC was designed with the ability to add extra time to the strobe enable period during write procedures. This parameter is referred to as Write Additional Latency. It is found in the MMDCx_MDMISC register and the field is labeled as WALAT. Incrementing the value of this register field by one adds a full clock cycle delay to the Write Post Amble period, and ensures enough time at the end of a burst write to guarantee a correct write. There is no maximum value to Write Post Amble Delay. Setting WALAT = 1 (or larger if WL parameters are larger) will cause a small hit in overall performance, but will add to the reliability of write operations, particularly on boards that require larger WL parameter settings.

Structures to be modified The main table that needs to be modified is in C:\WINCE600\PLATFORM\COMMON\SRC\SOC\COMMON_FSL_V2_PDK1_9\NAND\INC\NANDTYPES.h. Add the Nand specific information to the following structure. typedef struct _NandChipInfo { FlashInfo fi; //@<<info> FlashInfo structure BYTE NANDCode[NANDID_LENGTH];//@<<info> NAND full ID BYTE NumBlockCycles; //@<<info> flash erase address cycle BYTE ChipAddrCycleNum; //@<<info> flash access address cycle BYTE DataWidth; //@<<info> 8/16 bits data width BYTE BBMarkNum; //@<<info> MAX_MARK_NUM = 4 BYTE BBMarkPage[MAX_MARK_NUM];//@<<info> MAX_MARK_NUM = 4 BYTE StatusBusyBit; //@<<info> interleave mode support BYTE StatusErrorBit; //@<<info> interleave mode support WORD SpareDataLength; //@<<info> spare area size BYTE CmdReadStatus; //@<<command> read status BYTE CmdRead1; //@<<command> read first 256 bytes data BYTE CmdRead2; //@<<command> read last 256 bytes data BYTE CmdReadId; //@<<command> read device ID BYTE CmdReset; //@<<command> reset nand flash BYTE CmdWrite1; //@<<command> sequence data input BYTE CmdWrite2; //@<<command> page program BYTE CmdErase1; //@<<command> block erase BYTE CmdErase2; //@<<command> block erase NANDTiming timings; //@<<info> NAND timing parameters }NandChipInfo, *pNandChipInfo; All information from NANDCode to CmdErase2, can be obtained from the Nand Datasheet. The structure FlashInfo, is filled in with data obtained from the Nand Analysis sheet. Please check this link to see how to create this spreadsheet from Nand Datasheets. typedef struct _FlashInfo { FLASH_TYPE flashType; DWORD dwNumBlocks; DWORD dwBytesPerBlock; WORD wSectorsPerBlock; WORD wDataBytesPerSector; }FlashInfo, *PFlashInfo; In the similar way the Nand timings calculated from the spreadsheet are add into this structure. typedef struct _NANDTiming { BYTE DataSetup; BYTE DataHold; BYTE AddressSetup; BYTE DataSample; }NANDTiming, *PNANDTiming; Remember to do a clean sysgen and build.

i.MX 51 EVK Board Bootloader i.MX 51 EVK Board Flashing i.MX 51 EVK U-boot i.MX 51 EVK Compiling U-boot i.MX 51 EVK Changing Env Linux i.MX 51 Flashing Linux Application Only with SD Card Reader Multimedia i.MX 51 EVK Board USB Camera i.MX 51 EVK Board OpenCV Android All Board Android Without Ramdisk All Board install TTS Library Manually i.MX 51 Android ADB over USB Ubuntu i.MX 51 Ubuntu USB TS i.MX 51 Ubuntu TS Lucid

Atlas PMIC i.MX Platforms uses Freescale Atlas chipset as power management IC (PMIC). PMIC is connected with i.MX processor through SPI port. Reading and Changing PMIC Registers pmic_reg is a simple program that allows to read and change PMIC registers through SPI. Click here to download the binary Click here to download the source package Click here to download the spec file pmic_reg Installation To use pmic_reg, you can simply download the binary file and move it to your system. To build the source code, download and mv the source package (in this case "pmic_reg-1.0.tar.gz") to /opt/freescale/pkgs: sudo mv pmic_reg-1.0.tar.gz /opt/freescale/pkgs Download the spec file to spec directory: mkdir <ltib directory>/dist/lfs-5.1/pmic_reg cp pmic_reg.spec <ltib directory>/dist/lfs-5.1/pmic_reg On <ltib directory>, extract, build and deploy pmic_reg: ./ltib -p pmic_reg.spec -m prep ./ltib -p pmic_reg.spec -m scbuild ./ltib -p pmic_reg.spec -m scdeploy Source files will be located at <ltib directory>/rpm/BUILD/pmic_reg-1.0 and binary will be located at /usr/bin on your i.MX system rootfs. pmic_reg Usage To get pmic_reg help, just type pmic_reg: PMIC_REG v1.0 (2009.12.15) Usage To read all PMIC registers: pmic_reg r To write to a specific register: pmic_reg w <register address> <register value>

Features Additional Information Detailed Features List of i.MX31ADS board This is a development tool which is designed to run software applications designed for i.MX31 (MCIMX31) microprocessor unit (MPU). The MCIMX31ADS includes a baseboard, a CPU board, a power management board, an LCD display panel, a keypad, a NAND Flash card, an image sensor, etc. It supports application software, target-board debugging, or optional extra memory. Features Three board system Base board with display and interface connectors CPU board with i.MX31 ARM-11 MCU Power management board with MC13783 Atlas chip +5.0 VDC, 2.4 A universal power supply QVGA LCD display panel with touchscreen capability and LED backlight Keypad with 64 push button keys Image sensor camera Configurable intelligent management of system power Separate selectable voltage regulators for running the CPU board in stand-alone mode Two selectable system clock sources, 32.768 kHz and 26 MHz Onboard CPLD that manages memory-mapped expansion I/O, interrupts, and general-purpose I/O Multi-ICE debug support 32 MB of 16-bit NOR burst flash memory 16 MB of 16-bit PSRAM 128 MB of 32-bit DDR SDRAM memory Two sets of two memory card connectors, selectable as SD/MMC (on Base board) or MS (on CPU board), with card-sense functionality 1G-bit x8 data NOR Flash on a removable card SIMM card connector PCMCIA connector NAND Flash card connector Three RS-232 interfaces with DB-9 connectors driven by UART channels internal to the MX31. Each interface has two UART options and power up enable DIP switches. One supports DCE with optional full modem controls, another is DTE with optional full modem controls, and the third is DTE with RTS/CTS controls only. An external DUART configured as two RS-232 DCE channels (one DB9 connector, one 10-pin header) Two USB host transceivers, one full-speed and one high-speed, with standard USB host connectors Three USB OTG transceivers, one full-speed and one high-speed on the Base board, one full-speed on the Atlas board, with mini AB connectors 10 Base-T Ethernet controller with RJ-45 connector with built-in data flow LED indicators IrDA Specification 1.4 transceiver supports fast, medium, and slow operating modes ATA5 controller with 44-position dual row, 2 mm header for small form-factor disk drives I2C interface with one of two selectable MCU interfaces CSPI connector Two CSI connectors, with different image sensor orientations Smart serial LCD display connector QVGA LCD display connector with touch screen interface plus companion connector with additional control signals Two smart parallel LCD display connectors TV encoder connector Keypad connector Interface connector to baseband processor Audio synthesizer chip with microphone and line inputs (3.5 mm jacks); line, voice, and headphone outputs (3.5 mm jacks); and speaker output (screw terminals) Eight DIP configuration switches with user-definable functions Software-readable CPU and Base board versions LED indicators for +5V IN, 3.3V, vibrator output, and synthesizer output. Two LED indicators for user-defined function Piezoelectric audible alert and vibratory alert Three RGB funlight indicators and funlight connector Push button Reset (on CPU) or reset control from Atlas 1-wire EPROM • Push button interrupt source Two Mictor LA/SW Analysis Connectors (Base board) Four Samtec LA Connectors (CPU) Three Extension connectors, two are compatible with the MX21 ADS Extension connectors Special Atlas board features Stereo microphone jack, normal microphone jack, external TXIN jack, headphone jack, low level stereo input and output jacks, stereo and mono (ear piece) speaker terminals Main battery emulation from +5V Main battery connection terminals Back up battery emulation (super cap) Coin cell (backup) battery connection terminals Battery charger input terminals Backlight LED indicators Three Push button switches to act as power on/off switches DIP switches to select default power up power and power sequencing. USB mode, USB enable, and WDI disable DIP Switches. Audio clock source selection DIP Switches. Individual test point and LED indicator for each Atlas voltage USB cables, RS-232 serial cable, and two RJ-45 Ethernet cables, network, and crossover Additional Resources Booting Linux From NAND Flash on the i.MX 31 ADS IMX31ADS Compiling Linux kernel mainline

On L4.1.15 BSP, PWM output clock may be not stable, for example, it may switch between 200KHz and 50KHz. PWM clock source is perclk, in running mode, perclk is 24MHz, while in low power idle mode, perclk is reduced to 6MHz, so PWM output clock is reduced to 1/4. To keep PWM output stable clock, we should let perclk stay in 24MHz in low power idle mode. Attached is the patch for 6UL and 6ULL.

If you are a Windows user and don't want to install Linux on your machine, VMware is a virtual machine used to install Linux under Windows. It's a good way to start with Linux (if you're unfamiliar with it) and also start your i.MX development. Installing VMWare - VMWare Workstation [VMWare Workstation (Click here to go to Download page)] VMWare Workstation is available in commercial and trial versions. With Workstation is possible to create your own installation image—installing a new operating system as you would install it in a new machine. - VMWare Player [VMWare Player (Click here to go to Download page)] VMWare Player is available in a free version. With Player is only possible to run images previously made. - VMWare Images at ThoughtPolice site [ThoughtPolice site (Click here to go to Download page)] This site has many ready VMWare images from many Linux distributions. It just needs to be downloaded, unziped and it's ready to be used with VMware. Workstation or Player.

Q: Can OpenGL/OpenVG work on any of our boards with a 16-bit DDR bus? Here is GPU state dump when run some of the GPU SDK tutorials on their imx6 solo board with a 16-bit DDR bus: Mounting rootfs VFS: Mounted root (nfs filesystem) readonly on device 0:12. Freeing init memory: 156K Starting init GPU[0]: ************************** ***   GPU STATE DUMP   *** **************************   axi      = 0x000000B1   idle     = 0x7FFFFF86     FE not idle     SH not idle     PA not idle     SE not idle     RA not idle   DMA appears to be stuck at this address:     0x1882F230   dmaLow   = 0x08010583   dmaHigh  = 0x80003400   dmaState = 0x00000904     command state       = 4 (PAR_ADR1_ST)     command DMA state   = 1 (CMD_START_ST)     command fetch state = 2 (FET_VALID_ST)     DMA request state   = 0 (REQ_IDLE_ST)     cal state           = 0 (CAL_IDLE_ST)     VE request state    = 0 (VER_IDLE_ST)   RA debug registers:     [0x00] 0x0108C378     [0x01] 0x0042FB12     [0x02] 0x0042FB11     [0x03] 0x0000022C     [0x04] 0x10220033     [0x05] 0x0885C800     [0x06] 0xC054CBFE     [0x07] 0x68100000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x12344321     [0x0D] 0x12344321     [0x0E] 0x12344321     [0x0F] 0x12344321     signature = 0x12344321 (1 read attempt(s))   TX debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   FE debug registers:     [0x00] 0x1882F450     [0x01] 0x08010594     [0x02] 0x00000001     [0x03] 0x00000256     [0x04] 0x00080049     [0x05] 0x0000000D     [0x06] 0x00009571     [0x07] 0x00007445     [0x08] 0x00000004     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0xA3105D67     [0x0E] 0x000000D0     [0x0F] 0xBABEF00D     signature = 0xBABEF00D (1 read attempt(s))   PE debug registers:     [0x00] 0x0108C369     [0x01] 0x00000000     [0x02] 0x0108C369     [0x03] 0x00000000     [0x04] 0xA0000000     [0x05] 0xABC00000     [0x06] 0xBC000000     [0x07] 0xCDE00000     [0x08] 0xD04045C0     [0x09] 0x204045C0     [0x0A] 0x0D863084     [0x0B] 0x00000000     [0x0C] 0xBABEF00D     [0x0D] 0xBABEF00D     [0x0E] 0xBABEF00D     [0x0F] 0xBABEF00D     signature = 0xBABEF00D (1 read attempt(s))   DE debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   SH debug registers:     [0x00] 0x0049AB4C     [0x01] 0x0000000B     [0x02] 0x00000411     [0x03] 0x00020A95     [0x04] 0x00000000     [0x05] 0x000F024E     [0x06] 0x000F424C     [0x07] 0x010BEC30     [0x08] 0x0108C368     [0x09] 0x000020DF     [0x0A] 0x00000693     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0xDEADBEEF     signature = 0xDEADBEEF (1 read attempt(s))   PA debug registers:     [0x00] 0x640006FE     [0x01] 0x64000000     [0x02] 0x00000810     [0x03] 0x00000690     [0x04] 0x00000230     [0x05] 0x0000022D     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000003     [0x09] 0x0000AAAA     [0x0A] 0x0000AAAA     [0x0B] 0x0000AAAA     [0x0C] 0x0000AAAA     [0x0D] 0x0000AAAA     [0x0E] 0x0000AAAA     [0x0F] 0x0000AAAA     signature = 0x0000AAAA (1 read attempt(s))   SE debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x00000000     [0x05] 0x00000000     [0x06] 0x00000000     [0x07] 0x00000000     [0x08] 0x00000000     [0x09] 0x00000000     [0x0A] 0x00000000     [0x0B] 0x00000000     [0x0C] 0x00000000     [0x0D] 0x00000000     [0x0E] 0x00000000     [0x0F] 0x00000000     failed to obtain the signature (read 0x00000000).   MC debug registers:     [0x00] 0x00000000     [0x01] 0x00000000     [0x02] 0x00000000     [0x03] 0x00000000     [0x04] 0x12345678     [0x05] 0x12345678     [0x06] 0x12345678     [0x07] 0x12345678     [0x08] 0x12345678     [0x09] 0x12345678     [0x0A] 0x12345678     [0x0B] 0x12345678     [0x0C] 0x12345678     [0x0D] 0x12345678     [0x0E] 0x12345678     [0x0F] 0x12345678     signature = 0x12345678 (1 read attempt(s))   HI debug registers:     [0x00] 0x0000F719     [0x01] 0x19C020C8     [0x02] 0x1EBC2426     [0x03] 0xAAAAAAAA     [0x04] 0xAAAAAAAA     [0x05] 0xAAAAAAAA     [0x06] 0xAAAAAAAA     [0x07] 0xAAAAAAAA     [0x08] 0xAAAAAAAA     [0x09] 0xAAAAAAAA     [0x0A] 0xAAAAAAAA     [0x0B] 0xAAAAAAAA     [0x0C] 0xAAAAAAAA     [0x0D] 0xAAAAAAAA     [0x0E] 0xAAAAAAAA     [0x0F] 0xAAAAAAAA     signature = 0xAAAAAAAA (1 read attempt(s))   Other Registers:     [0x0040] 0x00924A66     [0x0044] 0x06F47370     [0x004C] 0x06F47370     [0x0050] 0x00DE8E6E     [0x0054] 0x00DE8E6E     [0x0058] 0x00924A66     [0x005C] 0x001254D6     [0x0060] 0x001254D6     [0x043C] 0x00000000     [0x0440] 0x00000000     [0x0444] 0x00000000     [0x0414] 0x3C000000 [<8003b21c>] (unwind_backtrace+0x0/0xfc) from [<80308114>] (_DumpGPUState+0x4ec/0x6b4) [<80308114>] (_DumpGPUState+0x4ec/0x6b4) from [<80308324>] (gckOS_Broadcast+0x38/0xe8) [<80308324>] (gckOS_Broadcast+0x38/0xe8) from [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) [<80311008>] (gckEVENT_GetEvent+0x184/0x1b4) from [<80311294>] (gckEVENT_Submit+0x8c/0x328) [<80311294>] (gckEVENT_Submit+0x8c/0x328) from [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) [<8030dedc>] (gckCOMMAND_Commit+0x4d4/0xa28) from [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) [<8030c1d0>] (gckKERNEL_Dispatch+0x4b4/0x112c) from [<80306580>] (drv_ioctl+0x108/0x250) [<80306580>] (drv_ioctl+0x108/0x250) from [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) [<800ed704>] (do_vfs_ioctl+0x80/0x5e0) from [<800edc9c>] (sys_ioctl+0x38/0x60) [<800edc9c>] (sys_ioctl+0x38/0x60) from [<80035580>] (ret_fast_syscall+0x0/0x30) A: This GPU driver stack dump indicates GPU stuck when VDDPU_CAP was under spec values (1.2V) so GPU was not correctly powered. Was fixed by adjusting PMU_REG_CORE[REG1_TARG]. AFAIK, GPU drivers have some DDR bank configuration, so you may see a different problem though.

You can use TV Out on i.MX27ADS board by following these steps: Remove the R71 and solder it on R69 place; See the image before of this process: And after this process: Set SWITCH S15: 1 = on; [2-5] = off. See the image for more details: Add to your Linux command line (in Redboot) the following parameter: video=mxcfb:TV-NTSC After this modification, the video signal will operate at 27MHz, that are applicable just with TV-OUT card. The LCD card will not work at this frequency.

Attached you can find a document that explains how to add Wi-Fi support in the iMX28evk using Yocto.

The lastest iMX28 WinCE 6.0 BSP "WCE600_MX28_SDK1008" has a UART RX DMA data lost issue. Test case to duplicate the issue: Connect iMX28 UART1 and PC with UART cable, then run some UART test application on iMX28 and PC side, PC can send a file to IMX28, file size should bigger than the default RX DMA buffer size 1024 bytes, then from iMX28 side, there will be data lost. The attached "SERIALAPP.zip" is the updated UART driver code to fix this issue, you can unzip and update it to "wince600\platform\common\src\soc\common_fsl_v2_pdk1_9\serialapp" folder, and rebuild the WinCE image. The followed improvement had been implemented in this update for UART RX DMA: 1. Added DMA recover code.     When UART error happens in DMA mode, the driver will re-initialize the DMA for next transfer.. 2. Set UART DMA timeout interrupt to 5ms. "#define SERIAL_DMA_RX_TIMEOUT      5"     After UART DMA interrupt happens, the IST need copy data from DMA buffer to MDD buffer, so it needs time. The default BSP had set this delay to 31 bits transfer time, this is very short, if the PC send "DMA buffer + 1" bytes to iMX28, after first DMA buffer full interrupt happens, the second DMA timeout interrupt will happen in a short time, this interrupt will be lost, because the driver is still processing the pre-interrupt. 3. Updated MDD code to make sure the buffer send to PDD is always bigger than the RX DMA buffer.     This MDD code modification will only active in DMA mode, so there is no impact for PIO mode. 4. Update UART DMA interrupt handler code.     When UART DMA interrupt happens, set up the next DMA transfer at once, so DMA can continue to receive data with another DMA buffer, the same time the IST will copy data from pre-DMA buffer to MDD buffer.

Ramdisk is unnecessary thing for some embedded systems, but it's required for Android . You can develop an Android system with no ramdisk (initrd/initramfs), just follow these steps: 1) Remove RAMDISK support from kernel: General setup  --->             [ ] Initial RAM filesystem and RAM disk (initramfs/initrd) support Create a single rootfs: cd myandroid/out/target/product/imx51_BBG mkdir rootfs sudo cp -a system rootfs/ sudo cp -a root/* rootfs/ sudo cp -a recovery rootfs/ Since you are using a single filesystem, then comment out these lines from rootfs/init.rc: #mount ext3 /dev/block/mmcblk0p2 /system #mount ext3 /dev/block/mmcblk0p2 /system ro remount #mount ext3 /dev/block/mmcblk0p5 /data nosuid nodev #mount ext3 /dev/block/mmcblk0p6 /cache nosuid nodev Create just one partition into your MMC or Flash memory: Partition 1: 200MB+ as EXT3 will be used as system(rootfs). Remember to skip 4MB to save kernel. It is a good idea to create a second partition (VFAT) to mount as /data to save user files. Mount that "system" partition and copy all content of rootfs: sudo mount /dev/sdb1 -t ext3 /mnt sudo cp -a .../target/product/imx51_BBG/rootfs/* /mnt sudo umount /mnt Now just setup your bootloader parameter correctly (i.e. MMC Partition 1): setenv bootargs_base 'setenv bootargs root=/dev/mmcblk0p1 rootfstype=ext3 console=ttymxc0,115200 noinitrd'

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343777 

The i.MX6 DL/S L3.035_3.0.4 patch release is now available onwww.freescale.com ·         Files available # Name Description 1 L3.0.35_3.0.4_TEMP_PATCH This patch release is based on the i.MX 6DualLite/6Solo   Linux L3.0.35_3.0.0 release. The purpose of this patch release is fix the   miscalibration issue for the thermal sensor.

Question: 1)      Is WDOG2 somehow accessible from customers code in normal mode? Is it only used within the trust zone to protect against DOS attacks from normal world?) 2)      Is there any mechanism preventing changing of the watchdog registers like being able to write them only during a period after Reset? If yes, which registers are protected? Answer: WDOG1 and WDOG2 are identical the only difference is how the signals are connected. There is nothing presenting someone from using both WDOGs for non-secure purposes. There is no time window for WDOG access but there are some write-once only bits in the register, which can be written only once after reset, after that all following writes will be ignored. They are clearly described in the RM. The bits are: WDZST, WDBG, WDW, WDE, WDT, WIE, WICT, and PDE.

Network File System (NFS) Setting the Host 1 - Install NFS Service on host typing: $sudo apt-get install nfs-kernel-server 2 - Create symbolic link to ltib/rootfs $sudo ln -s <ltib instalation folder>/rootfs /tftpboot/rootfs 3 - Setup exports typing: $sudo gedit /etc/exports and add the following line: /tftpboot/rootfs/ *(rw,no_root_squash,no_subtree_check,async) 4 - Restart the NFS server: $sudo /etc/init.d/nfs-kernel-server restart Now the host is ready to use NFS. Setting Target Linux Image to use NFS 1 - Run LTIB configuration typing: $cd <ltib instalation folder> $./ltib -c 2 - On first page menu, go to "Target Image Generation -> Options" as in the picture below. 3 - Select the option NFS only and exit LTIB configuration to compile with the new configuration. 4 - LTIB should start new compiling and create a new Linux image on /<ltib instalation folder>/rootfs/boot/zImage 5 - Copy the created image on /<ltib instalation folder>/rootfs/boot/zImage to /tftpboot/zImage 6 - The system is ready to run with NFS. The root file system on target will be located on host on /<ltib instalation folder>/rootfs/

ltib 编译的 解码插件包，官网比较难找到的。

Attached is a chunk of the Filesystem needed to construct the Linux Image https://community.freescale.com/docs/DOC-93887

[中文翻译版] 见附件   原文链接： eIQ Machine Learning Software for i.MX Linux 4.14.y