Q: Does anyone have the Lauterbach script files for connecting to the mx53?  Also,  does anyone know of a converter to convert RealView scripts to Lauterbach? A: Please see below attach.cmm and load_simbols.cmm for i.MX53. attach.cmm ; ; Script to attach to a running system, halt the CPU, ; and display the ASM code ; screen.on ; Debugger Reset winpage.reset area.reset WINPOS 0. 26. 75. 8. 0. 0. W000 area print "resetting ICD..." System.Down Break.Delete MAP.RESet TASK.RESet sYmbol.RESet Data.PROLOG.RESet Data.EPILOG.RESet sYmbol.AutoLoad.CHECK OFF      ; disable dynamic autoloader sYmbol.AutoLoad.RESet          ; reset autoloader list MMU.RESet ; setup of ICD JTAG print "initializing JTAG..." SYStem.CPU CORTEXA8 SYStem.MultiCore IRPOST 0x0 SYStem.MultiCore IRPRE 0x0 SYStem.MultiCore DRPOST 0x0 SYStem.MultiCore DRPRE 0x0 SYStem.MultiCore DAPIRPOST 0x09 SYStem.MultiCore DAPIRPRE 0x0 SYStem.MultiCore DAPDRPOST 0x02 SYStem.MultiCore DAPDRPRE 0x0 SYStem.MultiCore MEMORYACCESSPORT 0 SYStem.MultiCore DEBUGACCESSPORT 1 SYStem.MultiCore COREBASE APB:0xC0008000 SYStem.Option DACR ON          ; give Debugger global write permissions TrOnchip.Set DABORT OFF        ; used by Linux OS for page miss! TrOnchip.Set PABORT OFF        ; used by Linux OS for page miss! TrOnchip.Set UNDEF OFF         ; let UNDEF be handled by Linux OS SYStem.Option MMU ON           ; enable space ids to virtual addresses SYStem.JtagClock 20.0MHz SETUP.IMASKASM ON              ; lock interrupts while single stepping ; Use on-chip breakpoints Break.SELect PROGRAM ONCHIP Break.SELect READ ONCHIP Break.SELect WRITE ONCHIP Break.SELect ALPHA ONCHIP Break.SELect BETA ONCHIP Break.SELect CHARLY ONCHIP Break.SELect DELTA ONCHIP Break.SELect ECHO ONCHIP SYStem.Option EnReset OFF SYS.m attach ; wait until reset is complete wait 2.s if run()     Break ; Open a Code Window -- we like to see something WINPOS 0. 0. 75. 20. Data.List enddo load.symbols.cmm ; ; Script to load the Linux kernel symbols into the debugger ; print "loading Linux kernel symbols..." &linuxpath="S:\git\kernel\linux-2.6-imx-0" &kbuildpath="build" sYmbol.SourcePATH.SET &linuxpath Data.LOAD.Elf &linuxpath\&kbuildpath\imx5\vmlinux /StripPART 3 /gnu /nocode ; Map the virtual kernel symbols to physical addresses ; to give the debugger access to it before CPU MMU is ; initialized print "setting system MMU..." MMU.FORMAT Linux swapper_pg_dir 0xc0000000--0xc1ffffff 0x70000000 MMU.Create 0xc0000000--0xc1ffffff 0x70000000 ; map kernel pages at RAM start MMU.COMMON 0xc0000000--0xffffffff            ; common area for kernel and processes ;MMU.TableWalk OFF   ; debugger uses a table walk to decode virtual addresses MMU.ON             ; switch on debugger(!) address translation ; Initialize Mutitasking Support print "initializing multitask support..." TASK.CONFIG ../linux       ; loads Linux awareness (linux.t32) MENU.ReProgram ../linux    ; loads Linux menu (linux.men) HELP.FILTER.Add rtoslinux  ; add linux awareness manual to help filter enddo This document was generated from the following discussion: Lauterbach CMM scripts for mx53

Why raising QoS priority for EPDC Eink has been developing higher resolution panel. With higher resolution, TCE underrun problem is observed more easily. Highest QoS priority can provide obvious improvement. What's TCE underrun TCE is Timing Controller Engine which is responsible for TFT scan frame refreshes. The pixel FIFO (PIX_FIFO) is used to load working buffer pixel data for TCE. When FIFO underrun, TCE_UNDERRUN_IRQ interrupt is triggered, and TCE underrun log pops up in kernel log. The pixel data is processed by TCE to generate TFT voltage control pixels for panel. If an underrun occurs, unknown data is used and that can damage the panel. About the patch The patch raises EPDC reading to highest priority (QoS='f'), so the EPDC reading becomes real time channel in MMDC configuration. The patch is based on L4.1.15 kernel. Stress test of unit test can pass with 1920x1440 configuration.

i.MX31 Lite Kit is a low cost development board developed by LogicPD OEM (an AMD company). Expanding on the Freescale offering of low-cost, high-performance application development kits, Freescale introduces the i.MX31 Lite Kit. Developed in collaboration with Logic Product Development, the Freescale i.MX31 Lite Kit provides a product-ready software and hardware platform for OEMs, ODMs, IDHs and independent developers. The i.MX31 Lite Kit enables rapid design of embedded products targeting the medical, industrial, wireless, consumer markets and general purpose markets. Leverage the power of our popular i.MX 31 multimedia processor in this cost-effective development solution. Features The Freescale i.MX31 SOM-LV is based on the i.MX31 multimedia applications processor running up to 532 MHz. LCD Display Connector Integrated LCD, touch, and backlight connector for Zoom Display Kits Audio Stereo input and output jacks Network Support One RJ45 Ethernet jack connector with magnetics (application/debug) PC Card Expansion CompactFlash® Type I card MMC/SD card ATA Support USB One USB 2.0 high-speed host interface One USB high-speed On-the-Go device interface Serial Ports 115.2kbps RS-232 debug serial port Software LogicLoader™ (bootloader/monitor) Windows® CE 5.0 BSP GNU cross development toolchain (compiler, linker, assembler, debugger) Cables Serial cable (null-modem) Ethernet crossover cable USB A to mini-B cable 5 volt power supply (with Europe, Japan, UK, & US adapters) Mechanical 146.1 mm wide x 158.8 mm long x 17.1 mm high RoHS Compliant More information [here.]

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343802 

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-342420 

Freescale introduces the i.MXS Development Kit, a high performance development kit ideal for Microsoft's Windows Vista™ SideShow™ platform and .NET Micro Framework applications. The advanced i.MXS Development Kit leverages Freescale's i.MXS applications processor, based on the ARM920T™ core, a highly integrated IC that has been in production for nearly two years. The integrated development platform, featuring support of Microsoft's .NET Micro Framework for use with SideShow applications, is designed to enable hardware developers to more quickly and easily design applications targeting Microsoft's highly anticipated Windows Vista operating system. Typical SideShow applications include laptop external displays, remote controls and USB dongles, which can run certain applications without powering up the laptop. The i.MXS Development Kit features a small form-factor reference board that has a 2.5 inch color LCD panel with QVGA resolution. The card includes Freescale’s i.MXS applications processor that provides superb performance and extremely low power consumption, enabling hours of use off a single battery charge. The development kit also includes a USB interface and an expansion connector for add-on modules such as Bluetooth™ technology or the ZigBee™ wireless protocol, creating a comprehensive development platform for a variety of applications. Features i.MXS applications processor, based on the powerful ARM920T™ core Clock source crystal: 32 kilohertz Powered by USB bus voltage or external power adaptor Multi-ICE debug support connector I2C and SSI bus connector for connection to external audio CODEC SMbus interface 32-megabyte (MB) SDRAM device One 8-megabyte (MB) Burst Flash memory device One RS232 transceiver (configured for DCE) supporting on-chip UART1 port 1 UART port at CMOS level for expansion On-Chip USB 1.1 interface On-board 2.5 inch LCD with back-light and QVGA resolution 11 separated GPIO for key-button input LED indicator for power

How to add Ethernet UI support in ICS     How to add Ethernet UI support in ICS 1.  Introduction 2.  New feature detail   1.  Introduction   If you want to add Ethernet UI support , you need manually apply the attached patches in this file which is based on Android ICS and i.MX6.        About what the patches do, here is some comments: framework/base-----0001-ENGR00220371-Ethernet-add-support-for-ethernet.patch        By default, Android has no support for Ethernet UI. So if you want to add Ethernet UI , add Ethernet state tracker & Ethernet service & Ethernet manager & Ethernet monitor like WiFi. Meanwhile we need add Ethernet display support in status bar. Here this patch can solve it. Build---0001-ENGR00220371-Ethernet-add-ethernet-support.patch        add package directory compile. packages\apps\Settings---0001-ENGR00220371-Ethernet-add-app-UI-in-setting.patch        add UI logic in setting app. packages\providers\DownloadProvider---0001-ENGR00220371-Ethernet-add-downloadinfo.patch        add ConnectivityManager.TYPE_ETHERNET type support in download provider’s DownloadInfo.   2.  New feature detail   After applying the above patches, you will get the following features: Icon for Ethernet connection status. If on, a green icon will appear in status bar; If off,no icon will appear.     Add “Ethernet configuration” UI.  Choose box is designed for turn on or off Ethernet.      Only Ethernet is turned on, Ethernet configuration can be configured static IP.   First boot, Ethernet device default may not be eth0. So change it from the device list. Use imx6-ics-ethernet-v3.zip. It has updated and fixed the following issues compared with the previous two versions:   1. fix static IP not work issue. 2. fix dns using default 8.8.8.8 issue. 3. eth0 is the default interface, no longer need to choose it from the list. 4. dhcp is default mode. and if you are using static IP. After reboot, it will restore to dhcp again. 5. no need to edit dns again.   List the bug list for update. If using ethernet as upstream type, you need to apply the attached fix-use-ethernet-as-upstream.patch.   For JB4.2.2 and JB4.3, we have written one apk for this. Anyone who is interested in this can get it.

Using Clock Out - i.MX31PDK i.MX31 has a clock out pin that can be used to output internal clock signals. On the i.MX31PDK the clock out pin is accessible on TP1. The clock out is controlled by register COSR (Clock Out Source Register) at address 0x53F8001C. There three fields on COSR: Field Description CLKOEN (bit 9) Clock output enable bit CLKOUTDIV (bits 8-6) Clock output divide factor CLKOSEL (bits 3-0) These bits select which clock is to be reflected on the clock output CKO. Here are the values each field may assume: CLKOEN Values CLKOUTDIV Values CLKOSEL Values 1 clock output IO pin is enabled 0 clock output IO pin disabled 000 => 1 001 => 2 010 => 4 011 => 8 100 => 16 0000 => mpl_dpdgck_clk 0001 => ipg_clk_ccm 0010 => upl_dpdgck_clk 0011 => pll_ref_clk 0100 => fpm_ckil512_clk 0101 => ipg_clk_ahb_arm 0110 => ipg_clk_arm 0111 => spl_dpdgck_clk 1000 => ckih 1001 => ipg_clk_ahb _emi_clk 1010 => ipg_clk_ipu_hsp 1011 => ipg_clk_nfc_20m 1100 => ipg_clk_perclk_uart1 1101 => ref_cir1 (ref_cir_gateload) 1110 => ref_cir2 (ref_cir_intrcload) 1111 => ref_cir3 (ref_cir_path) Based on the Clock Generation Scheme, we can play with COSR register using the Register Accessing application to test Clock out pin by checking some i.MX31 internal clocks. Testing First we can check the value of CKIH, it should be 26MHz as a 26MHz is connected to that pin. We can write 0x208 to COSR. [CLKOEN = 1| CLKOUTDIV = 1| CLKOSEL = ckih] root@freescale /home$ ./io2 0x53f8001c w 0x208 /dev/mem opened. Memory mapped on address 0x4001f000. Written: 0x208 Then we can check pll_ref_clock. We can write 0x203 to COSR. [CLKOEN = 1| CLKOUTDIV = 1| CLKOSEL = pll_ref_clk] root@freescale /home$ ./io2 0x53f8001c w 0x203 /dev/mem opened. Memory mapped on address 0x4001f000. Written: 0x203 As expected, pll_ref_clock is equals to CKIH because CCMR[PCRS]=10. Reading CCMR to confirm CCMR[PCRS]=10: root@freescale /home$ ./io2 0x53f80000 /dev/mem opened. Memory mapped on address 0x4001f000. Address value 0x53F80000 (0x4001f000): 0x174B0D7D The pll_ref_clock inputs to MCU PLL and Serial PLL. We can check MCU PLL and Serial PLL configurations on MPCTL (0x53F80010) and SPCTL (0x53F80010) registers respectively. Reading MPCTL and SPCTL: root@freescale /home$ ./io2 0x53f80010 /dev/mem opened. Memory mapped on address 0x4001f000. Address value 0x53F80010 (0x4001f010): 0x33280C root@freescale /home$ ./io2 0x53f80018 /dev/mem opened. Memory mapped on address 0x4001f000. Address value 0x53F80018 (0x4001f018): 0x2072356 Determine the PLL multiplication factor from MPCTL and SPCTL: - MPCTL: PD = 1 (0000) | MFD = 52 (0000110011) | MFI = 10 (1010) | MFN = 12 (0000001100) - MCPTL Multiplication Factor: 20,46153 - mpl-dpdgck-clk = 20,46153 * 26MHz = 532 MHz - SPCTL: PD = 1 (0000) | MFD = 520 (1000000111) | MFI = 8 (1000) | MFN = -170 (1101010110) - SCPTL Multiplication Factor: 15,3461538 - spl-dpdgck-clk = 15,3461538 * 26MHz = 399 MHz Finally we can output mpl-dpdgck-clk and spl_dpdgck_clk values to check the calculations above. We can write 0x300 to COSR for mpl-dpdgck-clk. [CLKOEN = 1| CLKOUTDIV = 16| CLKOSEL = mpl_dpdgck_clk] And 0x307 for spl-dpdgck-clk. [CLKOEN = 1| CLKOUTDIV = 16| CLKOSEL = spl_dpdgck_clk] root@freescale /home$ ./io2 0x53f8001c w 0x300 /dev/mem opened. Memory mapped on address 0x4001f000. Written: 0x300 root@freescale /home$ ./io2 0x53f8001c w 0x307 /dev/mem opened. Memory mapped on address 0x4001f000. Written: 0x307 By multiplying the results above by 16 to compensate for CLKOUTDIV we have the expected results.

This is a HW design checklist for customer's reference. Please read and fill it in carefully before requesting a schematic/design review.

www.nxp.com公网资源 .............................................. 2 1.1 www.nxp.com Documentation ................................ 3 1.2 www.nxp.com Tools&Software ............................... 7 2 nxp share point资源(仅对有访问权限客户开放) ....... 14 2.1 i.MX 8X Family Board, Software POR and How to Purchase ...................................................................... 14 2.2 Development Platforms ........................................ 14 2.3 Device Dcoumentation ......................................... 15 2.4 Security Reference Manual .................................. 16 2.5 Software Documentation ...................................... 16 3 nxp 社区资源 ........................................................... 16

Based on example code provided in AN4466 I've written a simple memory calibration script for ARM DS-5 that runs same steps and prints out results for DQS, read and write calibration. This script can be run on new boards in order to find optimum calibration settings for the memory controller. Prior to running this script it is necessary to run standard memory initialization script! When bringing up new board: obtain default memory initialization script for memory type you're using (for example from DDR stress tester package) and modify the memory controller settings according to memory device you are going to use. run DDR stress tester with the given configuration on target frequency you're going to use to make memory works with given settings (default values for calibration are  fine in most cases unless there's issues with PCB and/or routing). run memory init script and then the attached script to obtain calibrated values. Re-test Vladan

imx8mm platform on 4.14.78/98 GA Android  LCD MIPI panel or HDMI display may appear some strange color stride .  This is  one patch for this issue. 

This tool is also for emmc user partition mirror. Just give this tool the emmc files. The typical use case is for emmc mass production by emmc offline programming. Ver 0.4.0 2/14/2017 Support Android 7 Nougat. AndroidSDCARDMirrorCreator_Version_0.4.0_02142017.tgz Ver 0.3.2: 6/13/2016 Using static link simg2img AndroidSDCARDMirrorCreator_Version_0.3.2_06132016.tgz Ver 0.3.1: 5/31/2016 Remove some redundent code   AndroidSDCARDMirrorCreator_Version_0.3.1_05312016.tgz Ver 0.3: 5/25/2016 Add Marshmallow partition layout AndroidSDCARDMirrorCreator_Version_0.3_05252016.tgz Ver 0.2: Add Lollipop partition layout 1. Directory AndroidSDCARDMirrorCreator |-- AndroidSDCARDMirrorCreator.sh        --- main script |-- CFG.INC                              --- configuration file |-- KitKat_LAYOUT.INC                    --- KitKat partition layout |-- LAYOUT.INC -> Lollipop_LAYOUT.INC    --- symbol link to partition layout |-- Lollipop_LAYOUT.INC                  --- Lollipop partition layout `-- readme.txt                           --- this file 2. Need "root" run or "sudo" to run 3. parted and kpartx must be installed    sudo apt-get instal parted kpartx 4. test pass under the debian 8.2 and ubuntu 12.04 5. The AndroidSDCARDMirrorCreator.sh will look for LAYOUT.INC.    please make symbol link to the correct partition layout.    The default symbol link has created for Lollipop_LAYOUT.INC (LAYOUT.INC -> Lollipop_LAYOUT.INC) 6. Command    AndroidSDCARDMirrorCreator.sh -c    AndroidSDCARDMirrorCreator.sh -p 7. Example:    Suppose    The AndroidSDCARDMirrorCreator directory is in    ~/AndroidSDCARDMirrorCreator       The Android Images are in    ~/SD and ~/eMMC       Sdcdard Mirror:    cd ~/SD    ~/AndroidSDCARDMirrorCreator/AndroidSDCARDMirrorCreator.sh -c    eMMC Mirror:    cd ~/eMMC    ~/AndroidSDCARDMirrorCreator/AndroidSDCARDMirrorCreator.sh -c    8. Once the Mirror has been created. Can be reused. Just use kpartx.

All, This document will help you to understand the " YOCTO PROJECT COMMUNITY LAYERS" and the "YOCTO PROJECT FREESCALE OFFICIAL RELEASE" differences and where the layer content is coming from.   Best Regards, Luis

I've recently done some digging into fstrim feature on sabresd-6q. Here list it below detailed: Background:      When Nexus 7 first came out, many users felt it was speedy and high-performance. But after months of installing applications and using the tablet, things began slowing down.This was a friction point that many hoped would be fixed in the new Nexus 7 (2013) model, which it was. There’s even more to the story though, it turns out Google has fixed that storage I/O aging problem on all Nexus devices with the Android 4.3 update which comes with a little-hyped feature that could be huge for performance in the future – TRIM support via fstrim. Why slowing down？      Remember that deleting a file in software isn't actually communicated to solid state storage (whether SSD or eMMC). The space is freed up from the user's perspective, but the eMMC controller in this case still treats the pages in NAND as having valid data. Let's say you copy a 3GB movie to your internal storage, watch the movie and later delete it. You'd have 3GB free to re-use, but until you re-write those blocks the eMMC controller would treat all 3GB as valid data. There's a data structure used by the eMMC controller that tracks mapping logical locations to physical locations in NAND. I won't go into great detail here but the more complex that mapping becomes, and the more locations that have to be tracked, the slower internal NAND management works. Why SSD has such issue? Root cause is "Flash memory is divided into blocks, which is further divided in pages. The minimum write unit is a page, but the smallest erase unit is a block" which will cause fragments as time goes. Why fstrim?      Fstrim is one mechanism of linux filesystem which derives from TRIM. TRIM is already introduced since linux2.6.33. It is the name of a command that the operating system can send to tell the SSD which blocks are free in the filesystem.The SSD uses this information to internally defragment the blocks and keep free pages available to be written quickly and efficiently. How framework triggers fstrim in android4.3?      Android4.3 introduces a new service IdleMaintenanceService to manage when and how trigger fstrim in right time. Once system satisfies the following conditions, it will send out one "ACTION_IDLE_MAINTENANCE_START" intent which the MountService listens for. Last time  "ACTION_IDLE_MAINTENANCE_START" intent has been sent before 24 hours. The device is either off-charger with 80% battery or on-charger with 30% battery The device can go idle state. User don't use it for 71 minutes. Test fstrim on Imx.6      In order to wait little time to trigger fstrim, I tried to change the following variables not to wait 71 minutes and 24 hours. After changing, it will trigger one time fstrim two minutes after system goes into idle state every 30 minutes. --- a/services/java/com/android/server/IdleMaintenanceService.java +++ b/services/java/com/android/server/IdleMaintenanceService.java -    private static final long MIN_IDLE_MAINTENANCE_INTERVAL_MILLIS = 24 * 60 * 60 * 1000; // 1 day +    private static final long MIN_IDLE_MAINTENANCE_INTERVAL_MILLIS = 30 * 60 * 1000; // 30 minute -    private static final long MIN_USER_INACTIVITY_IDLE_MAINTENANCE_START = 71 * 60 * 1000; // 71 min +    private static final long MIN_USER_INACTIVITY_IDLE_MAINTENANCE_START = 2 * 60 * 1000; // 2 min -    private static final long MAX_IDLE_MAINTENANCE_DURATION = 71 * 60 * 1000; // 71 min +    private static final long MAX_IDLE_MAINTENANCE_DURATION = 2 * 60 * 1000; // 2 min Firstly I  run Quadrant apk to see my I/O performance at beginning, Its score is 3544. During this 30 minutes, you can try to mess your system. Try your best to install most apks. Run monkey test in background. Then I  run Quadrant again to check my I/O performance, its score is only a little decline 3538. After that I run "logcat | busybox grep -i fstrim" in console to wait for the action of fstrim, here is my logcat: 130|root@sabresd_6dq:/ # logcat -d | busybox grep -i fstrim I/fstrim  ( 2344): Starting fstrim work... I/fstrim  ( 2344): Invoking FITRIM ioctl on /data I/fstrim  ( 2344): Trimmed 6367305728 bytes on /data I/fstrim  ( 2344): Invoking FITRIM ioctl on /cache I/fstrim  ( 2344): Trimmed 526355456 bytes on /cache I/fstrim  ( 2344): Finished fstrim work. OK, I checked the I/O information again, its score is restored to 3546: Conclusion      Good, fstrim takes effect. So on imx.6 using android4.3, fstrim will also work automatically. We will also enjoy good performance in I/O memory.Great!

Question: An alignement trap in Linux had been seen in an unaligned access of the WEIM (to an external FPGA) Alignment trap: testFPGA (1027) PC=0x000086dc Instr=0xe1d330b0 Address=0x08000001 FSR 0x011 The issue can be reproduced with the platform SDK EIM parallel Nor Test on the Sabre AI - When I access WEIM_BASE_ADDR +1 I get an exception. EIM test start: Flash size: 0x 2000000 Flash erase... . Oops, data abort occurred! Registers at point of exception: cpsr = nZCvqeAift Supervisor (0x60000113) r0 = 0x00000000    r8 =  0x00000000 r1 = 0x00000000    r9 =  0x00000000 r2 = 0x00000001    r10 = 0x00000000 r3 = 0x08000001    r11 = 0x10409770 r4 = 0xdeadfeed    r12 = 0x00000001 r5 = 0x10002458    sp =  0x10409734 r6 = 0x00000000    lr =  0x1000ef9c r7 = 0x00000094    pc =  0x1000bfd0 dfsr = 0x00000001 dfar = 0x08000001 Access type: read Fault status: 0x1 Is adress alligned access mandatory for EIM or AXI HW? or is it possible to support unaligned access? Answer: EIM should support unaligned access. Also ARM architecture supports unaligned access to data and address buses but only if the MMU co-processor is setup for that. Try checking cp15 sctlr[1]. Linux discourage the access to unaligned memory and some times that makes a bus error resulting in a kernel panic. So the drivers and the setup architecture files should support unaligned memory access. ARM Information Center /linux/Documentation/unaligned-memory-access.txt The EIM device is a AXI slave which should support unaligned access. Reference Manual and there's a sub-chapter in the EIM call AXI(Master) Bus cycles support. In that chapter there's a table AXI to Memory Burst Splits Number in that table states the increment burst access to a aligned or unaligned address. I expect those are for the EIM and not refer only to the AXI bus. At any case is not state clear if unaligned access should work only in burst mode (which doesn't make any sense to me) or if the RM information is incorrect. Also in the same chapter in signals not supported never list the alignment signals so unaligned access is supported. Link with some generic ARM information about that. http://forums.arm.com/index.php?/topic/8862-axi-narrowunaligned-read-transfers/ AXI4 - Aligned & unaligned address - ARM Community

Purpose: Introduce how to debug M4 using trace 32 and the difference with regular debug mode for imx6sx. If you are using other jtag debug tools, maybe you need to do the similar configuration. Debug tools: Trace32 – you can refer to http://www.lauterbach.cn/ for more information about this tool.

This is the prototype demo to enable surround view demo on SabreSD.   The attached Files are HW&SW guides and demo video. Updating Notes: Add miniPCIE Surround View_Rev A design file (include schematic and layout) as attachement. Add Gerber file   i.MX6Q Surround view patch https://community.freescale.com/docs/DOC-95143 Original Attachment has been moved to: Gerber-file.zip Original Attachment has been moved to: miniPCIe-Surround-View_Rev-A.zip