1.Compile full aosp or only kernel Build full aosp: source build/envsetup.sh lunch evk_8mm-userdebug ./imx-make.sh -j8  Only build kernel: ./imx-make.sh kernel -j8 2.Build GKI locally Download GKI outside of android_build. mkdir gki && cd gki (Make sure folder gki is not inside of ${MY_ANDROID}) repo init -u https://android.googlesource.com/kernel/manifest -b commonandroid13-5.15 repo sync Build GKI locally. BUILD_CONFIG=common/build.config.gki.aarch64 build/build.sh 3. Export symbols After building GKI locally, you can copy linux-imx from /vendor/nxp-opensource/kernel_imx into common. cd common rm -r ./* cp ${MY_ANDROID}/vendor/nxp-opensource/kernel_imx/* ./ ln -s ${MY_ANDROID}/vendor/nxp-opensource/verisilicon_sw_isp_vvcam verisilicon_sw_isp_vvcam ln -s ${MY_ANDROID}/vendor/nxp-opensource/nxp-mwifiex nxp-mwifiex  Build GKI about i.MX: BUILD_FOR_GKI=yes BUILD_CONFIG=common/build.config.imx EXT_MODULES_MAKEFILE="verisilicon_sw_isp_vvcam/vvcam/v4l2/Kbuild" EXT_MODULES="nxp-mwifiex/mxm_wifiex/wlan_src" build/build_abi.sh --update-symbol-list -j8 Then the  common/android/abi_gki_aarch64_imx will be generated. cd gki cp common/android/abi_gki_aarch64_imx /tmp/abi_gki_aarch64_imx   Update GKI kernel rm -r common/* # delete imx kernel repo sync # recover aosp kernel cp /tmp/abi_gki_aarch64_imx android/abi_gki_aarch64_imx cd .. BUILD_CONFIG=common/build.config.gki.aarch64 build/build_abi.sh LTO=thin --update -j8  Then, common/android/abi_gki_aarch64.xml is updated.  

  Introduction   Platform: i.MX93 EVK Uboot: origin/lf_v2022.04(lf-6.1.1-1.0.0) The LVDS design and media block control in i.MX93 is very similiar with i.MX8MPlus.This article implements the LVDS driver in uboot. You need apply 0001-Add-fake-adp5585-pwm-driver.patch which implements the adp5585 pwm driver in uboot. This is a fake pwm driver only implement the pwm driver framework. You can't use pwm value to adjust brightness for the moment, but this is enough to enable the backlight. Then please apply 0002-Add-imx93-lvds-and-panel-driver.patch, you will see nxp logo with this panel: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/dy1212w-4856:DY1212W-4856   Porting suggestions   1. Modify panel timing in drivers/video/simple_panel.c /* define your panel timing here and * copy it in simple_panel_get_display_timing */ static const struct display_timing boe_ev121wxm_n10_1850_timing = { .pixelclock.typ = 71143000, .hactive.typ = 1280, .hfront_porch.typ = 32, .hback_porch.typ = 80, .hsync_len.typ = 48, .vactive.typ = 800, .vfront_porch.typ = 6, .vback_porch.typ = 14, .vsync_len.typ = 3, }; static int simple_panel_get_display_timing(struct udevice *dev, struct display_timing *timings) { memcpy(timings, &boe_ev121wxm_n10_1850_timing, sizeof(*timings)); return 0; }   2.Modify VIDEO_PLL The VIDEO_PLL = pixel clock * 7. For default panel, the pixel clock is 71.143MHz and VIDEO_PLL  is 498MHz. static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ FRAC_PLL_RATE(498000000U, 1, 166, 8, 0, 1),/* rate, rdiv, mfi, odiv, mfn, mfd */ FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1), FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), }; 3. Modify lcdif node in dts <498000000>, <71142857>, <400000000>, <133333333>; <VIDEO PLL>,<PIX CLK>, <MEDIA_AXI>,<MEDIA_APB> &lcdif { status = "okay"; - assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>; + assigned-clock-rates = <498000000>, <71142857>, <400000000>, <133333333>; };  

The following setup is done on i.MX 93. For i.MX 8M the same steps are valid and can be followed. Prerequisites Prepare the Yocto environment. $ mkdir imx-yocto-bsp $ cd imx-yocto-bsp $ repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-langdale -m imx-6.1.1-1.0.0.xml $ repo sync  Set the build environment. $ DISTRO=fsl-imx-wayland MACHINE=imx93-11x11-lpddr4x-evk source imx-setup-release.sh -b build-imx93 Add the 32-bit support to the image For i.MX 8M / i.MX 93, building 32-bit applications on 64-bit OS can be supported using the multilib configuration. Multilib offers the ability to build libraries with different target optimizations or architecture formats and combine these together into one system image.  Building a 32-bit application requires the following statements in conf/local.conf. The configuration specifies a 64-bit machine as the main machine type and adds multilib:lib32, where those libraries are compiled with the armv7athf-neon tune, and then includes to the image the lib32 packages. # Define multilib target require conf/multilib.conf MULTILIBS = "multilib:lib32" DEFAULTTUNE:virtclass-multilib-lib32 = "armv7athf-neon" # Add the multilib packages to the image IMAGE_INSTALL:append = " lib32-glibc lib32-libgcc lib32-libstdc++" Multilib is not supported with the debian package management. It requires the RPM system. Check and comment out the two package management lines in conf/local.conf to go to the default RPM. PACKAGE_CLASSES = "package_deb" EXTRA_IMAGE_FEATURES += "package-management" Build the image. bitbake imx-image-core Cross-compile a 32-bit application This section shows how to use the Linux SDK to cross-compile a simple C application into a 32-bit binary. Generate the SDK, which includes the tools, toolchain, and small rootfs to compile against to put on host machine: DISTRO=fsl-imx-wayland MACHINE=imx93-11x11-lpddr4x-evk bitbake core-image-minimal -c populate_sdk Set the SDK environment with the following command before building: source /opt/fsl-imx-wayland/6.1-langdale/environment-setup-armv7at2hf-neon-pokymllib32-linux-gnueabi Implement a simple hello world application: cat hello_world_32.c #include <stdio.h> int main() { printf("Hello, World!"); return 0; } $CC hello_world_32.c -o hello_world_32 Check the file's type: $ file hello_world_32 hello_world_32: ELF 32-bit LSB shared object, ARM, EABI5 version 1 (SYSV), dynamically linked, interpreter /lib/ld-linux-armhf.so.3, BuildID[sha1]=0a5042a0309858e0b10b12175a155cfbfb4c6a80, for GNU/Linux 3.2.0, with debug_info, not stripped Copy the binary to the Linux rootfs. Run the application on i.MX 93 Boot the board and run the application: root@imx93-11x11-lpddr4x-evk:~# ./hello_world_32 Hello, World!  

1.Test environment Board: i.MX8MPlus, RM67199 BSP: uboot 2022.04, linux-6.1.1-1.0.1 2.Modification of uboot  In uboot, you need comment the video_link_shut_down and dm_remove_devices_flags in announce_and_cleanup function. #if defined(CONFIG_VIDEO_LINK) //video_link_shut_down(); #endif board_quiesce_devices(); printf("\nStarting kernel ...%s\n\n", fake ? "(fake run for tracing)" : ""); /* * Call remove function of all devices with a removal flag set. * This may be useful for last-stage operations, like cancelling * of DMA operation or releasing device internal buffers. */ // #ifndef CONFIG_POWER_DOMAIN // dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL); // /* Remove all active vital devices next */ // dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); // #endif cleanup_before_linux(); }  After doing this, the uboot logo will not be cleaned before Linux PM framework. 3.Modification of Linux You need add  CONFIG_LOGO=n into defconfig file to disable kernel logo.  3.1 Disable the power down of mediamix and mipi-dphy in gpcv2.c Please add below code into the beginning of  imx_pgc_power_down function if ((strcmp(genpd->name, "mipi-phy1") == 0) || (strcmp(genpd->name, "mediamix") == 0)) { return 0; }  3.2 Only reset lcdif in the last call of drm framework Please modify imx_lcdifv3_runtime_resume function like this. The imx_lcdifv3_runtime_resume function will be called two times, thus the lcdif will be reset two times.We can let it only reset last time,which before the rootfs mount. bool rst = false; ////////////////////////////// static int imx_lcdifv3_runtime_resume(struct device *dev) { int ret = 0; struct lcdifv3_soc *lcdifv3 = dev_get_drvdata(dev); if (unlikely(!atomic_read(&lcdifv3->rpm_suspended))) { dev_warn(lcdifv3->dev, "Unbalanced %s!\n", __func__); return 0; } if (!atomic_dec_and_test(&lcdifv3->rpm_suspended)) return 0; /* set LCDIF QoS and cache */ if (of_device_is_compatible(dev->of_node, "fsl,imx93-lcdif")) regmap_write(lcdifv3->gpr, 0xc, 0x3712); request_bus_freq(BUS_FREQ_HIGH); ret = lcdifv3_enable_clocks(lcdifv3); if (ret) { release_bus_freq(BUS_FREQ_HIGH); return ret; } ////////////////////////////// if (rst) { /* clear sw_reset */ writel(CTRL_SW_RESET, lcdifv3->base + LCDIFV3_CTRL_CLR); rst = false; } rst = true; ////////////////////////////// /* enable plane FIFO panic */ lcdifv3_enable_plane_panic(lcdifv3); return ret; } 4.Conclusion The uboot logo will be cleaned at log "imx-drm 1.0.0 20120507 for display-subsystem on minor 1". The boot time of  systemd service on evk is very long. For weston.service, it needs 3 seconds. From log here we test, the pcie and ethernet probe after drm system also cost about 1 second. If you want to reduce the boot time of other modules, you can try to reduce the system service and disable pcie/ethernet drivers if you don't need them. [ 2.505616] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1 [ 2.620324] imx6q-pcie 33800000.pcie: iATU unroll: enabled [ 2.620335] imx6q-pcie 33800000.pcie: iATU regions: 4 ob, 4 ib, align 64K, limit 16G [ 2.720689] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up [ 2.820996] imx6q-pcie 33800000.pcie: PCIe Gen.2 x1 link up [ 2.821003] imx6q-pcie 33800000.pcie: Link up, Gen2 [ 2.821010] imx6q-pcie 33800000.pcie: PCIe Gen.2 x1 link up [ 2.821112] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00 [ 2.821119] pci_bus 0000:00: root bus resource [bus 00-ff] [ 2.821126] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 2.821133] pci_bus 0000:00: root bus resource [mem 0x18000000-0x1fefffff] [ 2.821161] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400 [ 2.821176] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff] [ 2.821187] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref] [ 2.821232] pci 0000:00:00.0: supports D1 [ 2.821237] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold [ 2.824664] pci 0000:01:00.0: [1b4b:2b42] type 00 class 0x020000 [ 2.824725] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref] [ 2.824761] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x000fffff 64bit pref] [ 2.825066] pci 0000:01:00.0: supports D1 D2 [ 2.825072] pci 0000:01:00.0: PME# supported from D0 D1 D3hot D3cold [ 2.835499] pci 0000:00:00.0: BAR 0: assigned [mem 0x18000000-0x180fffff] [ 2.835511] pci 0000:00:00.0: BAR 15: assigned [mem 0x18100000-0x182fffff pref] [ 2.835519] pci 0000:00:00.0: BAR 6: assigned [mem 0x18300000-0x1830ffff pref] [ 2.835530] pci 0000:01:00.0: BAR 0: assigned [mem 0x18100000-0x181fffff 64bit pref] [ 2.835561] pci 0000:01:00.0: BAR 2: assigned [mem 0x18200000-0x182fffff 64bit pref] [ 2.835590] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [ 2.835598] pci 0000:00:00.0: bridge window [mem 0x18100000-0x182fffff pref] [ 2.835899] pcieport 0000:00:00.0: PME: Signaling with IRQ 218 [ 2.897767] Console: switching to colour frame buffer device 135x120 [ 3.098361] imx-drm display-subsystem: [drm] fb0: imx-drmdrmfb frame buffer device [ 3.111239] pps pps0: new PPS source ptp0 [ 3.316650] fec 30be0000.ethernet eth0: registered PHC device 0 [ 3.323645] imx-dwmac 30bf0000.ethernet: IRQ eth_lpi not found [ 3.329593] imx-dwmac 30bf0000.ethernet: force_sf_dma_mode is ignored if force_thresh_dma_mode is set. [ 3.340074] imx-dwmac 30bf0000.ethernet: User ID: 0x10, Synopsys ID: 0x51 [ 3.346883] imx-dwmac 30bf0000.ethernet: DWMAC4/5 [ 3.351684] imx-dwmac 30bf0000.ethernet: DMA HW capability register supported [ 3.358825] imx-dwmac 30bf0000.ethernet: RX Checksum Offload Engine supported [ 3.365966] imx-dwmac 30bf0000.ethernet: Wake-Up On Lan supported [ 3.372113] imx-dwmac 30bf0000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 3.379778] imx-dwmac 30bf0000.ethernet: Enabled L3L4 Flow TC (entries=8) [ 3.386573] imx-dwmac 30bf0000.ethernet: Enabled RFS Flow TC (entries=10) [ 3.393373] imx-dwmac 30bf0000.ethernet: Enabling HW TC (entries=256, max_off=256) [ 3.400950] imx-dwmac 30bf0000.ethernet: Using 34 bits DMA width [ 3.608045] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller [ 3.613580] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1 [ 3.621621] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220fe6d hci version 0x110 quirks 0x0000002001010010 [ 3.631059] xhci-hcd xhci-hcd.1.auto: irq 226, io mem 0x38200000 [ 3.637197] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller [ 3.642698] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2 [ 3.650365] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed [ 3.657695] hub 1-0:1.0: USB hub found [ 3.661473] hub 1-0:1.0: 1 port detected [ 3.665669] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. [ 3.674445] hub 2-0:1.0: USB hub found [ 3.678220] hub 2-0:1.0: 1 port detected [ 3.683428] imx-cpufreq-dt imx-cpufreq-dt: cpu speed grade 7 mkt segment 2 supported-hw 0x80 0x4 [ 3.693184] Hot alarm is canceled. GPU3D clock will return to 64/64 [ 3.702683] sdhci-esdhc-imx 30b50000.mmc: Got CD GPIO [ 3.703346] mxc-mipi-csi2-sam 32e40000.csi: supply mipi-phy not found, using dummy regulator [ 3.716645] : mipi_csis_imx8mp_phy_reset, No remote pad found! [ 3.722602] mxc-mipi-csi2-sam 32e40000.csi: lanes: 2, hs_settle: 13, clk_settle: 2, wclk: 1, freq: 500000000 [ 3.739353] mmc1: SDHCI controller on 30b50000.mmc [30b50000.mmc] using ADMA [ 3.752018] isi-m2m 32e00000.isi:m2m_device: Register m2m success for ISI.0 [ 3.759172] cfg80211: Loading compiled-in X.509 certificates for regulatory database [ 3.768303] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' [ 3.787598] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 [ 3.795171] ALSA device list: [ 3.796227] platform regulatory.0: Falling back to sysfs fallback for: regulatory.db [ 3.799186] No soundcards found. [ 3.819630] EXT4-fs (mmcblk2p2): mounted filesystem with ordered data mode. Quota mode: none. [ 3.828212] VFS: Mounted root (ext4 filesystem) on device 179:2. [ 3.834944] devtmpfs: mounted

Installing the new release (Ubuntu 22.04) was detected some NXP boards as iMX8MNEVK, iMX8MM-EVK, iMX8MP-EVK and iMX8ULP-EVK had an issue with the WIFI module that basically it does not initialize at boot. Remember, the supported WIFI modules in Ubuntu 22.04 in the EVKs are the following:       • NXP 88W8987       • NXP 88W9098       • NXP 88W8997       • NXP IW416       • NXP 88W8801       • NXP IW612 To initialize the WIFI module of NXP EVKs in Ubuntu 22.04 you can set the following command in console:   sudo modprobe moal mod_para=nxp/wifi_mod_para.conf   That command find the correct driver for our WIFI module and then initialize it, but this only works when Ubuntu is working and if you reset the EVK you need to set the command again.   The definitive solution is create a custom startup script as a service:   Step 1: Go to etc/systemd/system   cd etc/systemd/system   Step 2: In this directory create a new file with the name of your preference but the extension must be .service. You can do it with nano or vim: sudo nano or sudo vim   The file must contain: [Unit] Description=”Wifi Start” [Service] ExecStart=sudo modprobe moal mod_para=nxp/wifi_mod_para.conf [Install] WantedBy=multi-user.target   Now save the file, in my case the name was wifi_start.service.   Step 3: Now we need to enable the script in the startup/boot sequence following the command: sudo systemctl enable wifi_start.service   Remember in wifi_start.service is the name as you saved your file.   Finally, each time you boot your board, the WIFI module will initialize automatically.   Boards tested: iMX8MN (With WIFI module NXP 88W8987) iMX8MM (With WIFI module NXP 88W8987) iMX8MP (With WIFI module NXP 88W8997) iMX8ULP (With WIFI module NXP IW416)  

Hello everyone, We have recently migrated our Source code from CAF (Codeaurora) to Github, so i.MX NXP old recipes/manifest that point to Codeaurora eventually will be modified so it points correctly to Github to avoid any issues while fetching using Yocto. Also, all repo init commands for old releases should be changed from: $ repo init -u https://source.codeaurora.org/external/imx/imx-manifest -b <branch name> [ -m <release manifest>] To: $ repo init -u https://github.com/nxp-imx/imx-manifest -b <branch name> [ -m <release manifest>] This will also apply to all source code that was stored in Codeaurora, the new repository for all i.MX NXP source code is: https://github.com/nxp-imx For any issues regarding this, please create a community thread and/or a support ticket. Regards, Aldo.

From Android 12, NXP use GKI(Generl kernel image) instead of NXP's kernel code.  This follow up Android ASOP standard. This article described that when customer use Android 12 and later version, they need to pay attention on GKI development, which is different with previous version.

We are pleased to announce that Config Tools for i.MX v13 are now available.

PCIE IP on i.MX8MM and i.MX8MP is same, customer can follow PCIE test Application note to do compliance test, if eye diagram failed, they can fine turn corresponding regs below: iMX8MMRM.pdf IMX8MPRM.pdf GEN1:             GEN2:                 Related code in kernel Phy-fsl-imx8-pcie.c (kernel-source\drivers\phy\freescale)    3794      2020/11/4 static int imx8_pcie_phy_init(struct phy *phy) { ……          /* Configure TX drive level  */        writel(0x2d, imx8_phy->base + 0x404);          return 0; }   Thanks Lambert

1. Description: On the i.MX Android camera HAL, It only supports YUYV sensor, regardless of whether the sensor is connected to ISP or ISI. Some users want to customize the sensor format, such as UYVY or raw, they need a guide to do this, this document intends to describe how to implement raw camera sensor on i.MX8MP android, and output raw data. Note: Base on  i.MX 8M plus, Android12_1.0.0.  2. Camera HAL Android's camera hardware abstraction layer (HAL) connects the higher level camera framework APIs in android.hardware.camera2 to your underlying camera driver and hardware. For more detail information, please refer to AOSP document: https://source.android.google.cn/docs/core/camera/camera3_requests_hal?hl=en while on I.MX camera HAL, the camera subsystem can be divided into several parts:   Camera framework:  frameworks\av\camera Camera service:    frameworks\av\services\camera\libcameraservice\ Camera provider: hardware/interfaces/camera/provider/ hardware/google/camera/common/hal/hidl_service/               hidl_service dlopen the camera HAL3. Camera HAL3:   vendor\nxp-opensource\imx\camera\ Camera driver:   vendor/nxp-opensource/kernel_imx/drivers/media/i2c  It's callstack can be list as follow:  There are 2 streams on pipeline, preview stream need 3 buffers and capture stream need 2 buffers: CameraDeviceSessionHwlImpl: ConfigurePipeline, stream 0: id 0, type 0, res 2592x1944, format 0x21, usage 0x3, space 0x8c20000, rot 0, is_phy 0, phy_id 0, size 8388608 CameraDeviceSessionHwlImpl: ConfigurePipeline create capture stream CameraDeviceSessionHwlImpl: ConfigurePipeline, stream 1: id 1, type 0, res 1024x768, format 0x22, usage 0x100, space 0x0, rot 0, is_phy 0, phy_id 0, size 0 CameraDeviceSessionHwlImpl: ConfigurePipeline create preview stream You can use this command to dump the stream input/output: "setprop vendor.rw.camera.test 1" to dump steam 0. "setprop vendor.rw.camera.test 2" to dump steam 1. Before you implement the command, you need to run “su; setenforce 0” to close the SeLinux, the data is dumped as "/data/x-src.data", "/data/x-dst.data", where "x" is the stream id as "0, "1,", "2", ...   Preview Stream Capture Stream ID 1 0 Resolution 1024*768 2592*1944 Format HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED (34) HAL_PIXEL_FORMAT_BLOB (33) Usage 0x900 GRALLOC_USAGE_HW_TEXTURE      (0x100) GRALLOC_USAGE_HW_COMPOSER  (0x800) 0x3 GRALLOC_USAGE_SW_READ_OFTEN Data space 0 HAL_DATASPACE_V0_JFIF  The following usage will be added by framework to distinguish preview and video:GRALLOC_USAGE_HW_VIDEO_ENCODER 3. Raw support  3.1 system modification  The default image for i.MX 8M Plus EVK supports basler + basler and the cameras can work after the image is flashed and boot up, it’s camera with ISP, but we need ISI to process raw. You should refer to Android_User’s_Guide.pdf, you need find the correct version, as Android12_2.0.0 is different with Android12_1.0.0. To make cameras work with Non-default images, execute the following additional commands: Only OV5640 (CSI1) on host： As we use OV2775 which support 1920*1080, unpacked raw12, the json file: 3.2 DTB modification  1. Firstly, change the BoardConfig.mk to generate dtbo-imx8mp-ov2775.img device\nxp\imx8m\evk_8mp\BoardConfig.mk: TARGET_BOARD_DTS_CONFIG += imx8mp-ov2775:imx8mp-evk-ov2775.dtb 2.  Secondly, add imx8mp-evk-ov2775.dts to vendor\nxp-opensource\kernel_imx\arch\arm64\boot\dts\freescale 3. Change imx8mp-evk-ov2775.dts, connect OV2775 to ISI: &isi_0 { status = "okay"; }; &isp_0 { status = "disabled"; }; &dewarp { status = "disabled"; }; 4. Build dtbo image and flash it to board: ./imx-make.sh dtboimage -j4 fastboot flash dtbo dtbo.img  3.3 Sensor driver modification  I use the OV2775 driver from the isp side, be careful that all the function such as g_frame_interval and enum_frame_size should be implemented, or the HAL will get wrong parameters and return error. static struct v4l2_subdev_video_ops ov2775_subdev_video_ops = { .g_frame_interval = ov2775_g_frame_interval, .s_frame_interval = ov2775_s_frame_interval, .s_stream = ov2775_s_stream, }; static const struct v4l2_subdev_pad_ops ov2775_subdev_pad_ops = { .enum_mbus_code = ov2775_enum_mbus_code, .set_fmt = ov2775_set_fmt, .get_fmt = ov2775_get_fmt, .enum_frame_size = ov2775_enum_frame_size, .enum_frame_interval = ov2775_enum_frame_interval, };  3.4 ISI driver modification  We need to add raw format on ISI driver: }, { .name = "RAW12 (SBGGR12)", .fourcc = V4L2_PIX_FMT_SBGGR12, .depth = { 16 }, .color = MXC_ISI_OUT_FMT_RAW12, .memplanes = 1, .colplanes = 1, .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, }, { .name = "RAW10 (SGRBG10)", .fourcc = V4L2_PIX_FMT_SGRBG10, .depth = { 16 }, .color = MXC_ISI_OUT_FMT_RAW10, .memplanes = 1, .colplanes = 1, .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, } 3.5 Camera HAL modification As there are preview stream and capture stream on the pipeline. GPU does not support raw format, it will print error log when application set raw format:    02-10 18:49:02.162 436 436 E NxpAllocatorHal: convertToMemDescriptor Unsupported fomat PixelFormat::RAW10 02-10 18:49:02.163 2390 2445 E GraphicBufferAllocator: Failed to allocate (1920 x 1080) layerCount 1 format 37 usage 20303: 7 02-10 18:49:02.163 2390 2445 E BufferQueueProducer: [ImageReader-1920x1080f25m2-2390-0](id:95600000002,api:4,p:2148,c:2390) dequeueBuffer: createGraphicBuffer failed 02-10 18:49:02.163 2390 2405 E BufferQueueProducer: [ImageReader-1920x1080f25m2-2390-0](id:95600000002,api:4,p:2148,c:2390) requestBuffer: slot 0 is not owned by the producer (state = FREE) 02-10 18:49:02.163 2148 2423 E Surface : dequeueBuffer: IGraphicBufferProducer::requestBuffer failed: -22 02-10 18:49:02.163 2390 2445 E BufferQueueProducer: [ImageReader-1920x1080f25m2-2390-0](id:95600000002,api:4,p:2148,c:2390) cancelBuffer: slot 0 is not owned by the producer (state = FREE) 02-10 18:49:02.164 2148 2423 E Camera3-OutputStream: getBufferLockedCommon: Stream 1: Can't dequeue next output buffer: Invalid argument (-22)   Modifying the gpu code is not recommended. When preview stream, it's pixel format is fixed to HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED, it needs YUYV format, in this patch, we don't convert raw12 to yuyv, just copy the buffer from input to output, so the preview stream is raw12 actually. When capture stream, we use the Blob format, which usually used for JPEG format. when we find the format is Blob pass down by application, camera HAL will copy the buffer from input to output directly. You can check the detail on function ProcessCapturedBuffer(),    4. Application and Tool 4.1 Application  The test application on the attachment “android-Camera2Basic-master_application.7z”, It's basically a common camera application, it set the capture stream format to blob:  Size largest = Collections.max( Arrays.asList(map.getOutputSizes(ImageFormat.JPEG)), new CompareSizesByArea()); mImageReader = ImageReader.newInstance(largest.getWidth(), largest.getHeight(), ImageFormat.JPEG, /*maxImages*/2); 4.2 Tool We use 7yuv tool to check the raw12 format, which is captured by applicable or dump by HAL, you need set the parameter on the right side:   ImageJ tool also can be used to review raw format.

This hands on is based on the evkmimxrt1170_pxp_lab_cm7.zip which is from https://community.nxp.com/t5/i-MX-RT1170-CAS-Training/PXP-Multiple-Files/ta-p/1178709 this hands on give an example to understand pxp basic concept like letterbox background color, rotation, ps buffer coordination definition, output buffer coordination definition more clear   No Roation This test is based on no rotation, so define as below #define LAB1_BIT_BLIT_NO_ROTATION This demo output is that the rabbit picture shows on the upper left corner of lcd, and the offset width and height is 100   #ifdef LAB1_BIT_BLIT_NO_ROTATION     PXP_ps_bitblit(                    // input                    (void*)bmp_rabbit,                    PIXEL_BYTES,                    BMP_RABBIT_WIDTH,                    BMP_RABBIT_HEIGHT,                      // output                    s_BufferLcd[curLcdBufferIdx],                    DEMO_PANEL_WIDTH,                    DEMO_PANEL_HEIGHT,                    100,  // output offset x                    100,  // output offset y                    kPXP_No_Rotate); #endif       in this lab sample code, the background is set to black, PXP_SetProcessSurfaceBackGroundColor(APP_PXP, 0U);   The output is     If we want to set the background to lighter blue, this is what I want to get     then I modify the code to PXP_SetProcessSurfaceBackGroundColor(APP_PXP, 0xFFF0U);   But we get the same output like, without any difference         Check the code, find that the original code   void PXP_ps_sub_region_bitblit(…) { …..     outputBufferConfig.width = sub_region_width;     outputBufferConfig.height = sub_region_height;   …… }   This means that the output buffer width and height are the same as the picture width and height, so whatever background color you set, you couldn’t find anything difference, then change the output buffer width and height is the same as lcd width and height     void PXP_ps_sub_region_bitblit(…) { …..       outputBufferConfig.width = output_width;       outputBufferConfig.height= output_height;   …… }   Then the output change to     We can find the color on the top of display is still black and this isn’t what I need, still tracing the code   void PXP_ps_sub_region_bitblit(…) { …..  // Output buffer  outputBufferConfig.buffer0Addr   =  (uint32_t)output_buffer + output_offset_y * output_width * pic_bytes_per_pixel + output_offset_x * pic_bytes_per_pixel …… }   output_buffer is defined as lcd buffer start address, here the output buffer start address isn’t defined as lcd buffer start address(output_buffer), this is offset of lcd buffer start address, so change it like   void PXP_ps_sub_region_bitblit(…) { …..  // Output buffer  outputBufferConfig.buffer0Addr = (uint32_t)output_buffer …… }   Then the output is like       The output picture move to the upper left corner without offset, but this demo defines the offset is 100   void PXP_ps_sub_region_bitblit(…) { …..  // PS buffer PXP_SetProcessSurfacePosition(APP_PXP,0,0,BMP_RABBIT_WIDTH - 1U, BMP_RABBIT_HEIGHT - 1U); ….. }   In the original code, the PS buffer offset is 0, because the ps buffer start address is the same as the output buffer start address, and output buffer start address is offset + lcd output buffer start address, so set the PS output offset is 0, but I change the output buffer start address is the same as lcd buffer start address, so change the code   void PXP_ps_sub_region_bitblit(…) { …..             uint32_t psUlcX         = output_offset_x;             uint32_t psUlcY         = output_offset_y;             uint32_t psLrcX, psLrcY;             psLrcX = psUlcX   +  sub_region_width  - 1U;             psLrcY = psUlcY + sub_region_height- 1U;         // PS buffer         PXP_SetProcessSurfacePosition(APP_PXP,psUlcX,psUlcY,psLrcX,psLrcY); ….. }   The output is   \   Now this is what we need     Roation Set Macro to #define LAB2_BIT_90_DEGREE_ROTATION   The output is     When rotation is 90 degree and width is wider than the output height, the display part will be cut, so change the code from Before void PXP_ps_sub_region_bitblit(…) { …..       outputBufferConfig.width = output_width;       outputBufferConfig.height= output_height; ….. }   To   void PXP_ps_sub_region_bitblit(…) { …..  if  (rotate == kPXP_Rotate90)  {     outputBufferConfig.width          = output_height;        /*Joan*/     outputBufferConfig.height         = output_width;         /*Joan*/  } else {         outputBufferConfig.width          = output_width;         /*Joan*/         outputBufferConfig.height         = output_height;        /*Joan*/ }….. }   Because this demo only shows no rotation and 90 degree rotation, if customer needs 270 degree, 180 degree, can add by themselves

current bsp fixed the lvds pixel clock up to 74.25Mhz for single channel and 148.5Mhz for dual channel, if customer wants to know why and how to change it, maybe can refer to the enclosed file, hope helpful for you

On i.MX8MP EVK, image is downloaded into eMMC/SD via OTG1, if customer wants to enable USB OTG2 on i.MX8MP for uuu tool. Pls find modification as attached.

In the i.MX 8M Plus LPDDR4 EVK board there are two Type-C port design. For the port0 is used to power supply no usb function, for the port1 used for USB function but without PD function. But in customer’s design, customer only use one USB design on their board, how to make the one USB work with the PD and USB function, we need to make the hardware design and software modify. This article only give method to realized it and have tested and realized the port1 PD function. 1 Introduction of the USB interface on i.MX8MP         There are two USB 3.0 TypeC controllers with integrated PHY interface on the i.MX8MP: Backward compatibility with USB 2.0 Spread spectrum clock support   The USB on the i.MX8MP supports USB3.0 and is compatible with USB2.0 downward. We can see that the upper layer is the universal layer for USB 2.0 and USB 3.0 operations. This is a common interface, buffer management block, list processor, used to schedule and control the status register (CSR) function： USB 2.0 physical layer and MAC layer USB 3.0 physical layer, link layer and MAC layer   Features of USB 3.0: USB compliant version 3.0 (xHCI compatible) Supports operation as a stand-alone USB host controller USB dual role operation, configurable as host or device Ultra high speed (5Gbit/s), high speed (480Mbit/s), full speed (12Mbit/s) and low speed (1.5Mbit/s) operation. Support independent single port USB operation Support for four programmable bidirectional USB endpoints Support system memory interface with 40 bit addressing capability   2 Design of USB on Development Board         The i.MX 8M Plus processor includes two USB 2.0/3.0 controllers and two integrated USB PHYs. USB supports both running as an independent USB host controller and dual role USB operation, and can be configured as a host or device. Therefore, the design of these two functions is implemented on the development board of i.MX8MP.   We can see that on the development board, one USB1 is used for the USB Type-C port and the other USB2 is used for the USB 3.0 host port. USB Type-C port 0 (J5) is only used for power supply. It does not support USB data transfer. It is the only power port, so the system must always be powered.   On the CPU side of the schematic diagram, we can also see that USB1 is the port for USB Type-C, and USB2 is the host for USB3.0.    USB1 is designed as USB Type-C:   USB2 USB3.0 Host design：   Power design of the USB Type-C port：   3 Only one USB interface is used in the design (compatible with both USB PD function and USB dual roles function)         Two USB Type-C ports are used on our development board. One is used to power the board separately, and the other is used as the function of USB Type-C. However, due to the limited design cost and chip layout and space on the board, some customers will use a USB interface to realize the dual role function of power supply and USB. How to achieve this? USB Device(Download mode)：     USB　Host mode（power+device　Need the hub support PD function）:     The specific implementation and design are as follows: 3.1 Hardware realize PTN5110 To realize the USB Type-C support power supply function, PTN5110 (USB PD TCPC PHY IC) chip is required to realize Type-C data logic and power control and management. The selection of PTN5110 is critical and important.   PTN5110 is a single port USB PD (power supply) PHY IC that conforms to TCPC. It integrates Type-C configuration channel (CC) interface and USB PD physical layer functions into Type-C port manager (TCPM) that handles PD policy management. It complies with USB PD, Type-C and TCPC specifications.   The IC is mainly aimed at applications in system platforms (such as laptops, desktops, Chromebooks, tablets, flip notebooks, etc.). Other application cases may be feasible, depending on the application architecture, such as docking stations, displays, accessories, cable adapters, smartphones, etc.   It can support various Type-C applications: Sink, Source, Sink with accessory support or DRP. It executes Type-C CC simulation part (i.e. Rd/Rp/Ra detection, Rd/Rp indication) and PD Tx/Rx PHY and protocol state machine. PTN5110 supports TCPM in the system implementation of the following PD roles.   PTN5110 integrates VCONN load switch, programmable current limit, reverse leakage current blocking and over temperature protection (OTP). It is equipped with two enable control outputs to control the load switch/FET in the VBUS pull and/or sink path. It can also perform VBUS voltage monitoring/measurement, VBUS forced discharge and discharge discharge.   PTN5110 provides the main IO related functions for the main processor/TCPM, so that Type-C/PD interfaces can be easily controlled and managed through the TCPC interface.   PTN5110 supports a wide range of power input voltages, providing platform integrators with great flexibility. PTN5110 can run on VBUS to support specific system use cases that require no power operation.https://www.nxp.com/products/interfaces/usb-interfaces/usb-type-c/usb-pd-phy-and-cc-logic/usb-pd-tcpc-phy-ic:PTN5110   The design only use the USB1：   Here, it is required to weld R53 or R54. You can refer to this design completely. 2 Software modify Modify the BPS of the software: Take the newest released Linux 5.15.32_2.0.0​ as example: In the u-boot /board/freescale/imx8mp_evk/imx8mp_evk.c     It can be seen that the PD function of the port is turned off, so if you want to use USB1 for power supply, remove the following commands and turn on the PD function of USB1. “-   .disable_pd = true,” Use the above action to enable Port1 PD function. Kernel section modify： Kernel section modify towards to PTN5110. Type-C Configure channel (CC) interface： root/drivers/usb/typec/tcpm/tcpci.c @@ -524,6 +524,7 @@ static int tcpci_vbus_force_discharge(struct tcpc_dev *tcpc, bool enable)  static int tcpci_set_vbus(struct tcpc_dev *tcpc, bool source, bool sink)  {        struct tcpci *tcpci = tcpc_to_tcpci(tcpc); +      unsigned int reg;        int ret;          if (tcpci->data->set_vbus) { @@ -533,16 +534,20 @@ static int tcpci_set_vbus(struct tcpc_dev *tcpc, bool source, bool sink)                         return ret < 0 ? ret : 0;        }   +      ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, &reg); +      if (ret < 0) +              return ret; +        /* Disable both source and sink first before enabling anything */   -       if (!source) { +      if (!source && (reg & TCPC_POWER_STATUS_SOURCING_VBUS)) {                 ret = regmap_write(tcpci->regmap, TCPC_COMMAND,                                     TCPC_CMD_DISABLE_SRC_VBUS);                 if (ret < 0)                         return ret;        }   -       if (!sink) { +      if (!sink && (reg & TCPC_POWER_STATUS_SINKING_VBUS)) {                 ret = regmap_write(tcpci->regmap, TCPC_COMMAND,                                     TCPC_CMD_DISABLE_SINK_VBUS);                 if (ret < 0)   Type-C port manager managed by PD (TCPM)： root/drivers/usb/typec/tcpm /tcpm.c @@ -340,6 +340,7 @@ struct tcpm_port {         */        bool vbus_vsafe0v;   +      bool vbus_keep;        bool vbus_never_low;        bool vbus_source;        bool vbus_charge; @@ -3662,7 +3663,8 @@ static void tcpm_reset_port(struct tcpm_port *port)        port->rx_msgid = -1;          port->tcpc->set_pd_rx(port->tcpc, false); -       tcpm_init_vbus(port);     /* also disables charging */ +      if (!port->vbus_keep) +              tcpm_init_vbus(port);  /* also disables charging */        tcpm_init_vconn(port);        tcpm_set_current_limit(port, 0, 0);        tcpm_set_polarity(port, TYPEC_POLARITY_CC1); @@ -5834,6 +5836,9 @@ static void tcpm_init(struct tcpm_port *port)          port->tcpc->init(port->tcpc);   +      port->vbus_present = port->tcpc->get_vbus(port->tcpc); +      if (port->vbus_present) +              port->vbus_keep = true;        tcpm_reset_port(port);          /* @@ -5872,7 +5877,10 @@ static void tcpm_init(struct tcpm_port *port)         * Some adapters need a clean slate at startup, and won't recover         * otherwise. So do not try to be fancy and force a clean disconnect.         */ -       tcpm_set_state(port, PORT_RESET, 0); +      if (!port->vbus_keep) +              tcpm_set_state(port, PORT_RESET, 0); + +      port->vbus_keep = false;  }    static int tcpm_port_type_set(struct typec_port *p, enum typec_port_type type) Note: The software just needs to modify these two parts. You also need to mention to the proper the I2C port use, if not proper the driver of the PTN5110 can not driver. 4 Test         In our i. MX8MP EVK development board show that R53 and R54 in the USB1 part of our development board are in DNP status, so VBUS_ IN is disconnected and no power comes in. Here, connect R53 or R54 with solder, so that VBUS_ IN, the power comes in again. After the power is connected. The board can be powered through USB1. 4.1 Download images to the emmc on the Board: Power from the USB1, set the boot mode to serial download mode, then go to download images finished. 4.2 Boot up the board from the EMMC Change the boot mode to boot up from EMMC，the board boot up, the log file is as following show：   It will stop at the TCPC for the section of PTN5110 driver. By default, the PD function of port1 in the u-boot is turned off, so if you want to use USB1 for power supply, remove the following commands and turn on the PD function of USB1. “-   .disable_pd = true,” After the PD function is turned on, the board can be started normally, but the whole part running to the kernel will be powered down, so the kernel part of PTN5110 still needs to be modified. After the patch modification of the above kernel part, the board can run normally.         I also did the same experiment on the i.MX8MM EVK development board. The same phenomenon occurs when the kernel starts. Therefore, similar modifications to the above i. MX8MP can work normally. Summary: In one word i.MX8MP and i.MX8M series can realize the role of using a USB for power supply and USB Dual. The hardware design refers to our development board, and we must use the logic chip PTN5110. For software, refer to the above code modification.  

  Background PCIe interface of Android 12 prebuilt and Built image on iMX8MM mini is not coming up. The Android BSP doesn't enable the pcie driver. Solution 1. imx8mm_gki.fragment CONFIG_PHY_FSL_IMX_PCIE=m CONFIG_PCI_IMX6=m 2. device/nxp/imx8m/evk_8mm/SharedBoardConfig.mk $(KERNEL_OUT)/drivers/pci/controller/dwc/pci-imx6.ko \ Result evk_8mm:/ # dmesg | grep pci [ 0.561609] ehci-pci: EHCI PCI platform driver [ 6.515345] imx6q-pcie 33800000.pcie: supply epdev_on not found, using dummy regulator [ 6.524925] imx6q-pcie 33800000.pcie: EXT REF_CLK is used!. [ 6.560211] imx6q-pcie 33800000.pcie: PCIe PLL locked after 20 us. [ 6.567328] imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges: [ 6.584463] imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000 [ 6.593833] imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000 [ 6.603140] imx6q-pcie 33800000.pcie: invalid resource [ 6.708123] imx6q-pcie 33800000.pcie: Link up [ 6.713393] imx6q-pcie 33800000.pcie: Link up [ 6.718586] imx6q-pcie 33800000.pcie: Link up, Gen1 [ 6.832372] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00 [ 6.840023] pci_bus 0000:00: root bus resource [bus 00-ff] [ 6.846535] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 6.853805] pci_bus 0000:00: root bus resource [mem 0x18000000-0x1fefffff] [ 6.861601] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400 [ 6.868529] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff] [ 6.876439] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref] [ 6.884101] pci 0000:00:00.0: supports D1 [ 6.888954] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold [ 6.899174] pci 0000:01:00.0: [1b4b:2b42] type 00 class 0x020000 [ 6.906127] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref] [ 6.914221] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x000fffff 64bit pref] [ 6.922740] pci 0000:01:00.0: supports D1 D2 [ 6.927854] pci 0000:01:00.0: PME# supported from D0 D1 D3hot D3cold [ 6.935200] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) [ 6.962608] pci 0000:00:00.0: BAR 0: assigned [mem 0x18000000-0x180fffff] [ 6.970251] pci 0000:00:00.0: BAR 15: assigned [mem 0x18100000-0x182fffff pref] [ 6.978426] pci 0000:00:00.0: BAR 6: assigned [mem 0x18300000-0x1830ffff pref] [ 6.986479] pci 0000:01:00.0: BAR 0: assigned [mem 0x18100000-0x181fffff 64bit pref] [ 7.001517] pci 0000:01:00.0: BAR 2: assigned [mem 0x18200000-0x182fffff 64bit pref] [ 7.010203] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [ 7.016271] pci 0000:00:00.0: bridge window [mem 0x18100000-0x182fffff pref] [ 7.025830] pcieport 0000:00:00.0: PME: Signaling with IRQ 238 [ 7.033786] pcieport 0000:00:00.0: AER: enabled with IRQ 238  

i.MX8 VPU hardware decoder support below video codec: H.265 HEVC Main Profile 4Kp60 Level 5.1 H.264 AVC Constrained Baseline, Main and High profile H.264 MVC WMV9 / VC-1 Simple, Main and Advanced Profile MPEG 1 and 2 Main Profile at High Level AVS Jizhun Profile (JP) MJPEG4.2 ASP, H.263, Sorenson Spark Divx 3.11, with Global Motion Compensation (GMC) ON2/Google VP6/VP8 RealVideo 8/9/10 JPEG and MJPEG A/B Baseline   i.MX8 VPU Linux driver is implemented based on V4L2 standard. Chromium beside software video decoding, it also support hardware video decoder(VideoDecodeAccelerator),  there are some kind of VideoDecodeAccelerator, one of them is V4L2VDA. Please note V4L2VDA is using V4l2 api, so it is possible that change V4L2VDA to enable Chromium hardware video playback on i.MX8.   This doc share patch to add chromium video decode accelerate by using i.MX8QM/i.MX8QXP VPU. It will support chromium H.264, H.265, VP8 hardware video decode. H.264 and H.265 need use mp4 container. VP8 use webm container.   HW: i.MX8QM/i.MX8QXP MEK board, 1080P HDMI display, mouse, keyboard SW: i.MX8 5.10.72_2.2.2 yocto bsp release(which included chromium 91.0), and patch in this doc   Patch description: imx8-5.10.72-vpudrv-update.diff, update i.MX8  5.10.72_2.2.2 kernel vpu driver to https://source.codeaurora.org/external/imx/linux-imx/commit/drivers/mxc/vpu_malone?h=lf-5.15.y&id=fa7c67e2c9ed4fb8392fa258f931d6996339a17a chromium-ozone-wayland_91.0.4472.114.bb.diff, change meta-browser/meta-chromium/recipes-browser/chromium/chromium-ozone-wayland_91.0.4472.114.bb for adding some compile flags, etc. 5.10.72-merge.patch, this patch change chromium source code to add video decode accelerate by using i.MX8 VPU.   Build steps: 1>Download i.MX8 5.10.72_2.2.2 yocto release from nxp.com 2>apply chromium-ozone-wayland_91.0.4472.114.bb.diff to change meta-browser/meta-chromium/recipes-browser/chromium/chromium-ozone-wayland_91.0.4472.114.bb 3>put 5.10.72-merge.patch to folder path_of_yocto-5.10.72-2.2.2/sources/meta-browser/meta-chromium/recipes-browser/chromium/files/ 3>apply imx8-5.10.72-vpudrv-update.diff to i.MX8 5.10.72_2.2.2 kernel 4>under the yocto image build folder, add "CORE_IMAGE_EXTRA_INSTALL += "chromium-ozone-wayland" to file path_of_yocto-5.10.72-2.2.2/folder-of-bld/conf/local.conf 5>run bitbake to build rootfs image   Test steps: After system boot up, put some video clip under /home/root/video then run below cmd (do not run chromium without any parameter, as that will start chromium with some other setting, you can check /usr/lib/chromium/chromium-wrapper) "/usr/lib/chromium/chromium-bin   --no-sandbox --ozone-platform=wayland --enable-features=VaapiVideoDecoder  --enable-accelerated-video-decode   --enable-clear-hevc-for-testing --ignore-gpu-blacklist --window-size=1920,1180  /home/root/video" then use mouse to click video clip and will start playback.   Reference: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors:IMX8-SERIES https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX https://www.chromium.org/audio-video/#:~:text=codec%20and%20container%20support https://github.com/igel-oss/meta-browser-hwdecode/blob/master/recipes-chromium/chromium/files/0001-Add-support-for-V4L2VDA-on-Linux.patch      

1. Intro   This document contains instructions to run run the SAI low power audio demo on the i.MX 8M Plus EVK. Here, the  RPSMG to allows audio to be passed from the A53 cluster running Linux to the M7 core. The latter controls the on board WM8960 audio codec,  which is connected to a 3.5 mm audio jack that allow us to play music using headphones. I will show the necessary steps to make the demo work and will add some GStreamer examples to demonstrate the demo's capabilities.   TBD: update this with a nice diagram that depicts the A53 and M7 RPMSG channel. 2. Requirements   Hardware  MX 8M Plus EVK Headphones with 3.5 mm audio jack Type-C power supply for i.MX 8M Plus EVK Micro USB to USB adapter cable Software  A recent prebuilt Linux BSP image from NXP.com ( we tested this on 5.15.35 and 5.15.5 releases) Windows 10 or Ubuntu 20.04 Workstation MCUXpresso SDK for i.MX 8M Plus ( available from:  Welcome | MCUXpresso SDK Builder (nxp.com)) 3. Reference documentation for this example   MCUXpresso SDK   [1] Getting Started with MCUXpresso SDK for EVK-MIMX8MP     Available within the MCUXpresso SDK package:  \{INSTALL PATH}\SDK_X_X_X_EVK-MIMX8MP\docs    [2] SAI low power audio README file Contains instructions for the SAI Low Power Audio Demo.  Available within the MCUXpresso SDK package: \{INSTALL PATH}\SDK_X_X_X_EVK-MIMX8MP\boards\evkmimx8mp\demo_apps\sai_low_power_audio   4. Downloading a pre-built Linux BSP image for the i.MX 8M Plus   I will make use of the prebuilt Linux Image for the i.MX 8M Plus EVK for demonstrating the demo works.  At the moment of writing this time, I used the 5.15.32 release, although there are older releases like 5.10.5 that I tested and proved to work with no issues. This SAI Low Power Audio Demo shall work for other processors on the i.MX 8M family. Although specific instructions ( e.g. load address for M-core binary load) might require some adaptation. For M-core load address, please refer to the specific MCUXpresso SDK documentation for each processor. The prebuilt Linux image (5.15.32) for the i.MX 8M Plus EVK can be downloaded from here: https://www.nxp.com/webapp/Download?colCode=L5.15.32_2.0.0_MX8MP&appType=license You can download other releases from here: Embedded Linux for i.MX Applications Processors | NXP Semiconductors . Select a version and a board and select download. 5. Flashing the BSP image   If you are using an Ubuntu 20.04 workstation, I recommend you to flash the image using dd. For this, you can refer to the i.MX Linux User's Guide: Section - 4.3.2 Copying the full SD card image - https://www.nxp.com/docs/en/user-guide/IMX_LINUX_USERS_GUIDE.pdf sudo dd if=.wic of=/dev/sdx bs=1M && sync NOTE: when using dd, ALWAYS, double check the of device that you are about to writing. Messing up with another location or partition will harm your system   If you are following this document on a Windows machine: You can use the Universal Update Utility (UUU) to flash your image on either the board's eMMC or SD card. Document named UUU.pdf shall serve as your reference guide for further instructions and flashing examples. It is available along with UUU binary here: https://github.com/NXPmicro/mfgtools/releases Two examples are shown below for your convenience:                                     SD card flash                                                 uuu -b sd_all bootloader rootfs.sdcard.bz2                                     eMMC flash                                                 uuu -b emmc_all bootloader rootfs.sdcard.bz2        uuu uuu.auto NOTE: UUU is also compatible with Ubuntu NOTE: there are other engineers who like to use BalenaEtcher for flashing their BSP images. I have tested it and works on both Ubuntu and Windows 10 machines.   6. Preparing the BSP and booting up M7 core  using U-Boot   I am writing this upon the instructions contained on the README file for the low power audio example  [2]. Instructions ready to copy and paste will follow:   Instruct U-Boot to pass to the kernel the rpmsg device tree to enable communication between the A53 cluster and the M7 one: u-boot=>setenv fdtfile imx8mp-evk-rpmsg.dtb u-boot=>saveenv Load the M7 example: u-boot=>setenv mmcargs 'setenv bootargs ${jh_clk} console=${console} root=${mmcroot} snd_pcm.max_alloc_per_card=134217728' u-boot=>saveenv Now, we need to load the M4 with the demo. Refer to [1] for further information. If running the BSP on an SD card, make sure the example binary is listed on the boot partition as follows: fatls mmc 1:1 You shall see something similar to this:             imx8mp_m7_TCM_sai_low_power_audio.bin Open the serial terminal emulator for the M7. Out of the fourth ports listed when we plug the i.MX 8M Plus serial debug cable to the PC, the M7 is typically the last one listed.   All the serial ports available to the workstation when the i.MX 8M Plus serial cable is connected to it. NOTE: you may require to install addtitional COM drivers if you are running on Windows. I like doing the previous step so I can see the result of the next commands issued in U-boot to load the M7 image. fatload mmc 1:1 0x48000000 imx8mp_m7_TCM_sai_low_power_audio.bin; cp.b 0x48000000 0x7e0000 20000; bootaux 0x7e0000 Here is an screenshot that shows how the U-Boot's response should look: U-Boot response when loading the SAI low power audio example to the Cortex M7 That should have prompted the following message on the M7 terminal: M7-core is up!   Now, let’s move to user space! u-boot=> boot 7. Testing the example using a simple GStreamer pipeline   As soon as the O.S. finishes booting. We can see that M7 terminal prompts the following: M7 is now in STOP mode; waiting for some audio to beat the room! Confirm that the WM8960 is listed as audio card as follows: cat /proc/asound/cards             Listing avaialable audio cards. WM8960 should be present. Make note of the list. The wm8960 is listed a the third sound card. This is where I like to differ a bit from [2] and I suggest a quicker test in case of not having an audio file ready. We just simply use GStreamer to play an audiotest source. Please make sure to plug in your headphones onto the board’s 3.5 mm jack before.   The following GStreamer pipeline is using the WM8960 as an audiosink.  gst-launch-1.0 audiotestsrc ! alsasink device=hw:3   NOTE: please be cautious and not put the headphones directly in your head at the first attempt. The sound can be too loud to some people. This is what you should see on the M7 side: Stop the GStreamer pipeline issuing CTRL + C. M7 shall warn you about that: NOTE: you can use the aplay command to play audio as shown on [2]. However, I consider using a testsrc is much quicker and flexible for a quick test.  8. Additional information   Feel free to go ahead and tweak the GStreamer pipeline to change audio test source properties. audiotest src. This command will let you know the available options:            gst-inspect-1.0 audiotestsrc                         NOTE: you can navigate through the displayed list using the “d”key. Press “q’’ to quit. For example:     For example, I am reproducing sound using a different setup based on the list above: gst-launch-1.0 audiotestsrc freq=4000 volume=0.8 wave=8 ! alsasink device=hw:3 9.  Errata and future updates   TBD:     Add an example on how to define the default audio card and play the audio either using gst-play or building the pipeline using filesrc Comment on the limitations of the M7 core regarding sample rate and audio formats  

some industry customer to use i.MX8MM will use RMII to link the 100Mhz ethernet phy and wish to use our i.mx8mm output 50Mhz reference clock to external phy to save a crystal, this doc and patch explain how to support it. SW: Linux BSP 5.10.17. HW: i.MX8MM LPDDR/DDR EVK board. 中文版本为一个完整的如何支持一个100Mhz以太网PHY  

BSP: L5.15.5_1.0.0 Platform: i.MX8MPlus EVK Background   The function lpddr4_mr_read in BSP always return zero and this casue the customer can't use it to read MR registers in DRAM. This is a simple demo for reading MR registers. Patch Code   diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 0f1e832c03..fd68996a23 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -721,6 +721,8 @@ int wait_ddrphy_training_complete(void); void ddrphy_init_set_dfi_clk(unsigned int drate); void ddrphy_init_read_msg_block(enum fw_type type); +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr); + void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 33bbbc09ac..85e40ffbbe 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -150,6 +150,40 @@ int board_fit_config_name_match(const char *name) return 0; } #endif +void lpddr4_get_info() +{ + int i = 0, attempts = 5; + + unsigned int ddr_info = 0; + unsigned int regs[] = { 5, 6, 7, 8 }; + + for(i = 0; i < ARRAY_SIZE(regs); i++){ + unsigned int data = 0; + data = lpddr4_mr_read(0xF,regs[i]); + ddr_info <<= 8; + ddr_info += (data & 0xFF); + switch (i) + { + case 0: + printf("DRAM INFO : Manufacturer ID = 0x%x",ddr_info); + if(ddr_info & 0Xff) + printf(", Micron\n"); + break; + case 1: + printf("DRAM INFO : Revision ID1 = 0x%x\n",ddr_info); + break; + case 2: + printf("DRAM INFO : Revision ID2 = 0x%x\n",ddr_info); + break; + case 3: + printf("DRAM INFO : I/O Width and Density = 0x%x\n",ddr_info); + break; + default: + break; + } + } + +} void board_init_f(ulong dummy) { @@ -187,6 +221,8 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); + + lpddr4_get_info(); board_init_r(NULL, 0); } diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 326b92d784..f45eeaf552 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -194,8 +194,15 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); } while ((tmp & 0x8) == 0); tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); - tmp = tmp & 0xff; reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + + while (tmp) { //try to find a significant byte in the word + if (tmp & 0xff) { + tmp &= 0xff; + break; + } + tmp >>= 8; + } return tmp; }     Test Result  

Many customer set GPIO as input or output functions. While they are confused on how to set GPIO property. This article describe on GPIO property setting tips, especially that input and out property setting are different.