uSDHC auto tuning and possible SDIO failures

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uSDHC auto tuning and possible SDIO failures

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uSDHC auto tuning and possible SDIO failures

1 - Introduction:

The Ultra Secured Digital Host Controller (uSDHC) provides the interface between the host processor and the SD/SDIO/MMC cards. Most recent versions provides the ability to automatically select a quantized delay (in fractions of the clock period) regardless of on-chip variations such as process, voltage, and temperature (PVT). The auto tuning is performed during runtime at hardware level, no software enablement is needed to drive this feature.

2 - Failure description:

SDIO cards can implement an optional feature that uses DATA[1] to signal the card's interrupt to the i.MX device, this feature can be enabled by the SDIO card device and does not depends on i.MX uSDHC driver configuration.

NXP Linux BSP is enabling the auto tuning for high SDIO frequencies (SDR104 and SDR50). Out of reset uSDHC_VEND_SPEC2 register is configured to use DATA[3:0] for calibration, this setup can conflict with the SDIO interrupt as DATA[1] signal can be asserted asynchronously.

SDIO failures can be observed when running SDIO applications that requires high usage of the SDIO interface (e.g Download of large files), SDIO controller cannot return an accurate DLL causing failures such as "CMD53 read error".

Failure can be observed on i.MX8MM EVK and i.MX8MN EVK boards, both devices are running 88w8987 Wi-Fi chipset at 208Mhz (SDR104). Users can observe an SDIO crash followed by error message below at Linux Kernel level.

[ 401.945627] cmd53 read error=-84
[ 401.974677] moal_read_data_sync: read registers failed

3 - Impacted devices:

The following devices are impacted by this limitation.

- i.MX6 Family:
  i.MX6SL, i.MX6SLL, i.MX6SX, i.MX6UL, i.MX6ULZ and i.MX6ULL.
- All i.MX7 and i.MX7ULP family:
  i.MX7D, i.MX7S and i.MX7ULP.
- All i.MX8M Family:
  i.MX8MQuad, i.MX8M Mini, i.MX8M Nano, i.MX8M Nano UL and i.MX8M Plus.
- All i.MX8/8X Family:
  i.MX8DQXP, i.MX8DX and i.MX8QM.

NXP Linux BSP is enabling the auto tuning for SDR104 and SDR50 modes. Other operation modes are not impacted by this limitation.

Users can poll uSDHCx_CLK_TUNE_CTRL_STATUS register when running SDIO applications to confirm. TAP_SEL_PRE field is updated automatically during run time and constant variations can point to an incorrect delay cell calculated by the uSDHC controller.

brenolima_0-1630447343352.png

brenolima_0-1630435469442.png

 

All NXP Wi-Fi chipsets are enabling SDIO interrupt during firmware load, failures can be observed with any Wi-Fi vendor enabling SDIO asynchronous interrupt.

4 - Software changes:

Recommendation is to enable auto tuning for DATA[0] and CMD signals only, DATA[1] should not be used for auto calibration to avoid a possible conflict with SDIO interrupt. This setup can only be used if SDIO interface length are well matched.

Software patches can be found at codeaurora.org. Fix is already included in L5.10.52-2.1.0 BSP, users can add fsl,sdio-interrupt-enabled property to uSDHC device tree node to enable SW workaround.

https://source.codeaurora.org/external/imx/linux-imx/commit/?h=lf-5.10.y&id=3b3d6dec05277f7786d81359...

https://source.codeaurora.org/external/imx/linux-imx/commit/?h=lf-5.10.y&id=b9b5a43df1d709809b2b654a...

https://source.codeaurora.org/external/imx/linux-imx/commit/?h=lf-5.10.y&id=95a846af9f82dc6ea60064d9...

 

Version history
Last update:
‎10-08-2021 12:42 PM
Updated by: