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The MCX W71 is a secure and ultra‑low‑power wireless microcontroller designed for Bluetooth® Low Energy 5.3 applications alongside Matter, Thread and Zigbee connectivity.  MCX W71 targets Bluetooth® LE 5.3 designs with basic connectivity requirements. Applications requiring greater scalability, advanced Bluetooth features, or long‑term feature expansion should use MCX W72 MCX W71 Block Diagram Evaluation boards FRDM-MCXW71 Page FRDM-MCXW71 User Manual FRDM-MCXW71 Getting Started   Bluetooth For the latest Bluetooth LE 6.x features please refer to MCX W72 Knowledge Hub  
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What is NAN? Neighbor Awareness Networking (NAN), also known as Wi-Fi Aware, is a mechanism defined by the Wi-Fi Alliance. NAN is an additional Wi-Fi interface to micro-AP (uAP), Station (STA), and Wi-Fi direct (wfd) that allows for quick discovery without the connection-association flow. The interface named: nan0.In this demo test, NAN is used to Wi-Fi locate and/or range. NXP Wi-Fi Products Supports NAN: Currently we have our IW612, IW611,AW611 and AW693 support NAN feature on Linux OS, and the remote devices should also be Linux OS or Android OS. Currently we do not support for remote device which running iOS. Below is the Release Notes showing which product in our NXP supports NAN feature. https://github.com/nxp-imx/mwifiex/blob/doc_WCT_release/doc/Release_Notes/Linux_RN/topics/wi_fi_radio.md Caution: There is typo in above release note. Actually IW610 doesn't support NAN feature. Demo setup: In this doc, the test is based on 2 IW612 module: Murata 2EL M.2 module on I.MX93-EVK which is running Linux OS, the Linux kernel is L6.12.49. IW612's driver and FW version is: SDIW612---18.99.8.p3--MM6X18542.p8-(FP92), and the nanapp in this release could not outout wls message, official working nanapp will be in next release, available in the end of March/2026. wifi_mod_para.conf SDIW612 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=2 auto_ds=2 host_mlme=1 drv_mode=0x17 fw_name=nxp/sduart_nw61x_v1.bin.se } Copy correct version's nanapp and mlanutl and mlanwls to 2 boards, and add execute permission. root@imx93evk:~# chmod +x nanapp root@imx93evk:~# chmod +x mlanutl root@imx93evk:~# chmod +x mlanwls Copy correct FWand driver: mlan.ko + moal.ko(Cross compiled with L6.12.49 linux kernel BSP, not included in this doc). After the I.MX93-EVK board boot up, need to unload the default L6.12.49's Wi-Fi driver, then load the newer L6.18.2 Wi-Fi driver and FW. The whole process is shown as follow: The generated wls_leader.log and wls_follower.log files contain location information. The Wireshark sniffer contains NAN-related packets. Please see attached .pdf file for more detailed steps and logs outputs.   How to configure to use Wireshark capture Sniffer logs On Ubuntu PC 24.04.2 LTS? Below is the commands for your reference. sudo iw dev //Check your Wi-Fi card name. Here is:wlp111s0 for me. sudo ifconfig wlp111s0 down sudo systemctl stop NetworkManager sudo killall wpa_supplicant //Here need to stop NetworkManager and wpa_supplicant, otherwise, after we configure wlp111s0 into monitor mode, these 2 service will automatically change it to managed mode. sudo iwconfig wlp111s0 mode monitor //set wlp111s0 into monitor mode sudo iwconfig //check whether set into monitor mode successfully. Here should show Mode:monitor sudo wireshark //Need to use sudo permission to run Wireshark, otherwise, could not use Wireshark to capture sniffer. Then choose wlp111s0 to capture sniffer. Reference link: Neighbor Awareness Networking (NAN) -Application note (confidential) https://github.com/nxp-imx/mwifiex/blob/doc_WCT_release/doc/Release_Notes/Linux_RN/topics/wi_fi_radio.md   Best regards, Christine.
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Be aware that it is necessary to work with the matching narrow band unit (NBU) image for the SDK version of the application you are working with. This means that when you download your SDK, prior to loading any wireless SDK example, update your NBU image with the provided binaries in the following folder of the SDK: ../middleware/wireless/ble-controller/bin   Here you will find the image for the NBU firmware:   To update the NBU, you may use the LinkFlash tool as follow: Open the path to LinkFlash tool. Usually, this path would be: C:\nxp\LinkServer_xx.x.xx ​ Select  KW47B42ZB7xxxA:KW47-EVK  as device, serial wire debug (SWD) as protocol and 0x48800000 as address. Check the 'Mass erase before programming' checkbox. Select ' kw47_nbu_ble_all_hosted.bin ' as image file. Press the 'Program' button and wait for the flash operation to be completed.    
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This post provides guidance on how to port the example projects from the NXP NCI 2.0 NFC library to the MCXW71 Wireless MCU using SPI interface to communicate with PN7160 SPI EVK. To follow this guide, please use the following environment: MCUXpresso IDE 25.06.136. FRDM-MCXW71 SDK v25.12.00 (last available for MCUXpresso IDE). FRDM-MCXW71. OM27160B1 (PN7160 SPI EVK). Hardware Setup. The MCXW71 complies with the Arduino header standard as the OM27160B1 board, therefore you can connect directly the shield over the FRDM-MCXW71 as the pin connection match among both, allowing an easy connection between the devices. Take into consideration that this setup forces us to use the LPSPI1 instance of the MCXW71, it is possible to use another instance, but we would not be able to connect the boards directly, rather we would need to do the connections with jumpers.   Downloading base projects and adapting for MCXW71 port. To start with the porting work, download the NXP-NCI example project from this page. This compressed file contains the base project for different boards that will allow us to do the required modifications to add support for the MCXW71. Once downloaded, extract the SW6705 file into a known path (e.g. the Downloads folder) to later import the project to the IDE. The extracted folder should contain a .zip file with the examples that we will later import to the IDE. Download the FRDM-MCXW71's SDK from the SDK Builder page, make sure to select the 25.12.00 version, as it is the latest SDK available to use along the MCUXpresso IDE. Now we have to import the NXP-NCI2.0_MCUXpresso_examples.zip file we previously extracted to the IDE's workspace, to do so, click on the Import project(s) from file system and in the Project archive (zip) tab, browse for the extracted file of step 1 (NXP-NCI2.0_MCUXpresso_examples.zip) and click on Next >. NOTE: Don’t worry if the IDE shows an error message for not having the SDKs of the default boards (iMXRT1170, LPC55S6x, LPC82x) or having a different version, close the warning message, we only need these examples to copy the NCI library and example files. Your workspace should now look like the following image: Import the hello_world example from the FRDM-MCXW71 SDK: Add the SPI drivers to the imported project by right clicking over the project, hover the cursor over the SDK Management option and select the option Manage SDK Components: Select the driver, click Ok and if you are asked to refresh files accept it, after this you should be able to see the driver in the "drivers" folder of the project. Copy the contents of the source folder of the iMXRT1170 project, as well as the NfcLibrary folder and paste them into the imported hello_world project:   Make sure to delete the hello_world.c and hello_word.mex files as we won't need it again. After this process your project should look like the following image: To avoid compiling issues, exclude from the build the files nfc_example_P2P.c and nfc_example_RW.c, to do so right click on the file, go to Resource Configurations and select Exclude from Build… and select for all configurations. Do this for each file. Add the preprocessor macro: BOARD_NXPNCI_INTERFACE_SPI, as this is used by the example to select the interface with the board. To do this, right-click on the project and select Properties, then drop-down the C/C++ Build option and go to the Settings tab. Here, add the macro in the Preprocessor option, click on Apply and accept the index rebuild. Add the root folder in C/C++ General > Paths and Symbols > Source Location tab, click on Ok and then Apply: Still in Paths and Symbols, go to the Includes tab and add the source, TML and tool folders from workspace, click Ok and Apply. Make sure to add them one by one. Now, go to C/C++ Build > Settings > Includes and add the following folders from Workspace. You can select all of them and add them at the same time or also do it one by one. Once done, click on Apply and Apply and Close. If you are asked to rebuild the index, do it. "${workspace_loc:/${ProjName}/source/TML}" "${workspace_loc:/${ProjName}/source/tool}" "${workspace_loc:/${ProjName}/NfcLibrary}" "${workspace_loc:/${ProjName}/NfcLibrary/inc}" "${workspace_loc:/${ProjName}/NfcLibrary/NdefLibrary}" "${workspace_loc:/${ProjName}/NfcLibrary/NdefLibrary/inc}" "${workspace_loc:/${ProjName}/NfcLibrary/NdefLibrary/src}" "${workspace_loc:/${ProjName}/NfcLibrary/NxpNci20}" "${workspace_loc:/${ProjName}/NfcLibrary/NxpNci20/inc}" "${workspace_loc:/${ProjName}/NfcLibrary/NxpNci20/src}" Source Code Changes. In the board folder, open the board.h file and add the following definitions to refer to the peripherals and clocks to be used. Please notice that you may change the LPSPI instance, however you would need to connect jumpers instead of connecting directly the shield over the FRDM. #ifdef BOARD_NXPNCI_INTERFACE_SPI #define BOARD_NXPNCI_SPI_CLOCK (CLOCK_GetIpFreq(kCLOCK_Lpspi1)) #define BOARD_NXPNCI_SPI_INSTANCE (LPSPI1) #define BOARD_NXPNCI_SPI_BAUDRATE (400000) #endif #define BOARD_NXPNCI_IRQ_PORT (GPIOC) // J2.10 - GPIO0 [PN7160] - IRQ -> J2.10 GPIOC0 [MCXW71] #define BOARD_NXPNCI_VEN_PORT (GPIOA) // J4.1 - GPIO1 [PN7160] - VEN -> J1.8 GPIOA21 [MCXW71] #define BOARD_NXPNCI_DWL_PORT (GPIOA) // J4.2 - GPIO2 [PN7160] - REQ -> J1.7 GPIOA20 [MCXW71] #define BOARD_NXPNCI_IRQ_PIN (0U) #define BOARD_NXPNCI_VEN_PIN (21U) #define BOARD_NXPNCI_DWL_PIN (20U) Now we need to add the required clock, peripheral and pin initialization for our board. To do this, go to the hardware_init.c file inside the board folder, and overwrite the BOARD_InitHardware function with the following: void BOARD_InitHardware(void) { BOARD_InitPins(); BOARD_BootClockRUN(); BOARD_InitDebugConsole(); CLOCK_SetIpSrc(kCLOCK_Lpspi1, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Lpspi1, kSCG_SysClkDivBy16); }   To add the correct pin multiplexing and configuration for our SPI and GPIO pins, go to the pin_mux.c file (also in the board folder) and overwrite the BOARD_InitPins function with the following: void BOARD_InitPins(void) { /* Clock Configuration: Peripheral clocks are enabled; module does not stall low power mode entry */ CLOCK_EnableClock(kCLOCK_GpioA); CLOCK_EnableClock(kCLOCK_GpioC); CLOCK_EnableClock(kCLOCK_PortA); CLOCK_EnableClock(kCLOCK_PortB); CLOCK_EnableClock(kCLOCK_PortC); /*IF SHORTING SH11, SH12, SH13, SH14 needed for LPSPI1*/ const port_pin_config_t portb0_pin46_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_PCS0 */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTB0 (pin 46) is configured as LPSPI1_PCS0 */ PORT_SetPinConfig(PORTB, 0U, &portb0_pin46_config); const port_pin_config_t portb1_pin47_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_SIN */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTB1 (pin 47) is configured as LPSPI1_SIN */ PORT_SetPinConfig(PORTB, 1U, &portb1_pin47_config); const port_pin_config_t portb3_pin1_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_SOUT */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTB3 (pin 1) is configured as LPSPI1_SOUT */ PORT_SetPinConfig(PORTB, 3U, &portb3_pin1_config); const port_pin_config_t portb2_pin48_config = {/* Internal pull-up resistor is enabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPSPI0_SCK */ (uint16_t)kPORT_MuxAlt2, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA19 (pin 14) is configured as LPSPI1_SCK */ PORT_SetPinConfig(PORTB, 2U, &portb2_pin48_config); /*IF SHORTING SH11, SH12, SH13, SH14 needed for LPSPI1*/ const port_pin_config_t irq_pin = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullUp, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as PTC0 */ (uint16_t)kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC0 (pin 37) is configured as PTC0 */ PORT_SetPinConfig(PORTC, 0U, &irq_pin); const port_pin_config_t ven_pin = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as PTA20 */ (uint16_t)kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA20 (pin 17) is configured as PTA20 */ PORT_SetPinConfig(PORTA, 20U, &ven_pin); const port_pin_config_t req_pin = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as PTA21 */ (uint16_t)kPORT_MuxAsGpio, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA21 (pin 18) is configured as PTA21 */ PORT_SetPinConfig(PORTA, 21U, &req_pin); const port_pin_config_t portc2_pin39_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART1_RX */ (uint16_t)kPORT_MuxAlt3, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC2 (pin 39) is configured as LPUART1_RX */ PORT_SetPinConfig(PORTC, 2U, &portc2_pin39_config); const port_pin_config_t portc3_pin40_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART1_TX */ (uint16_t)kPORT_MuxAlt3, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC3 (pin 40) is configured as LPUART1_TX */ PORT_SetPinConfig(PORTC, 3U, &portc3_pin40_config); }   To add the required interfacing APIs specific of our chip, we need to modify the tml.c file from the TML folder, in this file overwrite the functions: INTF_INIT, INTF_WRITE and INTF_READ with the following: static void INTF_INIT(void) { lpspi_master_config_t userConfig; uint32_t srcFreq = 0; /*SPI configuration*/ LPSPI_MasterGetDefaultConfig(&userConfig); userConfig.baudRate = BOARD_NXPNCI_SPI_BAUDRATE; srcFreq = BOARD_NXPNCI_SPI_CLOCK; userConfig.whichPcs = (lpspi_which_pcs_t)kLPSPI_Pcs0; userConfig.pcsActiveHighOrLow = (lpspi_pcs_polarity_config_t)kLPSPI_PcsActiveLow; /*Initialize SPI*/ LPSPI_MasterInit(BOARD_NXPNCI_SPI_INSTANCE, &userConfig, srcFreq); } static status_t INTF_WRITE(uint8_t *pBuff, uint16_t buffLen) { uint8_t temp[1000]; temp[0] = 0x7F; memcpy(temp+1, pBuff, buffLen); masterXfer.txData = temp; masterXfer.rxData = NULL; masterXfer.dataSize = buffLen+1; masterXfer.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap;; return LPSPI_MasterTransferBlocking(BOARD_NXPNCI_SPI_INSTANCE, &masterXfer); } static status_t INTF_READ(uint8_t *pBuff, uint16_t buffLen) { status_t status; uint8_t temp[257]; temp[0] = 0xFF; masterXfer.txData = temp; masterXfer.rxData = temp; masterXfer.dataSize = buffLen+1; masterXfer.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap;; status = LPSPI_MasterTransferBlocking(BOARD_NXPNCI_SPI_INSTANCE, &masterXfer); if(status == kStatus_Success) memcpy(pBuff, temp+1, buffLen); SDK_DelayAtLeastUs(10, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); return status; } #endif   We also need to overwrite the functions: tml_Init, tml_DeInit and tml_Reset to adapt them to use the specific APIs for the GPIOs of our board. static Status tml_Init(void) { gpio_pin_config_t in_config = {kGPIO_DigitalInput, 0}; gpio_pin_config_t out_config = {kGPIO_DigitalOutput, 0}; GPIO_PinInit(BOARD_NXPNCI_IRQ_PORT, BOARD_NXPNCI_IRQ_PIN, &in_config); GPIO_PinInit(BOARD_NXPNCI_VEN_PORT, BOARD_NXPNCI_VEN_PIN, &out_config); GPIO_PinInit(BOARD_NXPNCI_DWL_PORT, BOARD_NXPNCI_DWL_PIN, &out_config); INTF_INIT(); return SUCCESS; } static Status tml_DeInit(void) { GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); return SUCCESS; } static Status tml_Reset(void) { /* Set DWL_REQ low for NCI protocol */ GPIO_PortClear(BOARD_NXPNCI_DWL_PORT, 1U << BOARD_NXPNCI_DWL_PIN); GPIO_PortClear(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); GPIO_PortSet(BOARD_NXPNCI_VEN_PORT, 1U << BOARD_NXPNCI_VEN_PIN); Sleep(10); return SUCCESS; }   Finally, modify the main file so it uses the APIs to initialize our board clocks and pins: #include <stdio.h> #include <string.h> #include "app.h" #include "board.h" #include "pin_mux.h" #include "fsl_debug_console.h" extern void nfc_example (void); int main(void) { BOARD_InitHardware(); #ifdef BOARD_NXPNCI_INTERFACE_I2C PRINTF("\nRunning the NXP-NCI2.0 example (I2C interface)\n"); #else PRINTF("\nRunning the NXP-NCI2.0 example (SPI interface)\n"); #endif nfc_example(); } Testing the example. At this point we have everything set to build and flash our example with SPI interface, you may proceed to build and debug/flash the example by pressing the blue beetle button: Once the example is flashed, open a serial terminal such as Teraterm with the following settings: Baudrate: 115200. Data: 8 bits. Parity: None. Stop bits: 1 bit. No flow control. While running, the example should output the following logs to the terminal: When a tag is placed near the antenna, the example should print the tag information in the terminal as shown:
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This post will cover how to install the CMSIS-DAP/SEGGER J-link firmware for the KW47-EVK and FRDM-MCXW72 using NXP’s MCU-LINK installer. CMSIS-DAP Installation for KW47-EVK Place a jumper on JP20 1-2 while the board is disconnected  Connect the board using a USB-A to USB-C cable between the host PC and the KW47-EVK board’s J14 connector, the D13 red LED should turn ON, indicating that the board is in ISP mode.                         Double click the script called program_CMSIS or program_JLINK  to execute the script. These scripts are found on the following path: C:\NXP\MCU-LINK_installer_3.167\scripts​ ​Note: MCU-Link installer version may vary. Press any key to execute the script, if the board entered ISP mode correctly, the board will be programmed with the selected debug probe firmware:    for FRDM-MCXW72  Place a jumper on JP5 1-2 while the board is disconnected    Connect the board using a USB-A to USB-C cable between the host PC and the FRDM-MCXW72 board’s J10 connector, the ISP_EN_ML INK red LED should turn ON, indicating that the board is in ISP mode.                                                              Double click the script called program_CMSIS to open the command window. This script is found on the following path:  C:\NXP\MCU-LINK_installer_3.167\scripts​​​  Note: MCU-Link installer version may vary.   Press any key to execute the script, if the board entered ISP mode correctly, the board will be programmed with the CMISIS-DAP firmware:                              Once the sequence finishes, the command window will display a completion message like the example below:    Remove the ISP jumper (JP5). Then reboot the board by disconnecting it from the host PC and reconnecting it again. After reconnecting, the ISP_EN_MLINK red LED should be OFF, and the USB_ACT green LED should be ON.    
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This pages is used to log key items related with KW4X products evaluation, development with SDK, power and RF performance evaluation, etc.
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As mentionned in the KW47/MCXW72 errata, a DCDC failure can occur infrequently during a drive strength change to low, and the DCDC output voltage becomes greater than or equal to the current output voltage. To avoid this particular case from happening, a software workaround can be implemented to make the voltage level at the low-power low drive-strength mode lower than the current output voltage of the DCDC. We will take the low power peripheral reference design demo application as example to show the workaround implementation. First of all, the default DCDC configuration in this demo project will never trigger this DCDC failure, because the DCDC is always in low drive-strength mode. To force it to the failure condition, we have to change the DCDC setting in board_dcdc.c. The DCDC configuration should be set to Normal drive strength mode, and the output voltage to 1.25V. BOARD_DCDC_config(kSPC_DCDC_NormalDriveStrength, kSPC_DCDC_LowUnderVoltage, false); The workaround requires the SPC high power mode to be enabled. SPC0->HP_CNFG_CTRL |= SPC_HP_CNFG_CTRL_HP_REQ_EN_MASK; The DCDC output voltage during high power mode is to set to 1.35V (higher than that of the active mode and low power mode): RF_CMC1->SPC_HP_CTRL |= 0x2U;   The SPC_HP mode is to be enabled just at the moment before going into low power mode. To do this, the nbu_ble project needs to be modified, and the NBU needs to be reprogrammed with this change. In the nbu_ble project, please modify the file fwk_platform_lowpower.c. The function PLATFORM_HandleLowPowerEntry manages the low power mode entry, thus we can add here: RF_CMC1->SPC_HP_CTRL |= 0x1U; //enable HP mode while ((RF_CMC1->SPC_HP_STAT && RF_CMC1_SPC_HP_STAT_SPC_HP_ACK_MASH) == 0); //wait for HP mode requested to be ackownledged RF_CMC1->SPC_HP_CTRL &= 0x0U; //disable HP mode while ((RF_CMC1->SPC_HP_STAT && RF_CMC1_SPC_HP_STAT_SPC_HP_ACK_MASH) == 0); //wait for HP mode requested to be ackownledged /* WFI will trigger low power entry procedure */ __DSB(); __WFI(); __ISB();   Please note that this workaround is valid for all wireless connectivity examples where low power mode is used. It does not apply to non-connectivity examples.    
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This document provides the calculation of the Bluetooth Low Power consumption linked to the setting of the Kinetis.   The Power Profile Calculator is build to provide the power consumption of your application. It's a mix between real measurements in voltage and temperature. The process is not taken into account which may create some variation.   DISCLAIMER: This excel workbook is provided as an estimation tool for NXP customers and is based on power profile measurements done on a set of randomly selected parts. A specific part may exhibit deviation from the nominal measurements used on this tool.   This document is the summary of all the information available in the AN12459 Power Consumption Analysis - FRDM-KW38 available in the NXP web page.   Several parameters could be fill-in: Buck or bypass mode (DCDC) Supply Voltage (2.4V to 3.6V) Temperature (-40°C to +105°C) Processor configuration (20MHz, 32MHz or 48MHz) 10 different deep sleep modes Different Tx output power (0dBm, +3.5dBm or +5dBm) Data rate (1Mbps, 2Mbps, 500kbps, 125kbps) Possibility to set the Advertising interval, connection interval, scan interval and active scan windows duration Fix the Bluetooth Packet sizes in Advertising and Connection  Tx/Rx payload.   One optional information is to provide an idea of the duration life time on 9 typical batteries.
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What's DPP? DPP:Device Provisioning Protocol It is also called: Wi-Fi Easy Connect.   The DUT is a device that needs to join the network. It actively initiates DPP authentication (Initiator + Enrollee), which is configured by CTT1, and finally joins the Wi-Fi network provided by CTT2 (Responder + AP) as a STA.   DPP Role introduction: CTT1 (Configurator) Reads DUT's bootstrap key Coordinates DPP Authentication/Configuration Sends Wi‑Fi credentials to the DUT DUT (Initiator + Enrollee + STA) Is the device being provisioned Initiates DPP Authentication toward CTT2 Receives Wi‑Fi credentials from CTT1 Connects as a STA to the AP on CTT2 CTT2 (Responder + AP + Enrollee) Responds to DUT’s DPP Authentication messages Operates as an AP using hostapd The DUT will join this AP after provisioning   Below is the process flow: 1.Add a Configurator and generate QR code on CTT1 (configurator). 2.Authenticate the DUT on DUT(STA) 3.Generate the QR Code and get URI on CTT2 4.Enter the QR Code on CTT1 and authenticate 5.Update AP configuration on CTT2 6.The connection between the DUT (STA) and CTT2 (AP) is successful.     Reference: https://docs.nxp.com/bundle/RM00297/page/connectivity-features/topics/wi-fi_easy_connect_dpp.html Wi-Fi Easy Connect Specification   The red fonts in the pdf are commands. The green fonts in the pdf are comments. CTT1:Configurator Typically, it's a mobile phone or PC used to scan QR codes and issue Wi-Fi credentials. IMX93-EVK+IW612 module   imx93evk login: root root@imx93evk:~# uname -a Linux imx93evk 6.12.34-lts-next-gbe78e49cb433 #1 SMP PREEMPT Wed Sep  3 05:59:19 UTC 2025 aarch64 GNU/Linux root@imx93evk:~# cat /lib/firmware/nxp/wifi_mod_para.conf     SDIW612 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=2 auto_ds=2 host_mlme=1 drv_mode=0x17 fw_name=nxp/sduart_nw61x_v1.bin.se }   root@imx93evk:~# vi wpa_supplicant.conf root@imx93evk:~# cat wpa_supplicant.conf ctrl_interface=/var/run/wpa_supplicant ctrl_interface_group=0 update_config=1 dpp_config_processing=2     modprobe moal mod_para=nxp/wifi_mod_para.conf   root@imx93evk:~# wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B & [1] 678 root@imx93evk:~# Successfully initialized wpa_supplicant rfkill: Cannot open RFKILL control device   [1]+  Done                    wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B root@imx93evk:~# root@imx93evk:~# root@imx93evk:~# wpa_cli wpa_cli v2.11-M005 Copyright (c) 2004-2024, Jouni Malinen <[email protected]> and contributors   This software may be distributed under the terms of the BSD license. See README for more details.     Selected interface 'mlan0'   Interactive mode   > DPP_CONFIGURATOR_ADD 1 > SET dpp_configurator_params " conf=sta-dpp configurator=1" OK > DPP_BOOTSTRAP_GEN type=qrcode chan=81/1 mac=fc:84:a7:51:87:fc //MAC address of CTT1 itself. 1 > DPP_BOOTSTRAP_GET_URI 1  //Attention here, after this command, will generate a QR code, which will be use on DUT with command:DPP_QR_CODE DPP:C:81/1;M:fc84a75187fc;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgAD/bYibd4JdGvnK1etdgX/z4P+aJE2ztv89Q8xwjmbZNc=;; > DPP_LISTEN 2412 role=configurator OK   //Hold on here, and now go to DUT side to authenticate the DUT with above QR Code. After authenticate on DUT, will auto output below logs.   <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=0 <3>DPP-TX dst=20:4e:f6:bb:08:d9 freq=2412 type=1 <3>DPP-TX-STATUS dst=20:4e:f6:bb:08:d9 freq=2412 result=SUCCESS <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=2 <3>DPP-AUTH-SUCCESS init=0 pkhash=74a40ec058ac8c7f7acb6589253e76f5d1a9582359353bcd5e6983ee97c3a382 own=1 peer=-1 <3>DPP-CONF-REQ-RX src=20:4e:f6:bb:08:d9 <3>DPP-BAND-SUPPORT 81,82,83,84,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130 <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=11 <3>DPP-CONF-SENT conf_status=0   //Now continue, after you generate the QR Code and get URI on CTT2. Enter the QR Code on CTT1 and authenticate: > DPP_QR_CODE DPP:C:81/1;M:02e93a0db8cd;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgACQOp5kWO1ex4L2U5rRXdS9yPYWA9NdRXTsuT+v5L/jvc=;; 2 //On successfully adding QR Code, a bootstrapping info id is returned as shown 2 in above command and should input in below command DPP_AUTH_INIT > DPP_AUTH_INIT peer=2 conf=ap-dpp configurator=1 OK //Now go to CTT2 to update AP configurations. <3>DPP-TX dst=02:e9:3a:0d:b8:cd freq=2412 type=0 <3>DPP-TX-STATUS dst=02:e9:3a:0d:b8:cd freq=2412 result=SUCCESS <3>DPP-RX src=02:e9:3a:0d:b8:cd freq=2412 type=1 <3>DPP-AUTH-DIRECTION mutual=0 <3>DPP-TX dst=02:e9:3a:0d:b8:cd freq=2412 type=2 <3>DPP-TX-STATUS dst=02:e9:3a:0d:b8:cd freq=2412 result=SUCCESS <3>DPP-AUTH-SUCCESS init=1 pkhash=22233c6d83a272944eeb9788870b0b564b46ba8d48fd80787f5cc22bcec95c87 own=-1 peer=2 <3>DPP-CONF-REQ-RX src=02:e9:3a:0d:b8:cd <3>DPP-RX src=02:e9:3a:0d:b8:cd freq=2412 type=11 <3>DPP-CONF-SENT conf_status=0     > list_networks network id / ssid / bssid / flags > quit root@imx93evk:~# cat /proc/mwlan/adapter0/mlan0/info driver_name = "wlan" driver_version = SDIW612---18.99.3.p26.7-MM6X18540.p7-(FP92) interface_name="mlan0" firmware_major_version=18.99.3 uuid = 1653948cf99e5b2bbe5ad9b851d6151a bss_mode ="Managed" media_state="Disconnected" mac_address="fc:84:a7:51:87:fc" multicast_count="2" essid="" bssid="00:00:00:00:00:00" channel="0" region_code = "00" multicast_address[0]="33:33:00:00:00:01" multicast_address[1]="01:00:5e:00:00:01" num_tx_bytes = 0 num_rx_bytes = 0 num_tx_pkts = 0 num_rx_pkts = 0 num_tx_pkts_dropped = 0 num_rx_pkts_dropped = 0 num_tx_pkts_err = 0 num_rx_pkts_err = 0 carrier off tx queue 0:  stopped tx queue 1:  stopped tx queue 2:  stopped tx queue 3:  stopped === tp_acnt.on:0 drop_point:0 === ====Tx accounting==== [0] Tx packets     : 0 [0] Tx packets last: 0 [0] Tx packets rate: 0 [0] Tx bytes       : 0 [0] Tx bytes last  : 0 [0] Tx bytes rate  : 0Mbps [1] Tx packets     : 0 [1] Tx packets last: 0 [1] Tx packets rate: 0 [1] Tx bytes       : 0 [1] Tx bytes last  : 0 [1] Tx bytes rate  : 0Mbps [2] Tx packets     : 0 [2] Tx packets last: 0 [2] Tx packets rate: 0 [2] Tx bytes       : 0 [2] Tx bytes last  : 0 [2] Tx bytes rate  : 0Mbps [3] Tx packets     : 0 [3] Tx packets last: 0 [3] Tx packets rate: 0 [3] Tx bytes       : 0 [3] Tx bytes last  : 0 [3] Tx bytes rate  : 0Mbps [4] Tx packets     : 0 [4] Tx packets last: 0 [4] Tx packets rate: 0 [4] Tx bytes       : 0 [4] Tx bytes last  : 0 [4] Tx bytes rate  : 0Mbps Tx amsdu cnt            : 0 Tx amsdu cnt last       : 0 Tx amsdu cnt rate       : 0 Tx amsdu pkt cnt        : 0 Tx amsdu pkt cnt last : 0 Tx amsdu pkt cnt rate : 0 Tx intr cnt             : 1 Tx intr last        : 0 Tx intr rate        : 0 Tx pending          : 0 Tx xmit skb realloc : 0 Tx stop queue cnt : 0 ====Rx accounting==== [0] Rx packets     : 0 [0] Rx packets last: 0 [0] Rx packets rate: 0 [0] Rx bytes       : 0 [0] Rx bytes last  : 0 [0] Rx bytes rate  : 0Mbps [1] Rx packets     : 0 [1] Rx packets last: 0 [1] Rx packets rate: 0 [1] Rx bytes       : 0 [1] Rx bytes last  : 0 [1] Rx bytes rate  : 0Mbps [2] Rx packets     : 0 [2] Rx packets last: 0 [2] Rx packets rate: 0 [2] Rx bytes       : 0 [2] Rx bytes last  : 0 [2] Rx bytes rate  : 0Mbps [3] Rx packets     : 0 [3] Rx packets last: 0 [3] Rx packets rate: 0 [3] Rx bytes       : 0 [3] Rx bytes last  : 0 [3] Rx bytes rate  : 0Mbps [4] Rx packets     : 0 [4] Rx packets last: 0 [4] Rx packets rate: 0 [4] Rx bytes       : 0 [4] Rx bytes last  : 0 [4] Rx bytes rate  : 0Mbps Rx amsdu cnt             : 0 Rx amsdu cnt last        : 0 Rx amsdu cnt rate        : 0 Rx amsdu pkt cnt         : 0 Rx amsdu pkt cnt last : 0 Rx amsdu pkt cnt rate : 0 Rx intr cnt      : 7 Rx intr last        : 0 Rx intr rate        : 0 Rx pending          : 0 Rx pause            : 0 Rx rdptr full cnt   : 0 root@imx93evk:~#     DUT:Initiator + Enrollee + STA The device you want it to join the network. IMX8MQ-EVK+88W8997 module     root@imx8mqevk:~# uname -a Linux imx8mqevk 6.12.49-lts-next-gdf24f9428e38 #1 SMP PREEMPT Fri Nov 21 03:24:46 UTC 2025 aarch64 GNU/Linux   root@imx8mqevk:~# cat /lib/firmware/nxp/wifi_mod_para.conf   PCIE8997 = {         cfg80211_wext=0xf         max_vir_bss=1         cal_data_cfg=none         ps_mode=1         auto_ds=1         host_mlme=1         fw_name=nxp/pcieuart8997_combo_v4.bin }     root@imx8mqevk:~# cat wpa_supplicant.conf ctrl_interface=/var/run/wpa_supplicant ctrl_interface_group=0 update_config=1 dpp_config_processing=2   root@imx8mqevk:~# modprobe moal mod_para=nxp/wifi_mod_para.conf     root@imx8mqevk:~# wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B & [1] 799 root@imx8mqevk:~# Successfully initialized wpa_supplicant rfkill: Cannot open RFKILL control device   [1]+  Done                    wpa_supplicant -i mlan0 -D nl80211 -c wpa_supplicant.conf -B root@imx8mqevk:~# wpa_cli wpa_cli v2.11-M005 Copyright (c) 2004-2024, Jouni Malinen <[email protected]> and contributors   This software may be distributed under the terms of the BSD license. See README for more details.     Selected interface 'mlan0'   Interactive mode   > DPP_QR_CODE DPP:C:81/1;M:fc84a75187fc;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgAD/bYibd4JdGvnK1etdgX/z4P+aJE2ztv89Q8xwjmbZNc=;; 1 > DPP_AUTH_INIT peer=1 role=enrollee OK <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=0 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc freq=2412 result=SUCCESS <3>DPP-RX src=fc:84:a7:51:87:fc freq=2412 type=1 <3>DPP-AUTH-DIRECTION mutual=0 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=2 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc freq=2412 result=SUCCESS <3>DPP-AUTH-SUCCESS init=1 pkhash=6785abbd108e5ef6fe780819634ef620fc6eb71715b92b07f393e58af7afa0b6 own=-1 peer=1 <3>GAS-QUERY-START addr=fc:84:a7:51:87:fc dialog_token=199 freq=2412 <3>GAS-QUERY-DONE addr=fc:84:a7:51:87:fc dialog_token=199 freq=2412 status_code=0 result=SUCCESS <3>DPP-CONF-RECEIVED <3>DPP-CONFOBJ-AKM dpp <3>DPP-CONFOBJ-SSID test <3>DPP-CONNECTOR eyJ0eXAiOiJkcHBDb24iLCJraWQiOiJWV0hoQmp0enJVZ0xTSjhpTTJDRmRtNkxPQ0FFWHVCSWJEU3hzMEhaSDhnIiwiYWxnIjoiRVMyNTYifQ.eyJncm91cHMiOlt7Imdyb3VwSWQiOiIqIiwibmV0Um9sZSI6InN0YSJ9XSwibmV0QWNjZXNzS2V5Ijp7Imt0eSI6IkVDIiwiY3J2IjoiUC0yNTYiLCJ4IjoibjBQbXlSMVhUUE14WUNiM2tqYjF1Yjh3Q055bUUtREFTcE4tZ2I0ZDhDcyIsInkiOiJfbmlkd1V6NkFkM1AySy1RYVJuXzZTem9KYlJWRGt3d0VYeTdZU2JoMDU4In19.kfVVpSaFNaTfoLVE5Yu16bLMfpSlVXGlul07FNwQ7gLPlYOTGS5lbOLwCTkP246kSC1Wn-8MWSUXpxgpSpsX2A <3>DPP-C-SIGN-KEY 3039301306072a8648ce3d020106082a8648ce3d0301070322000226d58dd75a168da8b901b47e01694868af2158d57db2984784349e12768e668b <3>DPP-PP-KEY 3039301306072a8648ce3d020106082a8648ce3d03010703220002a0008bd0723f2723408ef53550f5cbc55785ea625ec5265d81e16c0cd45a5e3a <3>DPP-NET-ACCESS-KEY 30770201010420cedd6e85e66768b1a8e14e2e048fd54b7f09277195c3db3f6b1887e8b449e872a00a06082a8648ce3d030107a144034200049f43e6c91d574cf3316026f79236f5b9bf3008dca613e0c04a937e81be1df02bfe789dc14cfa01ddcfd8af906919ffe92ce825b4550e4c30117cbb6126e1d39f <3>CTRL-EVENT-NETWORK-ADDED 0 <3>DPP-NETWORK-ID 0 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=11 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc freq=2412 result=SUCCESS <3>CTRL-EVENT-SCAN-STARTED <3>CTRL-EVENT-SCAN-RESULTS <3>WPS-AP-AVAILABLE <3>CTRL-EVENT-NETWORK-NOT-FOUND <3>CTRL-EVENT-SCAN-STARTED <3>CTRL-EVENT-SCAN-RESULTS <3>WPS-AP-AVAILABLE <3>CTRL-EVENT-NETWORK-NOT-FOUND <3>CTRL-EVENT-SCAN-STARTED <3>CTRL-EVENT-SCAN-RESULTS <3>WPS-AP-AVAILABLE <3>CTRL-EVENT-NETWORK-NOT-FOUND > DPP_STOP_LISTEN OK   //All commands on DUT side finished until here. Now go to CTT2 side to continue, generate the QR Code and get URI on CTT2.   <3>CTRL-EVENT-SCAN-RESULTS <3>DPP-TX dst=02:e9:3a:0d:b8:cd freq=2412 type=5 <3>DPP-TX-STATUS dst=02:e9:3a:0d:b8:cd freq=2412 result=SUCCESS <3>DPP-RX src=02:e9:3a:0d:b8:cd freq=2412 type=6 <3>PMKSA-CACHE-ADDED 02:e9:3a:0d:b8:cd 0 <3>DPP-INTRO peer=02:e9:3a:0d:b8:cd status=0 version=2 <3>SME: Trying to authenticate with 02:e9:3a:0d:b8:cd (SSID='test' freq=2412 MHz) <3>Trying to associate with 02:e9:3a:0d:b8:cd (SSID='test' freq=2412 MHz) <3>Associated with 02:e9:3a:0d:b8:cd <3>CTRL-EVENT-SUBNET-STATUS-UPDATE status=0 <3>EAPOL-RX 02:e9:3a:0d:b8:cd 99 <3>EAPOL-RX 02:e9:3a:0d:b8:cd 195 <3>WPA: Key negotiation completed with 02:e9:3a:0d:b8:cd [PTK=CCMP GTK=CCMP] <3>CTRL-EVENT-CONNECTED - Connection to 02:e9:3a:0d:b8:cd completed [id=0 id_str=] > list_networks network id / ssid / bssid / flags 0       test    any     [CURRENT] > quit root@imx8mqevk:~# cat /proc/mwlan/adapter0/mlan0/info driver_name = "wlan" driver_version = PCIE8997--16.92.21.p153.7-MM6X16540.p33-GPL-(FP92) interface_name="mlan0" firmware_major_version=16.92.21 bss_mode ="Managed" media_state="Connected" mac_address="20:4e:f6:bb:08:d9" multicast_count="4" essid="test" bssid="02:e9:3a:0d:b8:cd" channel="1" region_code = "00" multicast_address[0]="33:33:00:00:00:01" multicast_address[1]="01:00:5e:00:00:01" multicast_address[2]="33:33:ff:bb:08:d9" multicast_address[3]="33:33:00:00:00:fb" num_tx_bytes = 2458 num_rx_bytes = 350 num_tx_pkts = 19 num_rx_pkts = 3 num_tx_pkts_dropped = 0 num_rx_pkts_dropped = 0 num_tx_pkts_err = 0 num_rx_pkts_err = 0 carrier on tx queue 0:  started tx queue 1:  started tx queue 2:  started tx queue 3:  started === tp_acnt.on:0 drop_point:0 === ====Tx accounting==== [0] Tx packets     : 0 [0] Tx packets last: 0 [0] Tx packets rate: 0 [0] Tx bytes       : 0 [0] Tx bytes last  : 0 [0] Tx bytes rate  : 0Mbps [1] Tx packets     : 0 [1] Tx packets last: 0 [1] Tx packets rate: 0 [1] Tx bytes       : 0 [1] Tx bytes last  : 0 [1] Tx bytes rate  : 0Mbps [2] Tx packets     : 0 [2] Tx packets last: 0 [2] Tx packets rate: 0 [2] Tx bytes       : 0 [2] Tx bytes last  : 0 [2] Tx bytes rate  : 0Mbps [3] Tx packets     : 0 [3] Tx packets last: 0 [3] Tx packets rate: 0 [3] Tx bytes       : 0 [3] Tx bytes last  : 0 [3] Tx bytes rate  : 0Mbps [4] Tx packets     : 0 [4] Tx packets last: 0 [4] Tx packets rate: 0 [4] Tx bytes       : 0 [4] Tx bytes last  : 0 [4] Tx bytes rate  : 0Mbps Tx amsdu cnt            : 0 Tx amsdu cnt last       : 0 Tx amsdu cnt rate       : 0 Tx amsdu pkt cnt        : 0 Tx amsdu pkt cnt last : 0 Tx amsdu pkt cnt rate : 0 Tx intr cnt             : 18 Tx intr last        : 0 Tx intr rate        : 0 Tx pending          : 0 Tx xmit skb realloc : 19 Tx stop queue cnt : 0 ====Rx accounting==== [0] Rx packets     : 0 [0] Rx packets last: 0 [0] Rx packets rate: 0 [0] Rx bytes       : 0 [0] Rx bytes last  : 0 [0] Rx bytes rate  : 0Mbps [1] Rx packets     : 0 [1] Rx packets last: 0 [1] Rx packets rate: 0 [1] Rx bytes       : 0 [1] Rx bytes last  : 0 [1] Rx bytes rate  : 0Mbps [2] Rx packets     : 0 [2] Rx packets last: 0 [2] Rx packets rate: 0 [2] Rx bytes       : 0 [2] Rx bytes last  : 0 [2] Rx bytes rate  : 0Mbps [3] Rx packets     : 0 [3] Rx packets last: 0 [3] Rx packets rate: 0 [3] Rx bytes       : 0 [3] Rx bytes last  : 0 [3] Rx bytes rate  : 0Mbps [4] Rx packets     : 0 [4] Rx packets last: 0 [4] Rx packets rate: 0 [4] Rx bytes       : 0 [4] Rx bytes last  : 0 [4] Rx bytes rate  : 0Mbps Rx amsdu cnt             : 0 Rx amsdu cnt last        : 0 Rx amsdu cnt rate        : 0 Rx amsdu pkt cnt         : 0 Rx amsdu pkt cnt last : 0 Rx amsdu pkt cnt rate : 0 Rx intr cnt      : 67 Rx intr last        : 0 Rx intr rate        : 0 Rx pending          : 0 Rx pause            : 0 Rx rdptr full cnt   : 0 root@imx8mqevk:~#                       CTT2 (AP):Responder + AP + Enrollee IMX8MPlus EVK + 88W8997 module   root@imx8mpevk:~# uname -a Linux imx8mpevk 6.12.49-lts-next-gdf24f9428e38 #1 SMP PREEMPT Fri Nov 21 03:24:46 UTC 2025 aarch64 GNU/Linux       root@imx8mpevk:~# cat /lib/firmware/nxp/wifi_mod_para.conf   PCIE8997 = {         cfg80211_wext=0xf         max_vir_bss=1         cal_data_cfg=none         ps_mode=1         auto_ds=1         host_mlme=1         fw_name=nxp/pcieuart8997_combo_v4.bin }   root@imx8mpevk:~# hostapd hostapd.conf -B & [1] 1731 root@imx8mpevk:~# HT (IEEE 802.11n) with WPA/WPA2 requires CCMP/GCMP to be enabled, disabling HT capabilities rfkill: Cannot open RFKILL control device uap0: interface state UNINITIALIZED->ENABLED uap0: AP-ENABLED   [1]+  Done                    hostapd hostapd.conf -B root@imx8mpevk:~# hostapd_cli hostapd_cli v2.11-M005 Copyright (c) 2004-2024, Jouni Malinen <[email protected]> and contributors   This software may be distributed under the terms of the BSD license. See README for more details.     Selected interface 'uap0'   Interactive mode > DPP_BOOTSTRAP_GEN type=qrcode chan=81/1 mac=02:e9:3a:0d:b8:cd //MAC address of CTT2 itself and returned 1 is bootstrap info id which require to get QR code in below command. 1> DPP_BOOTSTRAP_GET_URI 1 //Attention here, after this command, will generate a QR code, which will be use on CTT1 with command:DPP_QR_CODE. Then directly go to CTT1 to enter the QR Code. DPP:C:81/1;M:02e93a0db8cd;V:2;K:MDkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDIgACQOp5kWO1ex4L2U5rRXdS9yPYWA9NdRXTsuT+v5L/jvc=;;>     //Hold on here, and now go to CTT1 to authenticate this AP with above QR Code. After authenticate on CTT1 with QR Code, will auto output below logs. Pay attention on the keys and connectors info, will use them later when you update the AP.   > <3>DPP-RX src=fc:84:a7:51:87:fc freq=2412 type=0 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=1 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc result=SUCCESS <3>DPP-RX src=fc:84:a7:51:87:fc freq=2412 type=2 <3>DPP-AUTH-SUCCESS init=0 pkhash=8b3e0f88b70610446a84f53ea9d792f5631b2b87e30cd219a8059c6f7893c501 own=1 peer=-1 <3>GAS-QUERY-START addr=fc:84:a7:51:87:fc dialog_token=0 freq=2412 <3>GAS-QUERY-DONE addr=fc:84:a7:51:87:fc dialog_token=0 freq=2412 status_code=0 result=SUCCESS <3>DPP-CONF-RECEIVED <3>DPP-CONFOBJ-AKM dpp <3>DPP-CONFOBJ-SSID test <3>DPP-CONNECTOR eyJ0eXAiOiJkcHBDb24iLCJraWQiOiJWV0hoQmp0enJVZ0xTSjhpTTJDRmRtNkxPQ0FFWHVCSWJEU3hzMEhaSDhnIiwiYWxnIjoiRVMyNTYifQ.eyJncm91cHMiOlt7Imdyb3VwSWQiOiIqIiwibmV0Um9sZSI6ImFwIn1dLCJuZXRBY2Nlc3NLZXkiOnsia3R5IjoiRUMiLCJjcnYiOiJQLTI1NiIsIngiOiJEbVRmSVFTRFNPVXVkVFBkN0pobEQtQ2xOa0U3U2lEWmctLWpYeGdNRXRJIiwieSI6Iml2NlVCc1J0YXhGSEpzcEtPbWFQSktqUmNDTFV5REh6WHFFeWtLbkhsOGcifX0.vEzfQywitO8AMvmcXenL_qidmkNl7t_jen2YW9OV8M5OID9jmTu-GqVUUkMEQE7R7Ja5vGnOMQ2-x-h7qyRKIQ <3>DPP-C-SIGN-KEY 3039301306072a8648ce3d020106082a8648ce3d0301070322000226d58dd75a168da8b901b47e01694868af2158d57db2984784349e12768e668b <3>DPP-NET-ACCESS-KEY 307702010104200be4b069c34a39d844fca856dd1e583a729e74f394370a4da8bc7d68d0dfadc2a00a06082a8648ce3d030107a144034200040e64df21048348e52e7533ddec98650fe0a536413b4a20d983efa35f180c12d28afe9406c46d6b114726ca4a3a668f24a8d17022d4c831f35ea13290a9c797c8 <3>DPP-TX dst=fc:84:a7:51:87:fc freq=2412 type=11 <3>DPP-TX-STATUS dst=fc:84:a7:51:87:fc result=SUCCESS   //Now update AP configurations on CTT2: //First disable AP: > disable <3>AP-DISABLED OK   //Update AP parameters: > set ssid test OK > set wpa 2 OK > set wpa_key_mgmt DPP OK > set ieee80211w 2 OK > set rsn_pairwise CCMP OK > set dpp_connector eyJ0eXAiOiJkcHBDb24iLCJraWQiOiJWV0hoQmp0enJVZ0xTSjhpTTJDRmRtNkxPQ0FFWHVCSWJEU3hzMEhaSDhnIiwiYWxnIjoiRVMyNTYifQ.eyJncm91cHMiOlt7Imdyb3VwSWQiOiIqIiwibmV0Um9sZSI6ImFwIn1dLCJuZXRBY2Nlc3NLZXkiOnsia3R5IjoiRUMiLCJjcnYiOiJQLTI1NiIsIngiOiJEbVRmSVFTRFNPVXVkVFBkN0pobEQtQ2xOa0U3U2lEWmctLWpYeGdNRXRJIiwieSI6Iml2NlVCc1J0YXhGSEpzcEtPbWFQSktqUmNDTFV5REh6WHFFeWtLbkhsOGcifX0.vEzfQywitO8AMvmcXenL_qidmkNl7t_jen2YW9OV8M5OID9jmTu-GqVUUkMEQE7R7Ja5vGnOMQ2-x-h7qyRKIQ OK > set dpp_csign 3039301306072a8648ce3d020106082a8648ce3d0301070322000226d58dd75a168da8b901b47e01694868af2158d57db2984784349e12768e668b OK > set dpp_netaccesskey 307702010104200be4b069c34a39d844fca856dd1e583a729e74f394370a4da8bc7d68d0dfadc2a00a06082a8648ce3d030107a144034200040e64df21048348e52e7533ddec98650fe0a536413b4a20d983efa35f180c12d28afe9406c46d6b114726ca4a3a668f24a8d17022d4c831f35ea13290a9c797c8 OK   //Re-enable the AP after updates: > enable <3>AP-ENABLED OK   //just wait here, it will output below logs after some seconds. > <3>DPP-RX src=20:4e:f6:bb:08:d9 freq=2412 type=5 <3>DPP-TX dst=20:4e:f6:bb:08:d9 freq=2412 type=6 status=0 <3>DPP-TX-STATUS dst=20:4e:f6:bb:08:d9 result=SUCCESS <3>AP-STA-CONNECTED 20:4e:f6:bb:08:d9 dpp_pkhash=74a40ec058ac8c7f7acb6589253e76f5d1a9582359353bcd5e6983ee97c3a382 <3>EAPOL-4WAY-HS-COMPLETED 20:4e:f6:bb:08:d9 > quit > root@imx8mpevk:~# cat /proc/mwlan/adapter0/uap0/info driver_name = "uap" driver_version = PCIE8997--w8997o-V4, RF878X, FP92, 16.92.21.p153.7-MM6X16540.p33-GPL-(FP92) interface_name="uap0" firmware_major_version=16.92.21 media_state="Connected" mac_address="02:e9:3a:0d:b8:cd" num_tx_bytes = 462 num_rx_bytes = 2248 num_tx_pkts = 4 num_rx_pkts = 20 num_tx_pkts_dropped = 0 num_rx_pkts_dropped = 0 num_tx_pkts_err = 60 num_rx_pkts_err = 0 carrier on tx queue 0:  started tx queue 1:  started tx queue 2:  started tx queue 3:  started tkip_mic_failures = 0 ccmp_decrypt_errors = 0 wep_undecryptable_count = 0 wep_icv_error_count = 0 decrypt_failure_count = 0 mcast_tx_count = 20 failed_count = 3 retry_count = 0 multiple_retry_count = 0 frame_duplicate_count = 0 rts_success_count = 0 rts_failure_count = 0 ack_failure_count = 30 rx_fragment_count = 55 mcast_rx_frame_count = 18 fcs_error_count = 401368 tx_frame_count = 22 rsna_tkip_cm_invoked = 0 rsna_4way_hshk_failures = 0 === tp_acnt.on:0 drop_point:0 === ====Tx accounting==== [0] Tx packets     : 0 [0] Tx packets last: 0 [0] Tx packets rate: 0 [0] Tx bytes       : 0 [0] Tx bytes last  : 0 [0] Tx bytes rate  : 0Mbps [1] Tx packets     : 0 [1] Tx packets last: 0 [1] Tx packets rate: 0 [1] Tx bytes       : 0 [1] Tx bytes last  : 0 [1] Tx bytes rate  : 0Mbps [2] Tx packets     : 0 [2] Tx packets last: 0 [2] Tx packets rate: 0 [2] Tx bytes       : 0 [2] Tx bytes last  : 0 [2] Tx bytes rate  : 0Mbps [3] Tx packets     : 0 [3] Tx packets last: 0 [3] Tx packets rate: 0 [3] Tx bytes       : 0 [3] Tx bytes last  : 0 [3] Tx bytes rate  : 0Mbps [4] Tx packets     : 0 [4] Tx packets last: 0 [4] Tx packets rate: 0 [4] Tx bytes       : 0 [4] Tx bytes last  : 0 [4] Tx bytes rate  : 0Mbps Tx amsdu cnt            : 0 Tx amsdu cnt last       : 0 Tx amsdu cnt rate       : 0 Tx amsdu pkt cnt        : 0 Tx amsdu pkt cnt last : 0 Tx amsdu pkt cnt rate : 0 Tx intr cnt             : 22 Tx intr last        : 0 Tx intr rate        : 0 Tx pending          : 0 Tx xmit skb realloc : 64 Tx stop queue cnt : 0 ====Rx accounting==== [0] Rx packets     : 0 [0] Rx packets last: 0 [0] Rx packets rate: 0 [0] Rx bytes       : 0 [0] Rx bytes last  : 0 [0] Rx bytes rate  : 0Mbps [1] Rx packets     : 0 [1] Rx packets last: 0 [1] Rx packets rate: 0 [1] Rx bytes       : 0 [1] Rx bytes last  : 0 [1] Rx bytes rate  : 0Mbps [2] Rx packets     : 0 [2] Rx packets last: 0 [2] Rx packets rate: 0 [2] Rx bytes       : 0 [2] Rx bytes last  : 0 [2] Rx bytes rate  : 0Mbps [3] Rx packets     : 0 [3] Rx packets last: 0 [3] Rx packets rate: 0 [3] Rx bytes       : 0 [3] Rx bytes last  : 0 [3] Rx bytes rate  : 0Mbps [4] Rx packets     : 0 [4] Rx packets last: 0 [4] Rx packets rate: 0 [4] Rx bytes       : 0 [4] Rx bytes last  : 0 [4] Rx bytes rate  : 0Mbps Rx amsdu cnt             : 0 Rx amsdu cnt last        : 0 Rx amsdu cnt rate        : 0 Rx amsdu pkt cnt         : 0 Rx amsdu pkt cnt last : 0 Rx amsdu pkt cnt rate : 0 Rx intr cnt      : 28229 Rx intr last        : 0 Rx intr rate        : 0 Rx pending          : 0 Rx pause            : 0 Rx rdptr full cnt   : 0 root@imx8mpevk:~#            
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Blue Ravens (Bluetooth Ranging Access Vehicle Enablement System) is a system solution developed by NXP to assist customers in designing their own BLE-based car access solutions using NXP products. It is designed to support a variety of car access use cases through a modular approach. The main objective (but not limited) is to present all the capabilities and advantages of the Channel Sounding technology and NXP BLE Handover in an automotive use case. Channel Sounding is part of the new Bluetooth Low Energy (BLE) standard (BLE 6.0) as a highly accurate distance measurement solution, and available on the NXP KW47 chip. BLE Handover is an NXP proprietary feature developed by NXP to seamlessly transfer a BLE connection from one device to another, without disconnection, using and out of band channel (e.g. CAN). This transfer does not impact the peer device so interoperability is guaranteed. This feature can also be used to enable BLE connection RSSI sniffing to increase RSSI based system security. (KW45 & KW47) Thanks to its modularity, this system can be used to address multiple use-cases, from simple BLE connection system, up to a full BLE Channel Sounding positioning system. Please, note that Channel Sounding is only supported on KW47 chip. KW45 can only be used for simple BLE system. By default, the system on KW47 covers a basic use of Channel Sounding to measure the distance between one remote device (Digital Key) and alternatively several different fixed devices (Car Anchor). At each instant in time, only one anchor is connected to the Digital Key. The other anchors (not connected) can be set in Connection RSSI Sniffing mode (based on Handover). This mode increase the system security by accessing the RSSI value of a connection instead of an advertising packet. These RSSI values can be used to estimated which anchor can be used in the round-robin or to keep the best BLE link around the Car.     The system is composed of multiple KW4x boards, each with a specific role. On board is used as Digital Key, to be caried by the user, the other represent the Car sub-system. On this Car Sub-system, all boards are connected to each other using the CAN bus. The CAN bus fulfills the purpose to power all boards with 12V and to allow communication between the boards: Control Unit (KW4x EVK-Board) Car Anchors (KW4x LOC-Board) Digital Key (KW4x LOC-Board) Role: Central decision-making node Functionality: - Coordinates BLE anchors. - Triggers actions based on received data   Role: BLE devices connected to the Control Unit via CAN bus Functionality: - Advertise BLE presence. - Wait for a Digital Key to connect. - Act as CS initiators during the session. Role: Acts as the remote BLE device Functionality: - Scans for BLE anchors. - Initiates connection with a Car Anchor. - Once connected, behaves as a CS reflector.     A Desktop application is used to monitor the states and monitor the measurement done by the system:   Using the successive measurement on each anchors, the Car sub-system is able to estimate the Digital Key position (Disclaimer: this solution is not consider accurate in dynamic environments)       Features   BLE connection Supporting 1 connection only for now (multiple peer plan) BLE Channel Sounding (KW47 only) Yes RSSI Sniffing Yes – All not connected anchors Automatic exclusion of suboptimal anchors Yes BLE Handover with CS context (No CS repeat) Yes Trilateration algorithm Yes Measurement filtering (real time) Yes Detection area triggering action (e.g. Welcome zone) Yes Car Anchor CAN Synchronization (radio core sync) No (planned for next release) Channel Sounding Sniffing No (feasibility study ongoing)   KPIs   Number of Anchor From 2 to 8 Number of Digital Key 1 BLE Connection Interval 7.5ms – 4s (Default = 30ms) BLE Handover connection transfer time (+CS context transfer) <60ms (CI=30ms) <50ms (CI=10ms) CS start Delay (2+7)*CI CS measurement and data transfer (Real Time) <70ms (CI=30ms) CS Algo <30ms Full cycle time (CS + Handover) [Algorithm runs asynchronously on the anchor after the handover is finished] 390ms (CI=30ms) 190ms (CI=10ms) Line Of Sight CS measurement range 100m Max (at 10dBm) Back Pocket CS measurement range 10m (at 10dB)   This solution is under development and improvement will be added in the future releases. This system can also be enhanced with Ultra-Wide Band support. Videos For access, please contact [email protected]  
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Most available example applications use UART as the serial interface for terminal communication. This approach is commonly chosen because a terminal provides a simple and efficient method for interacting with the application during development and debugging. The KW47-EVK supports two CAN/CAN-FD interface; as well as two UART interfaces accessible through the onboard USB-to-UART bridge.  The corresponding SoC peripheral instances are CAN0 and CAN1 for the CAN/CAN‑FD interfaces, and LPUART0 and LPUART1 for the UART interfaces. Since the LPUART1 serial interface and the CAN1 interface are routed to the same pins (PTC2 and PTC3) at the board level, and both functions can be enabled through header configuration, external isolation is required to ensure correct operation and prevent interference from other onboard components. If CAN1 must be enabled and your application also requires a serial terminal interface, then LPUART0 must be used as the serial interface.To enable both CAN1 and LPUART0 on the KW47‑EVK, follow the steps below: Changes required on hardware CAN Node A CAN Node B Pin name Board jumper Pin name Board jumper CANH J21 - 1 CANH J21 - 1 CANL J21 - 2 CANL J21 - 2 GND J21 - 4 GND J21 - 4 P12V J21 - 3 P12V J21 - 3  Note: Plug in the 12V power supply on J9 to supply the P5V_CAN. LPUART0 interface connection Functionality Board jumper Connection configuration LIN_RX JP11 2 - 3 LIN_TX JP12 2 - 3 UART_RX_USB selector JP16 2 - 3 UART_TX_USB selector JP17 2 - 3 CAN_RX_1 selector JP56 1 - 2 CAN_TX_1 selector JP57 1 - 2   Changes required on software Note: These steps assume you are using a FlexCAN SDK example application. If your application requires enabling CAN1 instead of the default CAN0, update the following configuration in your project’s source code: 1. In board.c, modify the LPUART instance, kCLOCK_Lpuart1 -> kCLOCK_Lpuart0: /* Initialize debug console. */ void BOARD_InitDebugConsole(void) { uint32_t uartClkSrcFreq = 0U; /* Set LPUART0 clock source */ CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFro192M); uartClkSrcFreq = CLOCK_GetIpFreq(kCLOCK_Lpuart0); DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); } 2. In board.h, modify the LPUART instance definitions: BOARD_DEBUG_UART_BASEADDR LPUART1 -> LPUART0 BOARD_DEBUG_UART_INSTANCE 1U -> 0U BOARD_DEBUG_UART_CLK_FREQ kCLOCK_Lpuart1 -> kCLOCK_Lpuart0 /* The UART to use for debug messages. */ #define BOARD_USE_LPUART #define BOARD_DEBUG_UART_TYPE kSerialPort_Uart #define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0 #define BOARD_DEBUG_UART_INSTANCE 0U #define BOARD_DEBUG_UART_CLK_FREQ (CLOCK_GetIpFreq(kCLOCK_Lpuart0)) 3. In hardware_init.c, modify the CAN instance to CAN1 at FlexCAN functional clock configuration: void BOARD_InitHardware(void) { BOARD_InitPins(); BOARD_BootClockRUN(); BOARD_InitDebugConsole(); /* FRO192M is configured as CAN1 functional clock in this example but other clock options may be available */ CLOCK_SetIpSrc(kCLOCK_Can1, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Can1, kSCG_SysClkDivBy1); } 4. In app.h, modify the EXAMPLE_CAN definition to CAN1: #define EXAMPLE_CAN CAN1 #define USE_CANFD (1) #define RX_MESSAGE_BUFFER_NUM (0) #define TX_MESSAGE_BUFFER_NUM (1) 5. In pin_mux.c, modify pin multiplexing configuration to enable CAN1 and LPUART0 pins respectively. You can copy and paste the below code to replace BOARD_InitPins function: void BOARD_InitPins(void) { /* Clock Config: Peripheral clocks are enabled; module does not stall low power mode entry */ CLOCK_EnableClock(kCLOCK_PortA); CLOCK_EnableClock(kCLOCK_PortC); const port_pin_config_t porta16_pin11_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_RX */ (uint16_t)kPORT_MuxAlt6, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA16 (pin 11) is configured as LPUART0_RX */ PORT_SetPinConfig(PORTA, 16U, &porta16_pin11_config); const port_pin_config_t porta17_pin12_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as LPUART0_TX */ (uint16_t)kPORT_MuxAlt6, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTA17 (pin 12) is configured as LPUART0_TX */ PORT_SetPinConfig(PORTA, 17U, &porta17_pin12_config); const port_pin_config_t portc2_pin39_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as CAN1_RX */ (uint16_t)kPORT_MuxAlt11, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC2 (pin 39) is configured as CAN1_RX */ PORT_SetPinConfig(PORTC, 2U, &portc2_pin39_config); const port_pin_config_t portc3_pin40_config = {/* Internal pull-up/down resistor is disabled */ (uint16_t)kPORT_PullDisable, /* Low internal pull resistor value is selected. */ (uint16_t)kPORT_LowPullResistor, /* Fast slew rate is configured */ (uint16_t)kPORT_FastSlewRate, /* Passive input filter is disabled */ (uint16_t)kPORT_PassiveFilterDisable, /* Open drain output is disabled */ (uint16_t)kPORT_OpenDrainDisable, /* Low drive strength is configured */ (uint16_t)kPORT_LowDriveStrength, /* Normal drive strength is configured */ (uint16_t)kPORT_NormalDriveStrength, /* Pin is configured as CAN1_TX */ (uint16_t)kPORT_MuxAlt11, /* Does not invert */ (uint16_t)kPORT_InputNormal, /* Pin Control Register fields [15:0] are not locked */ (uint16_t)kPORT_UnlockRegister}; /* PORTC3 (pin 43) is configured as CAN1_TX */ PORT_SetPinConfig(PORTC, 3U, &portc3_pin40_config); } Run your demo application Connect a USB cable between the host PC and the KW47-EVK board J14. Open a serial terminal on PC for each board with the following settings: 115200 baud rate 8 data bits No parity One stop bit No flow control Download the program to the target board Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
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Channel Sounding 
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    As the support for MCUXpresso IDE as GUI and toolchain will be stopped and will be replaced by MCUXpresso for Visual Studio Code, I am sharing here some essential steps to start development on Visual Studio Code and MCUXpresso plugin. Preparation: - MCUXpresso for VS Code is installed as an extension inside Microsoft VS Code - see https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC - The rest of the toolchain including ARMGCC, west and other tools which work with MCUX for VS Code installation is available via MCUXpresso SDK option of the MCUXpresso Installer: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-installer:MCUXPRESSO-INSTALLER - See also generic Getting Started Guide for MCUX SDK with MCUX for VS Code at: https://mcuxpresso.nxp.com/mcuxsdk/latest/html/gsd/run_a_demo_using_mcuxvsc.html   Here I will provide the procedure to import the loc_reader example from the repository.   Import the repository: The recommended approach is to import REMOTE ARCHIVE which has a similar environment as the legacy MCUXpresso IDE. Here I will provide the procedure to import the loc_reader example from the repository From the MCUXpresso plugin, select "Import Repository", then in the "REMOTE ARCHIVE" tab, select the board, the SDK version and the location: Wait for the repository to be imported, this procedure can take several minutes. Once the import is succeed, it will appear here: Import demo projects and run: Once the repository is successfully imported, you can then import demo examples from the repo by selecting "Import Example from Repository": then select the demo example from "Template". "AppType" should be "Freestanding application" if you want a standalone project. "Location" is where the project will be located.  "Toolchain" should be the Arm GNU one that you installed in preparation steps Build and run the imported project:  
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Hello, all, Bellow you can find the necessary steps to enable dual monitor mode on our Wi-Fi chip: 88W9098. This procedure is helpful for using 88W9098's dual interfaces in monitor mode to simultaneously capture Wi-Fi sniffer logs in different band . Below is my test environment: Hardware: I.MX8MQ-EVK M.2 AzureWave PCIe XM458 module Software: Linux kernel version: L6.6.52 (prebuilt image for I.MX8MQ-EVK) Device Tree: imx8mq-evk-pcie1-m2.dtb Wi-Fi/BT Driver & Firmware: Version: PCIE9098--17.92.1.p149.81-MM6X17540.p33-(FP92) Firmware: nxp/pcieuart9098_combo_v1.bin Configuration: Edit wifi_mod_para.conf and add: mon_filter=0x27 max_vir_bss=2 Example configuration: PCIE9098_0 = { cfg80211_wext=0xf max_vir_bss=2 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 mon_filter=0x27 fw_name=nxp/pcieuart9098_combo_v1.bin } PCIE9098_1 = { cfg80211_wext=0xf max_vir_bss=2 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 mon_filter=0x27 fw_name=nxp/pcieuart9098_combo_v1.bin } Compile tcpdump Compile libpcap: wget https://www.tcpdump.org/release/libpcap-1.10.4.tar.gz tar -xvf libpcap-1.10.4.tar.gz cd libpcap-1.10.4 ./configure --host=arm-linux-gnueabihf --prefix=/opt/tcpdump make Output: libpcap.so.1.10.4 Compile tcpdump: wget https://www.tcpdump.org/release/tcpdump-4.99.4.tar.gz tar -xvf tcpdump-4.99.4.tar.gz cd tcpdump-4.99.4/ ./configure --host=arm-linux-gnueabihf --prefix=/opt/tcpdump --with-pcap=/opt/tcpdump make Output: tcpdump Deploy to Board: Copy libpcap.so.1.10.4 and tcpdump to the board Add execute permission: chmod +x tcpdump Dual Monitor Mode on 88W9098 Load the Wi-Fi drivers and firmware: modprobe moal mod_para=nxp/wifi_mod_para.conf Monitor Interface Setup 5 GHz (mlan0): iw mlan0 interface add mon0 type monitor ip link set mon0 up ip link set mlan0 down iw mon0 set channel 36 ./tcpdump -i mon0 -w capture_5g.pcap & ./tcpdump -r capture_5g.pcap 2.4 GHz (mmlan0): iw mmlan0 interface add mon1 type monitor ip link set mon1 up ip link set mmlan0 down iw mon1 set channel 6 ./tcpdump -i mon1 -w capture_2g.pcap & ./tcpdump -r capture_2g.pcap Simultaneous Capture ./tcpdump -i mon0 -w capture_5g.pcap & ./tcpdump -i mon1 -w capture_2g.pcap & Stop Capture killall tcpdump Read Captures ./tcpdump -r capture_5g.pcap ./tcpdump -r capture_2g.pcap Reference link: https://docs.nxp.com/bundle/RM00297/page/connectivity-features/topics/monitor_mode.html   Best regards, Christine.
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In daily work, many customers are asking how to develop Mifare Desfire EV3. Yes, it is true that the Mifare Desfire EV3 is a highly secure product, and the related application documents are complicated and difficult for customers to use or take too much time to research, so I want to share them with you.
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Using the Signal Frequency Analyzer (SFA) to Measure the FRO 6M Frequency Overview The Signal Frequency Analyzer (SFA) is a specialized hardware peripheral available in NXP’s KW45, MCXW71 microcontrollers. It is designed to provide precise, real-time measurement and analysis of digital signal characteristics, including frequency, period, and timing intervals. This makes it a valuable tool for applications requiring accurate timing diagnostics, signal validation, and system debugging. By utilizing internal 32-bit counters and configurable trigger mechanisms, the SFA enables high-resolution capture of signal transitions, supporting robust system monitoring and fault detection. Functional Capabilities of the SFA The SFA module supports the following measurements: Clock signal frequency of a Clock Under Test (CUT) Clock signal period It operates using two 32-bit counters: One for the Reference Clock (REF) One for the Clock Under Test (CUT) Measurement is performed by comparing the counts of both clocks until predefined target values are reached. FRO 6M Frequency Failure Scenarios The 6 MHz Free Running Oscillator (FRO6M) may occasionally output an incorrect frequency under certain conditions: When the device exits reset When the device wakes from low-power modes To mitigate potential issues caused by incorrect FRO6M output, it is the application developer’s responsibility to verify the oscillator’s frequency and apply corrective measures as needed. Monitoring the FRO 6M Using the SFA To monitor the FRO6M signal, the following configuration is recommended: SFA Configuration Parameters Reference Clock (REF): CPU Clock (e.g., 96 MHz) Clock Under Test (CUT): FRO6M routed via CLKOUT Interrupt Mode: Enabled for asynchronous measurement completion Code Implementation The presented functions are meant to be implemented in users application, the inner functions are part of the implementations of the SFA driver from the NXP’s SDK. It can be used on MCXW71, KW45 just make sure SFA Peripheral Initialization  void init_SFA_peripheral(void) { /* Enable SFA interrupt. */ EnableIRQ(SFA_IRQn); /* Set SFA interrupt priority. */ NVIC_SetPriority(SFA_IRQn, 1); SFA_Init(DEMO_SFA_BASEADDR); SFA_InstallCallback(DEMO_SFA_BASEADDR, EXAMPLE_SFA_CALLBACK); } SFA Callback Function void EXAMPLE_SFA_CALLBACK(status_t status) { if (status == kStatus_SFA_MeasurementCompleted) { SfaMeasureFinished = true; } sfa_callback_status = status; } Frequency Measurement Function This function sets up the measurement of the FRO6M signal using the CPU clock as the reference. uint8_t SFA_freq_measurement_6M_FRO(void) { uint8_t ratio = 0; uint32_t freq = 0UL; sfa_config_t config; CLOCK_SetClkOutSel(kClockClkoutSelSirc); //set clokout to SIRC SFA_GetDefaultConfig(&config); //Get SFA default config config.mode = kSFA_FrequencyMeasurement0; config.refSelect = kSFA_REFSelect1; //Set CPU clk as ref clk config.cutSelect = kSFA_CUTSelect1; //Set clkout as CUT config.refTarget = 0xFFFFFFUL; config.cutTarget = 0xFFFFUL; config.enableCUTPin = true; freq = get_ref_freq_value(CPU_CLK); SFA_SetMeasureConfig(DEMO_SFA_BASEADDR, &config); SFA_MeasureNonBlocking(DEMO_SFA_BASEADDR); while (1) { if (SfaMeasureFinished) { SfaMeasureFinished = false; if(kStatus_SFA_MeasurementCompleted == sfa_callback_status) { freq = SFA_CalculateFrequencyOrPeriod(DEMO_SFA_BASEADDR, freq);//Calculate the FRO freq if(FREQ_6MHZ + TOLERANCE <= freq ) { ratio = 1; } else { if(FREQ_3MHZ + TOLERANCE <= freq) { ratio = 2; } else { if(FREQ_2MHZ + TOLERANCE <= freq) { ratio = 3; } else { ratio = 4; } } } break; } } else { __WFI(); } } return ratio; } Result Interpretation and Usage To test the FRO 6M after adding the above functions the FRO can be tested after executing: init_SFA_peripheral(); SFA_freq_measurement_6M_FRO(); The measured FRO6M frequency ratio is returned by the function SFA_freq_measurement_6M_FRO(), with the ratio you can know the current frequency output of the 6M FRO, ration 1 means 6M are being output by the FRO, ratio 2 means the frequency output of the FRO it's being cut in half meaning the FRO is outputting 3 Mhz, ration 3 means the FRO output frequency is being cut by a third part, this results in 2MHz frequency output. With this information you can: Adapt peripheral clocking if the FRO6M frequency is incorrect (This can be achieve by modifying the peripheral dividers if dividers are being used). Trigger corrective actions such as  switching to an alternate clock source Steps to Reconfigure Peripheral Clocking When FRO6M output frequency is lower Detect the Faulty FRO6M Output Use the SFA measurement as described earlier to determine if the FRO6M is operating below its expected frequency (6 MHz). If the result is significantly lower, proceed to reconfigure. Choose an Alternative Clock Source Most NXP MCUs offer multiple internal and external clock sources. Common alternatives include: FRO 192M OSC RF 32M Sys OSC RTC OSC Choose one that is: Stable Available in your current power mode Compatible with the peripheral’s timing requirements You can add more clock divers if needed to make a higher frequency clock reach a certain lower frequency. Reconfigure the Peripheral Clock Source Use the SDK’s CLOCK_Set... APIs to change the clock source. You may also need to: Adjust dividers to match the required baud rate or timing Reinitialize the peripheral with the new clock settings Example Scenario: Measuring the FRO and Adjusting UART Based on Frequency Ratio Imagine your application relies on the 6 MHz Free Running Oscillator (FRO), and its accuracy directly affects UART communication. To ensure reliable operation, you can use the System Frequency Adjustment (SFA) feature to monitor the FRO output and dynamically adjust the UART configuration. After measuring the 6 MHz FRO using the recommended method, the system returns a frequency ratio value. This value ranges from 1 to 4, where: 1 indicates the frequency is within expected limits (no issues), 2 to 4 represent varying degrees of deviation from the expected frequency. Using this ratio, you can initialize and configure the UART peripheral and its driver to compensate for any frequency variation, ensuring stable and accurate communication. */ int main(void) { BOARD_InitHardware(); uint8_t ch = 0; uint8_t FRO_ratio = 0; init_SFA_peripheral(); /*Measure FRO6M output frequency*/ FRO_ratio = SFA_freq_measurment_6M_FRO(); /*Init debug console and compensate in case a different frequency is output */ if(0 == FRO_ratio) { assert(0);//this user defined return value means something went wrong while measuring 6Mz FRO } uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ/FRO_ratio;//Compensate the src frequency set for uart module CLOCK_EnableClock(kCLOCK_Lpuart1); CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFro6M); DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); ...... } SDK 25.0.00 Enhancements for FRO6M Calibration To address known reliability issues with the 6 MHz Free Running Oscillator (FRO6M), particularly during transitions from low-power modes, SDK version 25.06.00 introduces a set of software enhancements aimed at improving oscillator validation and calibration. Key Features Introduced FRO6M Calibration API Two new functions have been added to facilitate runtime verification of the FRO6M frequency: PLATFORM_StartFro6MCalibration() Initializes the calibration process by enabling the cycle counter, capturing a timestamp, and preparing the system to measure elapsed time using both the CPU and the FRO6M-based timestamp counter. PLATFORM_EndFro6MCalibration() Completes the calibration by comparing the time measured via CPU cycles and the FRO6M timestamp counter. This comparison determines whether the oscillator is operating at the expected 6 MHz or has erroneously locked to a lower frequency (e.g., 2 MHz). The result is stored in a global ratio variable (fwk_platform_FRO6MHz_ratio) for use by the system. These functions provide a lightweight and efficient mechanism to detect and respond to oscillator misbehavior, ensuring system stability and timing accuracy. Configuration Macro gPlatformEnableFro6MCalLowpower_d This macro enables automatic FRO6M frequency verification upon exiting low-power modes. When defined, the system will invoke the calibration functions to validate the oscillator before resuming normal operation. Default Integration The calibration mechanism is enabled by default in the SDK configuration file fwk_config.h, ensuring that all applications benefit from this safeguard without requiring manual setup. Use Case and Benefits These enhancements are particularly valuable in applications where: Precise timing is critical (e.g., wireless communication, sensor sampling). The system frequently enters and exits low-power states. Clock source integrity must be guaranteed to avoid peripheral misbehavior or timing faults. By integrating these calibration routines, developers can proactively detect and correct FRO6M frequency anomalies, improving overall system robustness and reducing the risk of runtime errors due to clock instability.  
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This article shares 2 step by step methods to create P2P connections between 2 IW612 modules. One is not setting pin code, another is setting pin code. And also shares local test results and printed logs for your reference. The basic environment: Hardware: 2 IW612 modules(Murata LBES5PL2EL) + I.MX93-EVK Software: Linux 6.12.20 Wi-Fi Driver and FW version = SDIW612---w9177o-V1, SDIO, FP99, 18.99.3.p25.7-MM6X18537.p9-GPL-(FP92) As a reference, you can also test on other NXP's Wi-Fi products based on Linux OS.   Best regards, Christine.
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NXP wireless solutions build upon decades of Wi-Fi, Bluetooth®, multiprotocol silicon, software and system design expertise, including 802.15.4 in the latest tri-radio architectures. NXP is committed to driving large-scale deployment across multiple markets by a broad array of power- and cost-optimized Wi-Fi, Bluetooth and 802.15.4 transceivers, enabling products with advanced Wi-Fi and multiradio capabilities including Wi-Fi 4, Wi-Fi 5 and Wi-Fi 6 chips.   Market Product Wi-Fi Spec Wi-Fi Support Summary  IoT IW623 802.11ax (Wi-Fi 6E) 2x2 Tri-band (2.4G/5/7 GHz) + 1x1 Single Band (2.4 GHz) supports Wi-Fi 6E, with a high-performance 2x2 tri-band module for fast and flexible connectivity, plus an extra 1x1 2.4 GHz module likely for compatibility or low-power tasks IoT IW693 802.11ax (Wi-Fi 6/6E) CDW 2x2 Dual Band (5-7 GHz) + 1x1 Single Band (2.4 GHz) High-speed, low-latency connectivity on modern bands (5 and 6 GHz). Compatibility with older devices via 2.4 GHz A 2x2 MIMO setup for better performance, plus a 1x1 fallback for basic connections IoT IW610 802.11ax (Wi-Fi 6) 1x1 DB (2.4/5 GHz)   IoT IW612 802.11ax (Wi-Fi 6) 1x1 DB (2.4/5 GHz)   IoT IW611 802.11ax (Wi-Fi 6) 1x1 DB (2.4/5 GHz)   IoT IW620 802.11ax (Wi-Fi 6) 2x2 DB (2.4/5 GHz)   IoT IW416 802.11n (Wi-Fi 4) 1x1 DB (2.4/5 GHz)       Markets Product Wi-Fi Spec Wi-Fi Support Summary Wireless MCU Hostless RW612 802.11ax (Wi-Fi 6) 1x1 DB (2.4/5 GHz) supports Wi-Fi 6, has a single antenna (1x1), and can connect to both 2.4 GHz and 5 GHz networks. Wireless MCU Hostless RW610 802.11ax (Wi-Fi 6) 1x1 DB (2.4/5 GHz) supports Wi-Fi 6, has a single antenna (1x1), and can connect to both 2.4 GHz and 5 GHz networks.   Markets Product Wi-Fi Spec Wi-Fi Support Automotive AW692 802.11ax (Wi-Fi 6) 2x2 + 1x1 CDW DB (2.4/5GHz + 2.4Ghz) Automotive AW693 802.11ax (Wi-Fi 6E) 2x2 + 1x1 CDW TB (2.4/5/6Ghz + 2.4Ghz) Automotive AW611 802.11ax (Wi-Fi 6) 1x1 DB (2.4/5 GHz) Automotive AW690 802.11ax (Wi-Fi 6) 1x1 CDW DB (2.4/5 GHz)   Wireless Module Partners Leading wireless connectivity solution providers offer NXP wireless modules in their wireless connectivity solutions. Module manufacturers develop Wi-Fi modules using NXP’s broad portfolio of Wi-Fi chips (system-on-chip (SoC)), including Wi-Fi 6 chips, Wi-Fi and Bluetooth® combo integrated circuits (ICs) and tri-radio SoCs with 802.15.4. NXP enables a broad range of wireless applications with an ecosystem of wireless module partners.   Why Use a Module Vendor? Accelerate time-to-market Avoid the complexity of RF design and testing Ensure regulatory compliance more easily (e.g. FCC, CE, ISED) Focus on the host product’s functionality while relying on the vendor for wireless performance   Useful Links Wi-Fi Basic concepts: This post provides information about the different terms used in Wi-Fi, 802.11 standards and the three types of 802.11 MAC frames. Wi-Fi Security Concepts: This post covers the security and authentication processes  Wi-Fi Connection/Disconnection process: In 802.11 standards, the connection procedure includes three major steps that shall be performed to make the device part of the Wi-Fi network and communicate in the network. Wi-Fi Software Drivers Locations: NXP Recommends using Wi-Fi source code drivers WiFi_BT_Integretation-(Linux_BSP_compilation_for_iMX_platform): This article describes how to compile the Linux BSP of the i.MX platform under ubuntu 18.04, 20.04 LTS and debian-10. This is a necessary step to integrate WIFI/BT to the I.MX platform. See the attachment for detailed steps. Enabling i.MX8MP-EVK uSDHC1 M.2 for Wi-Fi on Android-11.0.0_2.6.0: Detailed steps on enabling usdhc1 NXP Wi-Fi and Bluetooth Product:  The article will introduce how to build Wi-Fi Mass Market Driver Wi-Fi Firmware Automatic Recovery on RW61x: This article introduces the Wi-Fi automatic recovery feature as well as how to enable and verify it on RW61x SDK. Access Point Wi-Fi configuration on i.MX8 Family: This guide explains how to achieve that, using the i.MX8M Plus EVK (8MP) as the AP device and the i.MX8M Mini EVK (8MM) as the connected device. How to connect to a Wi-Fi network on i.MX8MP: this article guides you step by step how to connect to a Wi-Fi network NXP Wi-Fi/Bluetooth firmware on the i.MX8M series: steps to replace Wi-Fi/Bluetooth firmware on the i.MX8M series on Linux Enabling Wi-Fi on Zephyr projects with the FRDM-RW612: In this guide, we'll modify the mqtt_publisher example—originally designed for Ethernet—to work with Wi-Fi instead Training FRDM-iMX91 connectivity Wi-Fi Basic Hands-on FRDM-iMX91 connectivity Wi-Fi Bluetooth LE and OT COEX RW612/MCXW71 - Wi-Fi and thread border router Training FRDM-RW612 Getting Started, Wi-Fi CLI on VScode Community Support If you have questions regarding this training, please leave your comments in our Wireless MCU Community! here 
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Matter is the industry-unifying standard from the Connectivity Standards Alliance that is delivering reliable, secure and interoperable connectivity for smart home devices, ensuring that they will work seamlessly together, today and tomorrow. From connectivity to security, processing and software, NXP offers complete end-to-end solutions for accelerating the development of Matter-enabled devices and is focused on helping our customers overcome the complexity and challenges that come with developing around this game-changing technology.   Getting Started Our investment in Matter starts with easing the development experience for adopting Matter in existing or new designs. With the breadth and scale of our portfolios, we scale to the system level to enable the autonomous edge - bringing intelligence to the edge. This approach provides developers with integrated platforms for the processing, connectivity and security requirements to go from prototype to production faster.   Matter Open-Source Protocol Compatible Products    Matter (previously known as Project CHIP) is a single, unified, application-layer connectivity standard designed to enable developers to connect and build reliable, secure IoT ecosystems and increase compatibility among Smart Home and Building devices. Backed by major brands and developed through collaboration within the Connectivity Standards Alliance (previously known as the Zigbee Alliance), Matter is an open-source royalty-free connectivity standard built with market-proven technologies using Internet Protocol (IP) and compatible with Thread and Wi-Fi network transports.   Useful Links   Getting Started with MCUXpresso for VS Code: Matter on Windows (24.12.71) MCUXpresso extension for VS Code v24.12.71 integrates the Matter toolchain for development on Windows, macOS and Linux.    Understanding Matter Terminology   Matter Is What's Cooking and NXP Has All the Right Ingredients     Matter GitHub Links    Releases Matter 
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Board pictures (KW47-M2) Connectors (KW47-M2) Part Identifier Connector Type Description J3 2x5 pin header SWD DNP J8 1x6 pin header UART1 – FTDI DNP J9 1x6 pin header Power connector DNP Jumpers (KW47-M2) Part Identifier Connector Type Description JP5 2x3 pin header supply power source selection jumper: 1-2 shorted (default configuration): Use this configuration to set target MCU in DCDC mode.  3-4 shorted: Use this configuration to set target MCU in LDO/Bypass mode. All MCU power domains are supplied by P3V3_DUT.  JP4 1x2 pin header Target MCU boot configuration enable jumper: • Open (default setting): ISP mode is disabled • Shorted: ISP mode is enabled Push Buttons (KW47-M2) Part Identifier Switch name Description SW1 Reset button Resets the target MCU. This causes peripherals to reset to their default state. After this, MCU ROM bootloader will be executed. LED D1 turns on at SW1 press. SW2 User PB General purpose input. This pin supports low-power wakeup capabilities through Wake-Up Unit (WUU). LEDs (KW47-M2) Part Identifier Switch name Description D1 Reset LED Indicates a system reset event. When reset is triggered—such as by pressing the SW1 reset button—the D1 LED turns ON. D2 Led Green User indicator, indicates system activity   Power Configurations (KW47-M2) Populate J9 PWR connector. To run KW47 M2 as standalone, supply 3.3V to P3V3_DUT power rail Figure 1 J9 M10 Configuration (KW47-M2)   To get the KW47 M2 up and running, you need to select a power configuration through JP5 jumper. For more information on KW47 power configurations, refer to RM: Part Identifier pin Description JP5 1-2 1-2 shorted (default setting): Sets target MCU to DCDC mode. This mode is the recommended configuration. JP5 3-4 3-4 shorted: Sets target MCU to LDO mode.     External power configuration (KW47-M2) Enable KW47-M2 by supplying power through J9 connector: Note: When using DCDC or LDO mode, it is recommended to supply P3V3_DUT power rail only. Part Identifier pin Description J9 5 Use this pin to supply P3V3_DUT power rail with 3.3V. To get KW47-M2 up and running, it is recommended to set KW47 to DCDC mode and supply P3V3_DUT only. J9 3 Use this pin to supply P1V8_LDO power rail with 1.8V. This power rail is intended for an accurate control of VDD_RF power domain, but it is not necessary. J9 1 Use this pin to supply P1V1_EXT power rail with 1.1V. This power rail is intended for an accurate control of VDD_CORE power domain, but it is not necessary.     Programming the NBU in the KW47-M2 board The following steps guide you to program the NBU software for the KW47-M2 Place a jumper on the JP4 header while holding down the reset button (SW) on the module board. Then, connect the USB cable to the J8 connector (USB-to-serial bridge) and plug it into your computer. After the USB cable is connected, release the reset button.   Verify what COM Port was assigned to your KW47-M2 board. You can check the COM Port assigned in the Windows “Device Manager” program. Search for “Ports (COM & LPT)” and save the COM Port number. In this example the COM Port assigned was “COM19”   Navigate to your computer to the MCU-Link installation folder. The default installation path is located at “C:\nxp\LinkServer_25.3.31\MCU-LINK_installer Locate the “bin” folder and open it. Run the script “blhost” within a windows command prompt.   Type “blhost.exe -p COMX write-memory 0x48800000”, drag and drop the NBU binary file. When the process is ready you will see the response status "success"  
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